dev: Move network devices to src/dev/net/

--HG--
rename : src/dev/Ethernet.py => src/dev/net/Ethernet.py
rename : src/dev/etherbus.cc => src/dev/net/etherbus.cc
rename : src/dev/etherbus.hh => src/dev/net/etherbus.hh
rename : src/dev/etherdevice.cc => src/dev/net/etherdevice.cc
rename : src/dev/etherdevice.hh => src/dev/net/etherdevice.hh
rename : src/dev/etherdump.cc => src/dev/net/etherdump.cc
rename : src/dev/etherdump.hh => src/dev/net/etherdump.hh
rename : src/dev/etherint.cc => src/dev/net/etherint.cc
rename : src/dev/etherint.hh => src/dev/net/etherint.hh
rename : src/dev/etherlink.cc => src/dev/net/etherlink.cc
rename : src/dev/etherlink.hh => src/dev/net/etherlink.hh
rename : src/dev/etherobject.hh => src/dev/net/etherobject.hh
rename : src/dev/etherpkt.cc => src/dev/net/etherpkt.cc
rename : src/dev/etherpkt.hh => src/dev/net/etherpkt.hh
rename : src/dev/ethertap.cc => src/dev/net/ethertap.cc
rename : src/dev/ethertap.hh => src/dev/net/ethertap.hh
rename : src/dev/i8254xGBe.cc => src/dev/net/i8254xGBe.cc
rename : src/dev/i8254xGBe.hh => src/dev/net/i8254xGBe.hh
rename : src/dev/i8254xGBe_defs.hh => src/dev/net/i8254xGBe_defs.hh
rename : src/dev/multi_etherlink.cc => src/dev/net/multi_etherlink.cc
rename : src/dev/multi_etherlink.hh => src/dev/net/multi_etherlink.hh
rename : src/dev/multi_iface.cc => src/dev/net/multi_iface.cc
rename : src/dev/multi_iface.hh => src/dev/net/multi_iface.hh
rename : src/dev/multi_packet.cc => src/dev/net/multi_packet.cc
rename : src/dev/multi_packet.hh => src/dev/net/multi_packet.hh
rename : src/dev/ns_gige.cc => src/dev/net/ns_gige.cc
rename : src/dev/ns_gige.hh => src/dev/net/ns_gige.hh
rename : src/dev/ns_gige_reg.h => src/dev/net/ns_gige_reg.h
rename : src/dev/pktfifo.cc => src/dev/net/pktfifo.cc
rename : src/dev/pktfifo.hh => src/dev/net/pktfifo.hh
rename : src/dev/sinic.cc => src/dev/net/sinic.cc
rename : src/dev/sinic.hh => src/dev/net/sinic.hh
rename : src/dev/sinicreg.hh => src/dev/net/sinicreg.hh
rename : src/dev/tcp_iface.cc => src/dev/net/tcp_iface.cc
rename : src/dev/tcp_iface.hh => src/dev/net/tcp_iface.hh
This commit is contained in:
Andreas Sandberg 2015-12-10 10:35:18 +00:00
parent ef097ac438
commit 23c961a0fd
40 changed files with 239 additions and 164 deletions

View file

@ -53,7 +53,7 @@
#include <vector>
#include "base/types.hh"
#include "dev/etherpkt.hh"
#include "dev/net/etherpkt.hh"
#include "dnet/os.h"
#include "dnet/eth.h"
#include "dnet/ip.h"

View file

@ -41,7 +41,6 @@ if env['TARGET_ISA'] == 'null':
SimObject('BadDevice.py')
SimObject('DiskImage.py')
SimObject('Ethernet.py')
SimObject('Ide.py')
SimObject('Platform.py')
SimObject('SimpleDisk.py')
@ -51,29 +50,14 @@ SimObject('Uart.py')
Source('baddev.cc')
Source('disk_image.cc')
Source('dma_device.cc')
Source('etherbus.cc')
Source('etherdevice.cc')
Source('etherdump.cc')
Source('etherint.cc')
Source('etherlink.cc')
Source('multi_packet.cc')
Source('multi_iface.cc')
Source('multi_etherlink.cc')
Source('tcp_iface.cc')
Source('etherpkt.cc')
Source('ethertap.cc')
Source('i8254xGBe.cc')
Source('ide_ctrl.cc')
Source('ide_disk.cc')
Source('intel_8254_timer.cc')
Source('mc146818.cc')
Source('ns_gige.cc')
Source('pixelpump.cc')
Source('pktfifo.cc')
Source('platform.cc')
Source('ps2.cc')
Source('simple_disk.cc')
Source('sinic.cc')
Source('terminal.cc')
Source('uart.cc')
Source('uart8250.cc')
@ -81,17 +65,6 @@ Source('uart8250.cc')
DebugFlag('DiskImageRead')
DebugFlag('DiskImageWrite')
DebugFlag('DMA')
DebugFlag('Ethernet')
DebugFlag('MultiEthernet')
DebugFlag('MultiEthernetPkt')
DebugFlag('EthernetCksum')
DebugFlag('EthernetDMA')
DebugFlag('EthernetData')
DebugFlag('EthernetDesc')
DebugFlag('EthernetEEPROM')
DebugFlag('EthernetIntr')
DebugFlag('EthernetPIO')
DebugFlag('EthernetSM')
DebugFlag('IdeCtrl')
DebugFlag('IdeDisk')
DebugFlag('Intel8254Timer')
@ -103,9 +76,4 @@ DebugFlag('TerminalVerbose')
DebugFlag('Uart')
CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
'EthernetCksum', 'EthernetEEPROM' ])
CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])

View file

@ -46,11 +46,11 @@ from PciDevice import PciDevice
class EtherObject(SimObject):
type = 'EtherObject'
abstract = True
cxx_header = "dev/etherobject.hh"
cxx_header = "dev/net/etherobject.hh"
class EtherLink(EtherObject):
type = 'EtherLink'
cxx_header = "dev/etherlink.hh"
cxx_header = "dev/net/etherlink.hh"
int0 = SlavePort("interface 0")
int1 = SlavePort("interface 1")
delay = Param.Latency('0us', "packet transmit delay")
@ -60,7 +60,7 @@ class EtherLink(EtherObject):
class MultiEtherLink(EtherObject):
type = 'MultiEtherLink'
cxx_header = "dev/multi_etherlink.hh"
cxx_header = "dev/net/multi_etherlink.hh"
int0 = SlavePort("interface 0")
delay = Param.Latency('0us', "packet transmit delay")
delay_var = Param.Latency('0ns', "packet transmit delay variability")
@ -74,34 +74,34 @@ class MultiEtherLink(EtherObject):
class EtherBus(EtherObject):
type = 'EtherBus'
cxx_header = "dev/etherbus.hh"
cxx_header = "dev/net/etherbus.hh"
loopback = Param.Bool(True, "send packet back to the sending interface")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
class EtherTap(EtherObject):
type = 'EtherTap'
cxx_header = "dev/ethertap.hh"
cxx_header = "dev/net/ethertap.hh"
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
port = Param.UInt16(3500, "tap port")
class EtherDump(SimObject):
type = 'EtherDump'
cxx_header = "dev/etherdump.hh"
cxx_header = "dev/net/etherdump.hh"
file = Param.String("dump file")
maxlen = Param.Int(96, "max portion of packet data to dump")
class EtherDevice(PciDevice):
type = 'EtherDevice'
abstract = True
cxx_header = "dev/etherdevice.hh"
cxx_header = "dev/net/etherdevice.hh"
interface = MasterPort("Ethernet Interface")
class IGbE(EtherDevice):
# Base class for two IGbE adapters listed above
type = 'IGbE'
cxx_header = "dev/i8254xGBe.hh"
cxx_header = "dev/net/i8254xGBe.hh"
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
@ -154,7 +154,7 @@ class IGbE_igb(IGbE):
class EtherDevBase(EtherDevice):
type = 'EtherDevBase'
abstract = True
cxx_header = "dev/etherdevice.hh"
cxx_header = "dev/net/etherdevice.hh"
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
@ -177,7 +177,7 @@ class EtherDevBase(EtherDevice):
class NSGigE(EtherDevBase):
type = 'NSGigE'
cxx_header = "dev/ns_gige.hh"
cxx_header = "dev/net/ns_gige.hh"
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
@ -207,7 +207,7 @@ class NSGigE(EtherDevBase):
class Sinic(EtherDevBase):
type = 'Sinic'
cxx_class = 'Sinic::Device'
cxx_header = "dev/sinic.hh"
cxx_header = "dev/net/sinic.hh"
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")

94
src/dev/net/SConscript Normal file
View file

@ -0,0 +1,94 @@
# -*- mode:python -*-
# Copyright (c) 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
# Gabe Black
# Andreas Sandberg
Import('*')
if env['TARGET_ISA'] == 'null':
Return()
SimObject('Ethernet.py')
# Basic Ethernet infrastructure
Source('etherbus.cc')
Source('etherdevice.cc')
Source('etherdump.cc')
Source('etherint.cc')
Source('etherlink.cc')
Source('etherpkt.cc')
Source('ethertap.cc')
Source('pktfifo.cc')
DebugFlag('Ethernet')
DebugFlag('EthernetCksum')
DebugFlag('EthernetDMA')
DebugFlag('EthernetData')
DebugFlag('EthernetDesc')
DebugFlag('EthernetEEPROM')
DebugFlag('EthernetIntr')
DebugFlag('EthernetPIO')
DebugFlag('EthernetSM')
# Multi gem5
Source('multi_packet.cc')
Source('multi_iface.cc')
Source('multi_etherlink.cc')
Source('tcp_iface.cc')
DebugFlag('MultiEthernet')
DebugFlag('MultiEthernetPkt')
# Ethernet controllers
Source('i8254xGBe.cc')
Source('ns_gige.cc')
Source('sinic.cc')
CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
'EthernetCksum', 'EthernetEEPROM' ])
CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])

View file

@ -31,6 +31,7 @@
/* @file
* Device module for modelling an ethernet hub
*/
#include "dev/net/etherbus.hh"
#include <cmath>
#include <deque>
@ -40,10 +41,9 @@
#include "base/trace.hh"
#include "debug/Ethernet.hh"
#include "debug/EthernetData.hh"
#include "dev/etherbus.hh"
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/net/etherdump.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherpkt.hh"
#include "params/EtherBus.hh"
#include "sim/core.hh"

View file

@ -32,11 +32,11 @@
* Device module for modelling an ethernet hub
*/
#ifndef __ETHERBUS_H__
#define __ETHERBUS_H__
#ifndef __DEV_NET_ETHERBUS_HH__
#define __DEV_NET_ETHERBUS_HH__
#include "dev/etherobject.hh"
#include "dev/etherpkt.hh"
#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#include "params/EtherBus.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
@ -87,4 +87,4 @@ class EtherBus : public EtherObject
virtual EtherInt *getEthPort(const std::string &if_name, int idx);
};
#endif // __ETHERBUS_H__
#endif // __DEV_NET_ETHERBUS_HH__

View file

@ -29,7 +29,8 @@
* Lisa Hsu
*/
#include "dev/etherdevice.hh"
#include "dev/net/etherdevice.hh"
#include "sim/stats.hh"
void

View file

@ -33,13 +33,13 @@
* Base Ethernet Device declaration.
*/
#ifndef __DEV_ETHERDEVICE_HH__
#define __DEV_ETHERDEVICE_HH__
#ifndef __DEV_NET_ETHERDEVICE_HH__
#define __DEV_NET_ETHERDEVICE_HH__
#include "base/statistics.hh"
#include "dev/pci/device.hh"
#include "params/EtherDevice.hh"
#include "params/EtherDevBase.hh"
#include "params/EtherDevice.hh"
#include "sim/sim_object.hh"
class EtherInt;
@ -148,4 +148,5 @@ class EtherDevBase : public EtherDevice
};
#endif //__DEV_ETHERDEVICE_HH__
#endif // __DEV_NET_ETHERDEVICE_HH__

View file

@ -31,6 +31,7 @@
/* @file
* Simple object for creating a simple pcap style packet trace
*/
#include "dev/net/etherdump.hh"
#include <sys/time.h>
@ -39,7 +40,6 @@
#include "base/misc.hh"
#include "base/output.hh"
#include "dev/etherdump.hh"
#include "sim/core.hh"
using std::string;

View file

@ -32,12 +32,12 @@
* Simple object for creating a simple pcap style packet trace
*/
#ifndef __ETHERDUMP_H__
#define __ETHERDUMP_H__
#ifndef __DEV_NET_ETHERDUMP_HH__
#define __DEV_NET_ETHERDUMP_HH__
#include <fstream>
#include "dev/etherpkt.hh"
#include "dev/net/etherpkt.hh"
#include "params/EtherDump.hh"
#include "sim/sim_object.hh"
@ -59,4 +59,4 @@ class EtherDump : public SimObject
inline void dump(EthPacketPtr &pkt) { dumpPacket(pkt); }
};
#endif // __ETHERDUMP_H__
#endif // __DEV_NET_ETHERDUMP_HH__

View file

@ -28,8 +28,9 @@
* Authors: Nathan Binkert
*/
#include "dev/net/etherint.hh"
#include "base/misc.hh"
#include "dev/etherint.hh"
#include "sim/sim_object.hh"
void

View file

@ -33,12 +33,12 @@
* components.
*/
#ifndef __DEV_ETHERINT_HH__
#define __DEV_ETHERINT_HH__
#ifndef __DEV_NET_ETHERINT_HH__
#define __DEV_NET_ETHERINT_HH__
#include <string>
#include "dev/etherpkt.hh"
#include "dev/net/etherpkt.hh"
/*
* Class representing the actual interface between two ethernet
@ -73,4 +73,4 @@ class EtherInt
virtual bool isBusy() { return false; }
};
#endif // __DEV_ETHERINT_HH__
#endif // __DEV_NET_ETHERINT_HH__

View file

@ -45,6 +45,8 @@
* Device module for modelling a fixed bandwidth full duplex ethernet link
*/
#include "dev/net/etherlink.hh"
#include <cmath>
#include <deque>
#include <string>
@ -54,10 +56,9 @@
#include "base/trace.hh"
#include "debug/Ethernet.hh"
#include "debug/EthernetData.hh"
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherlink.hh"
#include "dev/etherpkt.hh"
#include "dev/net/etherdump.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherpkt.hh"
#include "params/EtherLink.hh"
#include "sim/core.hh"
#include "sim/serialize.hh"

View file

@ -44,15 +44,15 @@
* Device module for modelling a fixed bandwidth full duplex ethernet link
*/
#ifndef __DEV_ETHERLINK_HH__
#define __DEV_ETHERLINK_HH__
#ifndef __DEV_NET_ETHERLINK_HH__
#define __DEV_NET_ETHERLINK_HH__
#include <queue>
#include "base/types.hh"
#include "dev/etherint.hh"
#include "dev/etherobject.hh"
#include "dev/etherpkt.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#include "params/EtherLink.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
@ -163,4 +163,4 @@ class EtherLink : public EtherObject
};
#endif // __ETHERLINK_HH__
#endif // __DEV_NET_ETHERLINK_HH__

View file

@ -33,8 +33,8 @@
* Base Ethernet Object declaration.
*/
#ifndef __DEV_ETHEROBJECT_HH__
#define __DEV_ETHEROBJECT_HH__
#ifndef __DEV_NET_ETHEROBJECT_HH__
#define __DEV_NET_ETHEROBJECT_HH__
#include "params/EtherObject.hh"
#include "sim/sim_object.hh"
@ -64,4 +64,4 @@ class EtherObject : public SimObject
};
#endif //__MEM_MEM_OBJECT_HH__
#endif // __DEV_NET_ETHEROBJECT_HH__

View file

@ -28,11 +28,12 @@
* Authors: Nathan Binkert
*/
#include "dev/net/etherpkt.hh"
#include <iostream>
#include "base/misc.hh"
#include "base/inet.hh"
#include "dev/etherpkt.hh"
#include "base/misc.hh"
#include "sim/serialize.hh"
using namespace std;

View file

@ -33,8 +33,8 @@
* Reference counted class containing ethernet packet data
*/
#ifndef __ETHERPKT_HH__
#define __ETHERPKT_HH__
#ifndef __DEV_NET_ETHERPKT_HH__
#define __DEV_NET_ETHERPKT_HH__
#include <cassert>
#include <iosfwd>
@ -92,4 +92,4 @@ class EthPacketData
typedef std::shared_ptr<EthPacketData> EthPacketPtr;
#endif // __ETHERPKT_HH__
#endif // __DEV_NET_ETHERPKT_HH__

View file

@ -32,8 +32,11 @@
* Interface to connect a simulated ethernet device to the real world
*/
#include "dev/net/ethertap.hh"
#if defined(__OpenBSD__) || defined(__APPLE__)
#include <sys/param.h>
#endif
#include <netinet/in.h>
#include <unistd.h>
@ -47,10 +50,9 @@
#include "base/trace.hh"
#include "debug/Ethernet.hh"
#include "debug/EthernetData.hh"
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/ethertap.hh"
#include "dev/net/etherdump.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherpkt.hh"
using namespace std;

View file

@ -32,16 +32,16 @@
* Interface to connect a simulated ethernet device to the real world
*/
#ifndef __ETHERTAP_HH__
#define __ETHERTAP_HH__
#ifndef __DEV_NET_ETHERTAP_HH__
#define __DEV_NET_ETHERTAP_HH__
#include <queue>
#include <string>
#include "base/pollevent.hh"
#include "dev/etherint.hh"
#include "dev/etherobject.hh"
#include "dev/etherpkt.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#include "params/EtherTap.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
@ -133,4 +133,4 @@ class EtherTapInt : public EtherInt
};
#endif // __ETHERTAP_HH__
#endif // __DEV_NET_ETHERTAP_HH__

View file

@ -35,6 +35,7 @@
* other MACs with slight modifications.
*/
#include "dev/net/i8254xGBe.hh"
/*
* @todo really there are multiple dma engines.. we should implement them.
@ -47,7 +48,6 @@
#include "base/trace.hh"
#include "debug/Drain.hh"
#include "debug/EthernetAll.hh"
#include "dev/i8254xGBe.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/IGbE.hh"

View file

@ -32,8 +32,8 @@
* Device model for Intel's 8254x line of gigabit ethernet controllers.
*/
#ifndef __DEV_I8254XGBE_HH__
#define __DEV_I8254XGBE_HH__
#ifndef __DEV_NET_I8254XGBE_HH__
#define __DEV_NET_I8254XGBE_HH__
#include <deque>
#include <string>
@ -42,12 +42,12 @@
#include "base/inet.hh"
#include "debug/EthernetDesc.hh"
#include "debug/EthernetIntr.hh"
#include "dev/etherdevice.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/i8254xGBe_defs.hh"
#include "dev/net/etherdevice.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherpkt.hh"
#include "dev/net/i8254xGBe_defs.hh"
#include "dev/net/pktfifo.hh"
#include "dev/pci/device.hh"
#include "dev/pktfifo.hh"
#include "params/IGbE.hh"
#include "sim/eventq.hh"
@ -557,4 +557,4 @@ class IGbEInt : public EtherInt
virtual void sendDone() { dev->ethTxDone(); }
};
#endif //__DEV_I8254XGBE_HH__
#endif //__DEV_NET_I8254XGBE_HH__

View file

@ -41,7 +41,7 @@
* Device module for a full duplex ethernet link for multi gem5 simulations.
*/
#include "dev/multi_etherlink.hh"
#include "dev/net/multi_etherlink.hh"
#include <arpa/inet.h>
#include <sys/socket.h>
@ -57,13 +57,13 @@
#include "debug/EthernetData.hh"
#include "debug/MultiEthernet.hh"
#include "debug/MultiEthernetPkt.hh"
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherlink.hh"
#include "dev/etherobject.hh"
#include "dev/etherpkt.hh"
#include "dev/multi_iface.hh"
#include "dev/tcp_iface.hh"
#include "dev/net/etherdump.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherlink.hh"
#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#include "dev/net/multi_iface.hh"
#include "dev/net/tcp_iface.hh"
#include "params/EtherLink.hh"
#include "sim/core.hh"
#include "sim/serialize.hh"

View file

@ -47,12 +47,12 @@
* multi gem5 runs.
*
*/
#ifndef __DEV_MULTIETHERLINK_HH__
#define __DEV_MULTIETHERLINK_HH__
#ifndef __DEV_NET_MULTIETHERLINK_HH__
#define __DEV_NET_MULTIETHERLINK_HH__
#include <iostream>
#include "dev/etherlink.hh"
#include "dev/net/etherlink.hh"
#include "params/MultiEtherLink.hh"
class MultiIface;
@ -232,4 +232,4 @@ class MultiEtherLink : public EtherObject
void unserialize(CheckpointIn &cp) override;
};
#endif // __DEV_MULTIETHERLINK_HH__
#endif // __DEV_NET_MULTIETHERLINK_HH__

View file

@ -41,7 +41,7 @@
* The interface class for multi gem5 simulations.
*/
#include "dev/multi_iface.hh"
#include "dev/net/multi_iface.hh"
#include <queue>
#include <thread>
@ -50,7 +50,7 @@
#include "base/trace.hh"
#include "debug/MultiEthernet.hh"
#include "debug/MultiEthernetPkt.hh"
#include "dev/etherpkt.hh"
#include "dev/net/etherpkt.hh"
#include "sim/sim_exit.hh"
#include "sim/sim_object.hh"

View file

@ -75,8 +75,8 @@
* send/receive service implementations (e.g. TCP/IP, MPI,...). A TCP
* stream socket version is implemented in dev/src/tcp_iface.[hh,cc].
*/
#ifndef __DEV_MULTI_IFACE_HH__
#define __DEV_MULTI_IFACE_HH__
#ifndef __DEV_NET_MULTI_IFACE_HH__
#define __DEV_NET_MULTI_IFACE_HH__
#include <array>
#include <mutex>
@ -84,8 +84,8 @@
#include <thread>
#include <utility>
#include "dev/etherpkt.hh"
#include "dev/multi_packet.hh"
#include "dev/net/etherpkt.hh"
#include "dev/net/multi_packet.hh"
#include "sim/core.hh"
#include "sim/drain.hh"
#include "sim/global_event.hh"
@ -489,4 +489,4 @@ class MultiIface : public Drainable
};
#endif
#endif // __DEV_NET_MULTI_IFACE_HH__

View file

@ -42,7 +42,7 @@
*
*/
#include "dev/multi_packet.hh"
#include "dev/net/multi_packet.hh"
#include <cstdint>
#include <cstring>

View file

@ -50,8 +50,8 @@
* data packet description, the corresponding data packet always follows
* the header packet back-to-back.
*/
#ifndef __DEV_MULTI_PACKET_HH__
#define __DEV_MULTI_PACKET_HH__
#ifndef __DEV_NET_MULTI_PACKET_HH__
#define __DEV_NET_MULTI_PACKET_HH__
#include <cstring>
@ -127,4 +127,4 @@ class MultiHeaderPkt
static bool isBroadcastAddress(const AddressType &addr);
};
#endif
#endif // __DEV_NET_MULTI_PACKET_HH__

View file

@ -33,6 +33,9 @@
* Device module for modelling the National Semiconductor
* DP83820 ethernet controller. Does not support priority queueing
*/
#include "dev/net/ns_gige.hh"
#include <deque>
#include <memory>
#include <string>
@ -42,8 +45,7 @@
#include "base/types.hh"
#include "config/the_isa.hh"
#include "debug/EthernetAll.hh"
#include "dev/etherlink.hh"
#include "dev/ns_gige.hh"
#include "dev/net/etherlink.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/NSGigE.hh"

View file

@ -34,16 +34,16 @@
* DP83820 ethernet controller
*/
#ifndef __DEV_NS_GIGE_HH__
#define __DEV_NS_GIGE_HH__
#ifndef __DEV_NET_NS_GIGE_HH__
#define __DEV_NET_NS_GIGE_HH__
#include "base/inet.hh"
#include "dev/etherdevice.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/io_device.hh"
#include "dev/ns_gige_reg.h"
#include "dev/pktfifo.hh"
#include "dev/net/etherdevice.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherpkt.hh"
#include "dev/net/ns_gige_reg.h"
#include "dev/net/pktfifo.hh"
#include "params/NSGigE.hh"
#include "sim/eventq.hh"
@ -389,4 +389,4 @@ class NSGigEInt : public EtherInt
virtual void sendDone() { dev->transferDone(); }
};
#endif // __DEV_NS_GIGE_HH__
#endif // __DEV_NET_NS_GIGE_HH__

View file

@ -28,8 +28,9 @@
* Authors: Nathan Binkert
*/
#include "dev/net/pktfifo.hh"
#include "base/misc.hh"
#include "dev/pktfifo.hh"
using namespace std;

View file

@ -28,14 +28,15 @@
* Authors: Nathan Binkert
*/
#ifndef __DEV_PKTFIFO_HH__
#define __DEV_PKTFIFO_HH__
#ifndef __DEV_NET_PKTFIFO_HH__
#define __DEV_NET_PKTFIFO_HH__
#include <iosfwd>
#include <list>
#include <string>
#include "dev/etherpkt.hh"
#include "base/misc.hh"
#include "dev/net/etherpkt.hh"
#include "sim/serialize.hh"
class Checkpoint;
@ -208,4 +209,4 @@ class PacketFifo
void unserialize(const std::string &base, CheckpointIn &cp);
};
#endif // __DEV_PKTFIFO_HH__
#endif // __DEV_NET_PKTFIFO_HH__

View file

@ -28,12 +28,15 @@
* Authors: Nathan Binkert
*/
#include "dev/net/sinic.hh"
#include <deque>
#include <limits>
#include <string>
#ifdef SINIC_VTOPHYS
#include "arch/vtophys.hh"
#endif
#include "base/compiler.hh"
#include "base/debug.hh"
@ -41,8 +44,7 @@
#include "base/types.hh"
#include "config/the_isa.hh"
#include "debug/EthernetAll.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
#include "dev/net/etherlink.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"

View file

@ -28,18 +28,18 @@
* Authors: Nathan Binkert
*/
#ifndef __DEV_SINIC_HH__
#define __DEV_SINIC_HH__
#ifndef __DEV_NET_SINIC_HH__
#define __DEV_NET_SINIC_HH__
#include "base/inet.hh"
#include "base/statistics.hh"
#include "dev/etherdevice.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/io_device.hh"
#include "dev/net/etherdevice.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherpkt.hh"
#include "dev/net/pktfifo.hh"
#include "dev/net/sinicreg.hh"
#include "dev/pci/device.hh"
#include "dev/pktfifo.hh"
#include "dev/sinicreg.hh"
#include "params/Sinic.hh"
#include "sim/eventq.hh"
@ -324,4 +324,4 @@ class Interface : public EtherInt
} // namespace Sinic
#endif // __DEV_SINIC_HH__
#endif // __DEV_NET_SINIC_HH__

View file

@ -28,8 +28,8 @@
* Authors: Nathan Binkert
*/
#ifndef __DEV_SINICREG_HH__
#define __DEV_SINICREG_HH__
#ifndef __DEV_NET_SINICREG_HH__
#define __DEV_NET_SINICREG_HH__
#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL);
#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL);
@ -236,4 +236,4 @@ regValid(Addr daddr)
} // namespace Sinic
#endif // __DEV_SINICREG_HH__
#endif // __DEV_NET_SINICREG_HH__

View file

@ -41,7 +41,7 @@
* TCP stream socket based interface class implementation for multi gem5 runs.
*/
#include "dev/tcp_iface.hh"
#include "dev/net/tcp_iface.hh"
#include <arpa/inet.h>
#include <netdb.h>

View file

@ -49,13 +49,13 @@
* transfers messages and co-ordinates the synchronisation among the gem5
* peers.
*/
#ifndef __DEV_TCP_IFACE_HH__
#define __DEV_TCP_IFACE_HH__
#ifndef __DEV_NET_TCP_IFACE_HH__
#define __DEV_NET_TCP_IFACE_HH__
#include <string>
#include "dev/multi_iface.hh"
#include "dev/net/multi_iface.hh"
class EventManager;
@ -130,4 +130,4 @@ class TCPIface : public MultiIface
~TCPIface() override;
};
#endif
#endif // __DEV_NET_TCP_IFACE_HH__

View file

@ -36,8 +36,8 @@
#include "base/output.hh"
#include "config/the_isa.hh"
#if THE_ISA != NULL_ISA
#include "dev/etherdevice.hh"
#include "dev/etherobject.hh"
#include "dev/net/etherdevice.hh"
#include "dev/net/etherobject.hh"
#endif
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/mem_object.hh"

View file

@ -31,7 +31,7 @@
#include <Python.h>
#include "base/types.hh"
#include "dev/etherint.hh"
#include "dev/net/etherint.hh"
#include "sim/serialize.hh"
#include "sim/sim_object.hh"