Radhika Jagtap 54519fd51f cpu: Support virtual addr in elastic traces ... This patch adds support to optionally capture the virtual address and asid for load/store instructions in the elastic traces. If they are present in the traces, Trace CPU will set those fields of the request during replay.		2015-12-07 16:42:16 -06:00
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arch	arm, config: Automatically discover available platforms	2015-12-04 00:19:05 +00:00
base	sim: Add support for generating back traces on errors	2015-12-04 00:12:58 +00:00
cpu	cpu: Support virtual addr in elastic traces	2015-12-07 16:42:16 -06:00
dev	dev: Rewrite PCI host functionality	2015-12-05 00:11:24 +00:00
doc	cpu: `Minor' in-order CPU model	2014-07-23 16:09:04 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	misc: Remove redundant compiler-specific defines	2015-10-12 04:07:59 -04:00
mem	cpu: Support virtual addr in elastic traces	2015-12-07 16:42:16 -06:00
proto	cpu: Support virtual addr in elastic traces	2015-12-07 16:42:16 -06:00
python	config: Fix broken SimObject listing	2015-12-01 13:01:05 +00:00
sim	sim: Get rid of the non-const serialize() method	2015-12-04 09:48:48 +00:00
unittest	base: Rewrite the CircleBuf to fix bugs and add serialization	2015-08-07 09:59:19 +01:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	sim: tag-based checkpoint versioning	2015-09-02 15:23:30 -05:00