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ruby: print addresses in hex

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Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements.  So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals.  This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address.  This function has been put to use in some of the
places.  At other places, change has been made to print just the address in
hex.
This commit is contained in:
Nilay Vaish 2015-09-18 13:27:47 -05:00
parent 216529bf18
commit 96c999fe88
22 changed files with 97 additions and 82 deletions
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8
src/mem/protocol/MESI_Three_Level-L0cache.sm
View file

@ -369,7 +369,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
out_msg.Class := CoherenceClass:GETS;
out_msg.Sender := machineID;
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@ -386,7 +386,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
DPRINTF(RubySlicc, "%s\n", machineID);
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@ -402,7 +402,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
out_msg.Sender := machineID;
out_msg.Dest := createMachineID(MachineType:L1Cache, version);
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@ -438,7 +438,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
if (send_evictions) {
DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}

10
src/mem/protocol/MESI_Three_Level-L1cache.sm
View file

@ -392,7 +392,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@ -409,7 +409,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
DPRINTF(RubySlicc, "%s\n", machineID);
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@ -425,7 +425,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
@ -580,7 +580,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
out_msg.MessageSize := MessageSizeType:Response_Control;
DPRINTF(RubySlicc, "%s\n", address);
DPRINTF(RubySlicc, "%#x\n", address);
}
}
@ -592,7 +592,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, clusterID));
out_msg.MessageSize := MessageSizeType:Response_Control;
DPRINTF(RubySlicc, "%s\n", address);
DPRINTF(RubySlicc, "%#x\n", address);
}
}

20
src/mem/protocol/MESI_Two_Level-L1cache.sm
View file

@ -528,7 +528,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@ -545,7 +545,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@ -562,7 +562,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@ -585,7 +585,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Prefetch := in_msg.Prefetch;
out_msg.AccessMode := in_msg.AccessMode;
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
}
}
@ -600,7 +600,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
DPRINTF(RubySlicc, "%s\n", machineID);
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@ -620,7 +620,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@ -637,7 +637,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
DPRINTF(RubySlicc, "address: %#x, destination: %s\n",
address, out_msg.Destination);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.Prefetch := in_msg.Prefetch;
@ -759,7 +759,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
if (send_evictions) {
DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}
@ -790,7 +790,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
out_msg.MessageSize := MessageSizeType:Response_Control;
DPRINTF(RubySlicc, "%s\n", address);
DPRINTF(RubySlicc, "%#x\n", address);
}
}
@ -802,7 +802,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
l2_select_low_bit, l2_select_num_bits, intToID(0)));
out_msg.MessageSize := MessageSizeType:Response_Control;
DPRINTF(RubySlicc, "%s\n", address);
DPRINTF(RubySlicc, "%#x\n", address);
}
}

10
src/mem/protocol/MESI_Two_Level-L2cache.sm
View file

@ -174,7 +174,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
void addSharer(Addr addr, MachineID requestor, Entry cache_entry) {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %#x\n",
machineID, requestor, addr);
cache_entry.Sharers.add(requestor);
}
@ -267,7 +267,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
return Event:L1_PUTX_old;
}
} else {
DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
DPRINTF(RubySlicc, "address: %#x, Request Type: %s\n", addr, type);
error("Invalid L1 forwarded request type");
}
}
@ -293,7 +293,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
peek(L1unblockNetwork_in, ResponseMsg) {
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
DPRINTF(RubySlicc, "Addr: %#x State: %s Sender: %s Type: %s Dest: %s\n",
in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Sender, in_msg.Type, in_msg.Destination);
@ -357,7 +357,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
Entry cache_entry := getCacheEntry(in_msg.addr);
TBE tbe := TBEs[in_msg.addr];
DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
DPRINTF(RubySlicc, "Addr: %#x State: %s Req: %s Type: %s Dest: %s\n",
in_msg.addr, getState(tbe, cache_entry, in_msg.addr),
in_msg.Requestor, in_msg.Type, in_msg.Destination);
@ -546,7 +546,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
out_msg.Destination.add(tbe.L1_GetX_ID);
DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
out_msg.DataBlk := cache_entry.DataBlk;
DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Destination: %s, DataBlock: %s\n",
out_msg.addr, out_msg.Destination, out_msg.DataBlk);
out_msg.MessageSize := MessageSizeType:Response_Data;
}

2
src/mem/protocol/MI_example-cache.sm
View file

@ -396,7 +396,7 @@ machine(L1Cache, "MI Example L1 Cache")
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
if (send_evictions) {
DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}

4
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
View file

@ -514,7 +514,7 @@ machine(L1Cache, "Directory protocol")
out_msg.Acks := in_msg.Acks;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.addr);
DPRINTF(RubySlicc, "Sending data to L2: %#x\n", in_msg.addr);
}
else {
enqueue(responseNetwork_out, ResponseMsg, request_latency) {
@ -889,7 +889,7 @@ machine(L1Cache, "Directory protocol")
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
if (send_evictions) {
DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}

22
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
View file

@ -797,7 +797,7 @@ machine(L2Cache, "Token protocol")
out_msg.Dirty := false;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
@ -814,7 +814,7 @@ machine(L2Cache, "Token protocol")
out_msg.Acks := tbe.Local_GETX_IntAcks;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
@ -864,7 +864,7 @@ machine(L2Cache, "Token protocol")
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
@ -883,7 +883,7 @@ machine(L2Cache, "Token protocol")
out_msg.Acks := tbe.Fwd_GETX_ExtAcks;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
@ -900,7 +900,7 @@ machine(L2Cache, "Token protocol")
out_msg.Acks := tbe.Fwd_GETX_ExtAcks;
out_msg.MessageSize := MessageSizeType:Response_Data;
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, tbe.DataBlk);
}
@ -920,7 +920,7 @@ machine(L2Cache, "Token protocol")
out_msg.MessageSize := MessageSizeType:ResponseL2hit_Data;
}
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
}
@ -940,7 +940,7 @@ machine(L2Cache, "Token protocol")
out_msg.Acks := tbe.Local_GETX_IntAcks;
}
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
}
@ -959,7 +959,7 @@ machine(L2Cache, "Token protocol")
out_msg.Acks := in_msg.Acks;
}
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
}
@ -980,7 +980,7 @@ machine(L2Cache, "Token protocol")
out_msg.MessageSize := MessageSizeType:Response_Data;
}
}
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
}
@ -1044,7 +1044,7 @@ machine(L2Cache, "Token protocol")
action(ee_sendLocalInv, "\ee", desc="Send local invalidates") {
assert(is_valid(tbe));
tbe.NumIntPendingAcks := countLocalSharers(cache_entry, address);
DPRINTF(RubySlicc, "Address: %s, Local Sharers: %s, Pending Acks: %d\n",
DPRINTF(RubySlicc, "Address: %#x, Local Sharers: %s, Pending Acks: %d\n",
address, getLocalSharers(cache_entry, address),
tbe.NumIntPendingAcks);
if (isLocalOwnerValid(cache_entry, address)) {
@ -1494,7 +1494,7 @@ machine(L2Cache, "Token protocol")
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
cache_entry.DataBlk := in_msg.DataBlk;
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
if ((cache_entry.Dirty == false) && in_msg.Dirty) {
cache_entry.Dirty := in_msg.Dirty;

14
src/mem/protocol/MOESI_CMP_token-L1cache.sm
View file

@ -1294,7 +1294,7 @@ machine(L1Cache, "Token protocol")
action(h_load_hit, "hd", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
L1Dcache.setMRU(cache_entry);
@ -1304,7 +1304,7 @@ machine(L1Cache, "Token protocol")
action(h_ifetch_hit, "hi", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
L1Icache.setMRU(cache_entry);
@ -1314,7 +1314,7 @@ machine(L1Cache, "Token protocol")
action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
peek(responseNetwork_in, ResponseMsg) {
L1Icache.setMRU(address);
@ -1327,7 +1327,7 @@ machine(L1Cache, "Token protocol")
action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
L1Dcache.setMRU(cache_entry);
@ -1339,7 +1339,7 @@ machine(L1Cache, "Token protocol")
action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
DPRINTF(RubySlicc, "Address: %#x, Data Block: %s\n",
address, cache_entry.DataBlk);
peek(responseNetwork_in, ResponseMsg) {
L1Icache.setMRU(address);
@ -1424,7 +1424,7 @@ machine(L1Cache, "Token protocol")
peek(responseNetwork_in, ResponseMsg) {
assert(is_valid(cache_entry));
assert(in_msg.Tokens != 0);
DPRINTF(RubySlicc, "L1 received tokens for address: %s, tokens: %d\n",
DPRINTF(RubySlicc, "L1 received tokens for address: %#x, tokens: %d\n",
in_msg.addr, in_msg.Tokens);
cache_entry.Tokens := cache_entry.Tokens + in_msg.Tokens;
DPRINTF(RubySlicc, "%d\n", cache_entry.Tokens);
@ -1544,7 +1544,7 @@ machine(L1Cache, "Token protocol")
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
if (send_evictions) {
DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}

2
src/mem/protocol/MOESI_hammer-cache.sm
View file

@ -1258,7 +1258,7 @@ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
if (send_evictions) {
DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
DPRINTF(RubySlicc, "Sending invalidation for %#x to the CPU\n", address);
sequencer.evictionCallback(address);
}
}

10
src/mem/ruby/common/Address.cc
View file

@ -121,3 +121,13 @@ makeNextStrideAddress(Addr addr, int stride)
return maskLowOrderBits(addr, RubySystem::getBlockSizeBits())
+ RubySystem::getBlockSizeBytes() * stride;
}
std::string
printAddress(Addr addr)
{
std::stringstream out;
out << "[" << std::hex << "0x" << addr << "," << " line 0x"
<< maskLowOrderBits(addr, RubySystem::getBlockSizeBits())
<< std::dec << "]";
return out.str();
}

1
src/mem/ruby/common/Address.hh
View file

@ -47,5 +47,6 @@ Addr shiftLowOrderBits(Addr addr, unsigned int number);
Addr getOffset(Addr addr);
Addr makeLineAddress(Addr addr);
Addr makeNextStrideAddress(Addr addr, int stride);
std::string printAddress(Addr addr);
#endif // __MEM_RUBY_COMMON_ADDRESS_HH__

4
src/mem/ruby/network/MessageBuffer.cc
View file

@ -281,7 +281,7 @@ MessageBuffer::reanalyzeList(list<MsgPtr> &lt, Tick schdTick)
void
MessageBuffer::reanalyzeMessages(Addr addr, Tick current_time)
{
DPRINTF(RubyQueue, "ReanalyzeMessages %s\n", addr);
DPRINTF(RubyQueue, "ReanalyzeMessages %#x\n", addr);
assert(m_stall_msg_map.count(addr) > 0);
//
@ -315,7 +315,7 @@ MessageBuffer::reanalyzeAllMessages(Tick current_time)
void
MessageBuffer::stallMessage(Addr addr, Tick current_time)
{
DPRINTF(RubyQueue, "Stalling due to %s\n", addr);
DPRINTF(RubyQueue, "Stalling due to %#x\n", addr);
assert(isReady(current_time));
assert(getOffset(addr) == 0);
MsgPtr message = m_prio_heap.front();

6
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
View file

@ -55,21 +55,21 @@ AbstractCacheEntry::changePermission(AccessPermission new_perm)
void
AbstractCacheEntry::setLocked(int context)
{
DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", m_Address, context);
DPRINTF(RubyCache, "Setting Lock for addr: %#x to %d\n", m_Address, context);
m_locked = context;
}
void
AbstractCacheEntry::clearLocked()
{
DPRINTF(RubyCache, "Clear Lock for addr: %x\n", m_Address);
DPRINTF(RubyCache, "Clear Lock for addr: %#x\n", m_Address);
m_locked = -1;
}
bool
AbstractCacheEntry::isLocked(int context) const
{
DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
DPRINTF(RubyCache, "Testing Lock for addr: %#llx cur %d con %d\n",
m_Address, m_locked, context);
return m_locked == context;
}

2
src/mem/ruby/slicc_interface/AbstractController.cc
View file

@ -97,7 +97,7 @@ AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
msgVec->resize(m_in_ports, NULL);
m_waiting_buffers[addr] = msgVec;
}
DPRINTF(RubyQueue, "stalling %s port %d addr %s\n", buf, m_cur_in_port,
DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port,
addr);
assert(m_in_ports > m_cur_in_port);
(*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;

6
src/mem/ruby/slicc_interface/RubyRequest.cc
View file

@ -36,10 +36,10 @@ void
RubyRequest::print(ostream& out) const
{
out << "[RubyRequest: ";
out << "LineAddress = " << m_LineAddress << " ";
out << "PhysicalAddress = " << m_PhysicalAddress << " ";
out << hex << "LineAddress = 0x" << m_LineAddress << dec << " ";
out << hex << "PhysicalAddress = 0x" << m_PhysicalAddress << dec << " ";
out << "Type = " << m_Type << " ";
out << "ProgramCounter = " << m_ProgramCounter << " ";
out << hex << "ProgramCounter = 0x" << m_ProgramCounter << dec << " ";
out << "AccessMode = " << m_AccessMode << " ";
out << "Size = " << m_Size << " ";
out << "Prefetch = " << m_Prefetch << " ";

22
src/mem/ruby/structures/CacheMemory.cc
View file

@ -163,7 +163,7 @@ CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
DataBlock*& data_ptr)
{
assert(address == makeLineAddress(address));
DPRINTF(RubyCache, "address: %s\n", address);
DPRINTF(RubyCache, "address: %#x\n", address);
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if (loc != -1) {
@ -190,7 +190,7 @@ CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
DataBlock*& data_ptr)
{
assert(address == makeLineAddress(address));
DPRINTF(RubyCache, "address: %s\n", address);
DPRINTF(RubyCache, "address: %#x\n", address);
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
@ -218,10 +218,10 @@ CacheMemory::isTagPresent(Addr address) const
if (loc == -1) {
// We didn't find the tag
DPRINTF(RubyCache, "No tag match for address: %s\n", address);
DPRINTF(RubyCache, "No tag match for address: %#x\n", address);
return false;
}
DPRINTF(RubyCache, "address: %s found\n", address);
DPRINTF(RubyCache, "address: %#x found\n", address);
return true;
}
@ -256,7 +256,7 @@ CacheMemory::allocate(Addr address, AbstractCacheEntry *entry, bool touch)
assert(address == makeLineAddress(address));
assert(!isTagPresent(address));
assert(cacheAvail(address));
DPRINTF(RubyCache, "address: %s\n", address);
DPRINTF(RubyCache, "address: %#x\n", address);
// Find the first open slot
int64_t cacheSet = addressToCacheSet(address);
@ -288,7 +288,7 @@ CacheMemory::deallocate(Addr address)
{
assert(address == makeLineAddress(address));
assert(isTagPresent(address));
DPRINTF(RubyCache, "address: %s\n", address);
DPRINTF(RubyCache, "address: %#x\n", address);
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
if (loc != -1) {
@ -417,7 +417,7 @@ CacheMemory::printData(ostream& out) const
void
CacheMemory::setLocked(Addr address, int context)
{
DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
DPRINTF(RubyCache, "Setting Lock for addr: %#x to %d\n", address, context);
assert(address == makeLineAddress(address));
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
@ -428,7 +428,7 @@ CacheMemory::setLocked(Addr address, int context)
void
CacheMemory::clearLocked(Addr address)
{
DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
DPRINTF(RubyCache, "Clear Lock for addr: %#x\n", address);
assert(address == makeLineAddress(address));
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
@ -443,7 +443,7 @@ CacheMemory::isLocked(Addr address, int context)
int64_t cacheSet = addressToCacheSet(address);
int loc = findTagInSet(cacheSet, address);
assert(loc != -1);
DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
DPRINTF(RubyCache, "Testing Lock for addr: %#llx cur %d con %d\n",
address, m_cache[cacheSet][loc]->m_locked, context);
return m_cache[cacheSet][loc]->isLocked(context);
}
@ -582,7 +582,7 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
if (tagArray.tryAccess(addressToCacheSet(addr))) return true;
else {
DPRINTF(RubyResourceStalls,
"Tag array stall on addr %s in set %d\n",
"Tag array stall on addr %#x in set %d\n",
addr, addressToCacheSet(addr));
numTagArrayStalls++;
return false;
@ -591,7 +591,7 @@ CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
if (dataArray.tryAccess(addressToCacheSet(addr))) return true;
else {
DPRINTF(RubyResourceStalls,
"Data array stall on addr %s in set %d\n",
"Data array stall on addr %#x in set %d\n",
addr, addressToCacheSet(addr));
numDataArrayStalls++;
return false;

4
src/mem/ruby/structures/DirectoryMemory.cc
View file

@ -114,7 +114,7 @@ AbstractEntry*
DirectoryMemory::lookup(Addr address)
{
assert(isPresent(address));
DPRINTF(RubyCache, "Looking up address: %s\n", address);
DPRINTF(RubyCache, "Looking up address: %#x\n", address);
uint64_t idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
@ -126,7 +126,7 @@ DirectoryMemory::allocate(Addr address, AbstractEntry *entry)
{
assert(isPresent(address));
uint64_t idx;
DPRINTF(RubyCache, "Looking up address: %s\n", address);
DPRINTF(RubyCache, "Looking up address: %#x\n", address);
idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);

10
src/mem/ruby/structures/Prefetcher.cc
View file

@ -135,7 +135,7 @@ Prefetcher::regStats()
void
Prefetcher::observeMiss(Addr address, const RubyRequestType& type)
{
DPRINTF(RubyPrefetcher, "Observed miss for %s\n", address);
DPRINTF(RubyPrefetcher, "Observed miss for %#x\n", address);
Addr line_addr = makeLineAddress(address);
numMissObserved++;
@ -204,7 +204,7 @@ void
Prefetcher::observePfMiss(Addr address)
{
numPartialHits++;
DPRINTF(RubyPrefetcher, "Observed partial hit for %s\n", address);
DPRINTF(RubyPrefetcher, "Observed partial hit for %#x\n", address);
issueNextPrefetch(address, NULL);
}
@ -212,7 +212,7 @@ void
Prefetcher::observePfHit(Addr address)
{
numHits++;
DPRINTF(RubyPrefetcher, "Observed hit for %s\n", address);
DPRINTF(RubyPrefetcher, "Observed hit for %#x\n", address);
issueNextPrefetch(address, NULL);
}
@ -250,7 +250,7 @@ Prefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream)
// launch next prefetch
stream->m_address = line_addr;
stream->m_use_time = m_controller->curCycle();
DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr);
DPRINTF(RubyPrefetcher, "Requesting prefetch for %#x\n", line_addr);
m_controller->enqueuePrefetch(line_addr, stream->m_type);
}
@ -314,7 +314,7 @@ Prefetcher::initializeStream(Addr address, int stride,
// launch prefetch
numPrefetchRequested++;
DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr);
DPRINTF(RubyPrefetcher, "Requesting prefetch for %#x\n", line_addr);
m_controller->enqueuePrefetch(line_addr, m_array[index].m_type);
}

4
src/mem/ruby/system/RubySystem.cc
View file

@ -404,7 +404,7 @@ RubySystem::functionalRead(PacketPtr pkt)
AccessPermission access_perm = AccessPermission_NotPresent;
int num_controllers = m_abs_cntrl_vec.size();
DPRINTF(RubySystem, "Functional Read request for %s\n", address);
DPRINTF(RubySystem, "Functional Read request for %#x\n", address);
unsigned int num_ro = 0;
unsigned int num_rw = 0;
@ -486,7 +486,7 @@ RubySystem::functionalWrite(PacketPtr pkt)
AccessPermission access_perm = AccessPermission_NotPresent;
int num_controllers = m_abs_cntrl_vec.size();
DPRINTF(RubySystem, "Functional Write request for %s\n", addr);
DPRINTF(RubySystem, "Functional Write request for %#x\n", addr);
uint32_t M5_VAR_USED num_functional_writes = 0;

4
src/mem/ruby/system/Sequencer.cc
View file

@ -443,7 +443,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n",
curTick(), m_version, "Seq",
llscSuccess ? "Done" : "SC_Failed", "", "",
request_address, total_latency);
printAddress(request_address), total_latency);
// update the data unless it is a non-data-carrying flush
if (RubySystem::getWarmupEnabled()) {
@ -610,7 +610,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
curTick(), m_version, "Seq", "Begin", "", "",
msg->getPhysicalAddress(),
printAddress(msg->getPhysicalAddress()),
RubyRequestType_to_string(secondary_type));
// The Sequencer currently assesses instruction and data cache hit latency

8
src/mem/slicc/symbols/StateMachine.py
View file

@ -1155,7 +1155,7 @@ ${ident}_Controller::doTransition(${ident}_Event event,
code('''
${ident}_State next_state = state;
DPRINTF(RubyGenerated, "%s, Time: %lld, state: %s, event: %s, addr: %s\\n",
DPRINTF(RubyGenerated, "%s, Time: %lld, state: %s, event: %s, addr: %#x\\n",
*this, curCycle(), ${ident}_State_to_string(state),
${ident}_Event_to_string(event), addr);
@ -1184,7 +1184,7 @@ if (result == TransitionResult_Valid) {
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
${ident}_State_to_string(next_state),
addr, GET_TRANSITION_COMMENT());
printAddress(addr), GET_TRANSITION_COMMENT());
CLEAR_TRANSITION_COMMENT();
''')
@ -1208,7 +1208,7 @@ if (result == TransitionResult_Valid) {
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
${ident}_State_to_string(next_state),
addr, "Resource Stall");
printAddress(addr), "Resource Stall");
} else if (result == TransitionResult_ProtocolStall) {
DPRINTF(RubyGenerated, "stalling\\n");
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\\n",
@ -1216,7 +1216,7 @@ if (result == TransitionResult_Valid) {
${ident}_Event_to_string(event),
${ident}_State_to_string(state),
${ident}_State_to_string(next_state),
addr, "Protocol Stall");
printAddress(addr), "Protocol Stall");
}
return result;

6
src/mem/slicc/symbols/Type.py
View file

@ -412,7 +412,11 @@ ${{self.c_ident}}::print(ostream& out) const
# For each field
code.indent()
for dm in self.data_members.values():
code('out << "${{dm.ident}} = " << m_${{dm.ident}} << " ";''')
if dm.type.c_ident == "Addr":
code('''
out << "${{dm.ident}} = " << printAddress(m_${{dm.ident}}) << " ";''')
else:
code('out << "${{dm.ident}} = " << m_${{dm.ident}} << " ";''')
code.dedent()