gem5/src
Dylan Johnson 7624fc1fb4 sim: Add relative break scheduling
Add schedRelBreak() function, executable within a debugger, that sets a
breakpoint by relative rather than absolute tick.
2015-10-09 14:27:09 -05:00
..
arch arch: clean up isa_parser error handling 2015-10-06 17:26:50 -07:00
base base: remove Trace::enabled flag 2015-09-30 15:21:55 -05:00
cpu sim: add ExecMacro to Exec* compound debug flags 2015-10-06 17:26:50 -07:00
dev isa,cpu: Add support for FS SMT Interrupts 2015-09-30 11:14:19 -05:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern style: change Process function calls to use camelCase 2015-07-24 12:25:23 -07:00
mem cpu,isa,mem: Add per-thread wakeup logic 2015-09-30 11:14:19 -05:00
proto cpu: add support for outputing a protobuf formatted CPU trace 2015-02-16 03:32:38 -05:00
python sim: print pid in output header 2015-10-06 17:26:50 -07:00
sim sim: Add relative break scheduling 2015-10-09 14:27:09 -05:00
unittest base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00