gem5/src
Andreas Sandberg 139c97c977 dev: Move existing PCI device functionality to src/dev/pci
Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing
devices to use the new header location. This also renames the PCIDEV
debug flag to have a capitalization that is consistent with the PCI
host and other devices.

--HG--
rename : src/dev/Pci.py => src/dev/pci/PciDevice.py
rename : src/dev/pcidev.cc => src/dev/pci/device.cc
rename : src/dev/pcidev.hh => src/dev/pci/device.hh
rename : src/dev/pcireg.h => src/dev/pci/pcireg.h
2015-12-10 10:35:15 +00:00
..
arch arm, config: Automatically discover available platforms 2015-12-04 00:19:05 +00:00
base sim: Disable gzip compression for writefile pseudo instruction 2015-11-05 18:26:23 +00:00
cpu cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
dev dev: Move existing PCI device functionality to src/dev/pci 2015-12-10 10:35:15 +00:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
mem mem: remove acq/rel cmds from packet and add mem fence req 2015-12-09 22:56:31 -05:00
proto cpu: Support virtual addr in elastic traces 2015-12-07 16:42:16 -06:00
python config: Fix broken SimObject listing 2015-12-01 13:01:05 +00:00
sim sim: Disable gzip compression for writefile pseudo instruction 2015-11-05 18:26:23 +00:00
unittest base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript sim: tag-based checkpoint versioning 2015-09-02 15:23:30 -05:00