dev: Move storage devices to src/dev/storage/

Move the IDE controller and the disk implementations to
src/dev/storage.

--HG--
rename : src/dev/DiskImage.py => src/dev/storage/DiskImage.py
rename : src/dev/Ide.py => src/dev/storage/Ide.py
rename : src/dev/SimpleDisk.py => src/dev/storage/SimpleDisk.py
rename : src/dev/disk_image.cc => src/dev/storage/disk_image.cc
rename : src/dev/disk_image.hh => src/dev/storage/disk_image.hh
rename : src/dev/ide_atareg.h => src/dev/storage/ide_atareg.h
rename : src/dev/ide_ctrl.cc => src/dev/storage/ide_ctrl.cc
rename : src/dev/ide_ctrl.hh => src/dev/storage/ide_ctrl.hh
rename : src/dev/ide_disk.cc => src/dev/storage/ide_disk.cc
rename : src/dev/ide_disk.hh => src/dev/storage/ide_disk.hh
rename : src/dev/ide_wdcreg.h => src/dev/storage/ide_wdcreg.h
rename : src/dev/simple_disk.cc => src/dev/storage/simple_disk.cc
rename : src/dev/simple_disk.hh => src/dev/storage/simple_disk.hh

src/dev/SConscript

@@ -40,40 +40,24 @@ if env['TARGET_ISA'] == 'null':
     Return()
 
 SimObject('BadDevice.py')
-SimObject('DiskImage.py')
-SimObject('Ide.py')
 SimObject('Platform.py')
-SimObject('SimpleDisk.py')
 SimObject('Terminal.py')
 SimObject('Uart.py')
 
 Source('baddev.cc')
-Source('disk_image.cc')
 Source('dma_device.cc')
-Source('ide_ctrl.cc')
-Source('ide_disk.cc')
 Source('intel_8254_timer.cc')
 Source('mc146818.cc')
 Source('pixelpump.cc')
 Source('platform.cc')
 Source('ps2.cc')
-Source('simple_disk.cc')
 Source('terminal.cc')
 Source('uart.cc')
 Source('uart8250.cc')
 
-DebugFlag('DiskImageRead')
-DebugFlag('DiskImageWrite')
 DebugFlag('DMA')
-DebugFlag('IdeCtrl')
-DebugFlag('IdeDisk')
 DebugFlag('Intel8254Timer')
 DebugFlag('MC146818')
-DebugFlag('SimpleDisk')
-DebugFlag('SimpleDiskData')
 DebugFlag('Terminal')
 DebugFlag('TerminalVerbose')
 DebugFlag('Uart')
-
-CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
-CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])

src/dev/alpha/backdoor.cc

@@ -50,7 +50,7 @@
 #include "dev/alpha/tsunami_cchip.hh"
 #include "dev/alpha/tsunami_io.hh"
 #include "dev/platform.hh"
-#include "dev/simple_disk.hh"
+#include "dev/storage/simple_disk.hh"
 #include "dev/terminal.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"

src/dev/arm/ufs_device.hh

@@ -152,7 +152,7 @@
 #include "debug/UFSHostDevice.hh"
 #include "dev/arm/abstract_nvm.hh"
 #include "dev/arm/base_gic.hh"
-#include "dev/disk_image.hh"
+#include "dev/storage/disk_image.hh"
 #include "dev/dma_device.hh"
 #include "dev/io_device.hh"
 #include "mem/packet.hh"

src/dev/sparc/iob.hh

@@ -36,7 +36,6 @@
 #ifndef __DEV_SPARC_IOB_HH__
 #define __DEV_SPARC_IOB_HH__
 
-#include "dev/disk_image.hh"
 #include "dev/io_device.hh"
 #include "params/Iob.hh"
 

src/dev/sparc/mm_disk.hh

@@ -36,8 +36,8 @@
 #ifndef __DEV_SPARC_MM_DISK_HH__
 #define __DEV_SPARC_MM_DISK_HH__
 
-#include "dev/disk_image.hh"
 #include "dev/io_device.hh"
+#include "dev/storage/disk_image.hh"
 #include "params/MmDisk.hh"
 
 class MmDisk : public BasicPioDevice

src/dev/storage/DiskImage.py

@@ -31,17 +31,17 @@ from m5.params import *
 class DiskImage(SimObject):
     type = 'DiskImage'
     abstract = True
-    cxx_header = "dev/disk_image.hh"
+    cxx_header = "dev/storage/disk_image.hh"
     image_file = Param.String("disk image file")
     read_only = Param.Bool(False, "read only image")
 
 class RawDiskImage(DiskImage):
     type = 'RawDiskImage'
-    cxx_header = "dev/disk_image.hh"
+    cxx_header = "dev/storage/disk_image.hh"
 
 class CowDiskImage(DiskImage):
     type = 'CowDiskImage'
-    cxx_header = "dev/disk_image.hh"
+    cxx_header = "dev/storage/disk_image.hh"
     child = Param.DiskImage(RawDiskImage(read_only=True),
                             "child image")
     table_size = Param.Int(65536, "initial table size")

src/dev/storage/Ide.py

@@ -34,14 +34,14 @@ class IdeID(Enum): vals = ['master', 'slave']
 
 class IdeDisk(SimObject):
     type = 'IdeDisk'
-    cxx_header = "dev/ide_disk.hh"
+    cxx_header = "dev/storage/ide_disk.hh"
     delay = Param.Latency('1us', "Fixed disk delay in microseconds")
     driveID = Param.IdeID('master', "Drive ID")
     image = Param.DiskImage("Disk image")
 
 class IdeController(PciDevice):
     type = 'IdeController'
-    cxx_header = "dev/ide_ctrl.hh"
+    cxx_header = "dev/storage/ide_ctrl.hh"
     disks = VectorParam.IdeDisk("IDE disks attached to this controller")
 
     VendorID = 0x8086

src/dev/storage/SConscript

@@ -0,0 +1,73 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2015 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+#          Gabe Black
+#          Andreas Sandberg
+
+Import('*')
+
+if env['TARGET_ISA'] == 'null':
+    Return()
+
+# Controllers
+SimObject('Ide.py')
+
+Source('ide_ctrl.cc')
+Source('ide_disk.cc')
+
+DebugFlag('IdeCtrl')
+DebugFlag('IdeDisk')
+
+# Disk models
+SimObject('DiskImage.py')
+SimObject('SimpleDisk.py')
+
+Source('disk_image.cc')
+Source('simple_disk.cc')
+
+DebugFlag('DiskImageRead')
+DebugFlag('DiskImageWrite')
+DebugFlag('SimpleDisk')
+DebugFlag('SimpleDiskData')
+
+
+CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
+CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])

src/dev/storage/SimpleDisk.py

@@ -29,8 +29,9 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+
 class SimpleDisk(SimObject):
     type = 'SimpleDisk'
-    cxx_header = "dev/simple_disk.hh"
+    cxx_header = "dev/storage/simple_disk.hh"
     disk = Param.DiskImage("Disk Image")
     system = Param.System(Parent.any, "System Pointer")

src/dev/storage/disk_image.cc

@@ -32,6 +32,8 @@
  * Disk Image Definitions
  */
 
+#include "dev/storage/disk_image.hh"
+
 #include <sys/types.h>
 #include <sys/uio.h>
 #include <unistd.h>
@@ -46,7 +48,6 @@
 #include "base/trace.hh"
 #include "debug/DiskImageRead.hh"
 #include "debug/DiskImageWrite.hh"
-#include "dev/disk_image.hh"
 #include "sim/byteswap.hh"
 #include "sim/sim_exit.hh"
 

src/dev/storage/disk_image.hh

@@ -32,8 +32,8 @@
  * Disk Image Interfaces
  */
 
-#ifndef __DISK_IMAGE_HH__
-#define __DISK_IMAGE_HH__
+#ifndef __DEV_STORAGE_DISK_IMAGE_HH__
+#define __DEV_STORAGE_DISK_IMAGE_HH__
 
 #include <fstream>
 #include <unordered_map>
@@ -154,4 +154,4 @@ void SafeWrite(std::ofstream &stream, const T &data);
 template<class T>
 void SafeWriteSwap(std::ofstream &stream, const T &data);
 
-#endif // __DISK_IMAGE_HH__
+#endif // __DEV_STORAGE_DISK_IMAGE_HH__

src/dev/storage/ide_atareg.h

@@ -35,10 +35,13 @@
 
 #if defined(__linux__)
 #include <endian.h>
+
 #elif defined(__sun)
 #include <sys/isa_defs.h>
+
 #else
 #include <machine/endian.h>
+
 #endif
 
 #ifdef LITTLE_ENDIAN

src/dev/storage/ide_ctrl.cc

@@ -42,12 +42,13 @@
  *          Miguel Serrano
  */
 
+#include "dev/storage/ide_ctrl.hh"
+
 #include <string>
 
 #include "cpu/intr_control.hh"
 #include "debug/IdeCtrl.hh"
-#include "dev/ide_ctrl.hh"
-#include "dev/ide_disk.hh"
+#include "dev/storage/ide_disk.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/IdeController.hh"

src/dev/storage/ide_ctrl.hh

@@ -34,8 +34,8 @@
  * modeled after controller in the Intel PIIX4 chip
  */
 
-#ifndef __IDE_CTRL_HH__
-#define __IDE_CTRL_HH__
+#ifndef __DEV_STORAGE_IDE_CTRL_HH__
+#define __DEV_STORAGE_IDE_CTRL_HH__
 
 #include "base/bitunion.hh"
 #include "dev/io_device.hh"
@@ -156,4 +156,4 @@ class IdeController : public PciDevice
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
 };
-#endif // __IDE_CTRL_HH_
+#endif // __DEV_STORAGE_IDE_CTRL_HH_

src/dev/storage/ide_disk.cc

@@ -45,6 +45,8 @@
  * Device model implementation for an IDE disk
  */
 
+#include "dev/storage/ide_disk.hh"
+
 #include <cerrno>
 #include <cstring>
 #include <deque>
@@ -56,9 +58,8 @@
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "debug/IdeDisk.hh"
-#include "dev/disk_image.hh"
-#include "dev/ide_ctrl.hh"
-#include "dev/ide_disk.hh"
+#include "dev/storage/disk_image.hh"
+#include "dev/storage/ide_ctrl.hh"
 #include "sim/core.hh"
 #include "sim/sim_object.hh"
 

src/dev/storage/ide_disk.hh

@@ -44,15 +44,15 @@
  * Device model for an IDE disk
  */
 
-#ifndef __IDE_DISK_HH__
-#define __IDE_DISK_HH__
+#ifndef __DEV_STORAGE_IDE_DISK_HH__
+#define __DEV_STORAGE_IDE_DISK_HH__
 
 #include "base/statistics.hh"
-#include "dev/disk_image.hh"
-#include "dev/ide_atareg.h"
-#include "dev/ide_ctrl.hh"
-#include "dev/ide_wdcreg.h"
 #include "dev/io_device.hh"
+#include "dev/storage/disk_image.hh"
+#include "dev/storage/ide_atareg.h"
+#include "dev/storage/ide_ctrl.hh"
+#include "dev/storage/ide_wdcreg.h"
 #include "params/IdeDisk.hh"
 #include "sim/eventq.hh"
 
@@ -370,4 +370,4 @@ class IdeDisk : public SimObject
 };
 
 
-#endif // __IDE_DISK_HH__
+#endif // __DEV_STORAGE_IDE_DISK_HH__

src/dev/storage/simple_disk.cc

@@ -32,9 +32,11 @@
  * Simple disk interface for the system console
  */
 
+#include "dev/storage/simple_disk.hh"
+
+#include <fcntl.h>
 #include <sys/types.h>
 #include <sys/uio.h>
-#include <fcntl.h>
 #include <unistd.h>
 
 #include <cstring>
@@ -44,8 +46,7 @@
 #include "base/trace.hh"
 #include "debug/SimpleDisk.hh"
 #include "debug/SimpleDiskData.hh"
-#include "dev/disk_image.hh"
-#include "dev/simple_disk.hh"
+#include "dev/storage/disk_image.hh"
 #include "mem/port_proxy.hh"
 #include "sim/system.hh"
 

src/dev/storage/simple_disk.hh

@@ -32,8 +32,8 @@
  * Simple disk interface for the system console
  */
 
-#ifndef __DEV_SIMPLE_DISK_HH__
-#define __DEV_SIMPLE_DISK_HH__
+#ifndef __DEV_STORAGE_SIMPLE_DISK_HH__
+#define __DEV_STORAGE_SIMPLE_DISK_HH__
 
 #include "params/SimpleDisk.hh"
 #include "sim/sim_object.hh"
@@ -62,4 +62,4 @@ class SimpleDisk : public SimObject
     void write(Addr addr, baddr_t block, int count);
 };
 
-#endif // __DEV_SIMPLE_DISK_HH__
+#endif // __DEV_STORAGE_SIMPLE_DISK_HH__

src/dev/virtio/block.hh

@@ -41,7 +41,7 @@
 #define __DEV_VIRTIO_BLOCK_HH__
 
 #include "dev/virtio/base.hh"
-#include "dev/disk_image.hh"
+#include "dev/storage/disk_image.hh"
 #include "dev/terminal.hh"
 
 struct VirtIOBlockParams;