mem: hmc: serial link model
This changeset adds a serial link model for the Hybrid Memory Cube (HMC). SerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization. Also trySendTiming has been modified to correctly model bandwidth. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Erfan Azarkhish
parent
1530e1a690
commit
7e3f670457
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@ -43,6 +43,7 @@ SimObject('MemObject.py')
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SimObject('SimpleMemory.py')
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SimObject('XBar.py')
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SimObject('HMCController.py')
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SimObject('SerialLink.py')
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Source('abstract_mem.cc')
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Source('addr_mapper.cc')
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@ -66,6 +67,7 @@ Source('stack_dist_calc.cc')
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Source('tport.cc')
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Source('xbar.cc')
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Source('hmc_controller.cc')
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Source('serial_link.cc')
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if env['TARGET_ISA'] != 'null':
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Source('fs_translating_port_proxy.cc')
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@ -104,6 +106,7 @@ DebugFlag('PacketQueue')
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DebugFlag('StackDist')
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DebugFlag("DRAMSim2")
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DebugFlag('HMCController')
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DebugFlag('SerialLink')
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DebugFlag("MemChecker")
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DebugFlag("MemCheckerMonitor")
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63
src/mem/SerialLink.py
Normal file
63
src/mem/SerialLink.py
Normal file
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@ -0,0 +1,63 @@
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# Copyright (c) 2012-2013 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2015 The University of Bologna
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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# Andreas Hansson
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# Erfan Azarkhish
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from m5.params import *
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from MemObject import MemObject
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# SerialLink is a simple variation of the Bridge class, with the ability to
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# account for the latency of packet serialization.
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class SerialLink(MemObject):
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type = 'SerialLink'
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cxx_header = "mem/serial_link.hh"
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slave = SlavePort('Slave port')
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master = MasterPort('Master port')
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req_size = Param.Unsigned(16, "The number of requests to buffer")
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resp_size = Param.Unsigned(16, "The number of responses to buffer")
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delay = Param.Latency('0ns', "The latency of this serial_link")
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ranges = VectorParam.AddrRange([AllMemory],
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"Address ranges to pass through the serial_link")
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# Bandwidth of the serial link is determined by the clock domain which the
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# link belongs to and the number of lanes:
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num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
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"link. (aka. lane width)")
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437
src/mem/serial_link.cc
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437
src/mem/serial_link.cc
Normal file
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@ -0,0 +1,437 @@
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/*
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* Copyright (c) 2011-2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2015 The University of Bologna
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Steve Reinhardt
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* Andreas Hansson
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* Erfan Azarkhish
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*/
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/**
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* @file
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* Implementation of the SerialLink Class, modeling Hybrid-Memory-Cube's
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* serial interface.
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*/
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#include "mem/serial_link.hh"
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#include "base/trace.hh"
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#include "debug/SerialLink.hh"
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#include "params/SerialLink.hh"
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SerialLink::SerialLinkSlavePort::SerialLinkSlavePort(const std::string& _name,
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SerialLink& _serial_link,
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SerialLinkMasterPort& _masterPort,
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Cycles _delay, int _resp_limit,
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const std::vector<AddrRange>&
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_ranges)
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: SlavePort(_name, &_serial_link), serial_link(_serial_link),
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masterPort(_masterPort), delay(_delay),
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ranges(_ranges.begin(), _ranges.end()),
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outstandingResponses(0), retryReq(false),
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respQueueLimit(_resp_limit), sendEvent(*this)
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{
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}
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SerialLink::SerialLinkMasterPort::SerialLinkMasterPort(const std::string&
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_name, SerialLink& _serial_link,
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SerialLinkSlavePort& _slavePort,
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Cycles _delay, int _req_limit)
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: MasterPort(_name, &_serial_link), serial_link(_serial_link),
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slavePort(_slavePort), delay(_delay), reqQueueLimit(_req_limit),
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sendEvent(*this)
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{
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}
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SerialLink::SerialLink(SerialLinkParams *p)
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: MemObject(p),
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slavePort(p->name + ".slave", *this, masterPort,
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ticksToCycles(p->delay), p->resp_size, p->ranges),
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masterPort(p->name + ".master", *this, slavePort,
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ticksToCycles(p->delay), p->req_size),
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num_lanes(p->num_lanes)
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{
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}
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BaseMasterPort&
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SerialLink::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "master")
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return masterPort;
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else
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// pass it along to our super class
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return MemObject::getMasterPort(if_name, idx);
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}
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BaseSlavePort&
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SerialLink::getSlavePort(const std::string &if_name, PortID idx)
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{
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if (if_name == "slave")
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return slavePort;
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else
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// pass it along to our super class
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return MemObject::getSlavePort(if_name, idx);
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}
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void
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SerialLink::init()
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{
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// make sure both sides are connected and have the same block size
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if (!slavePort.isConnected() || !masterPort.isConnected())
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fatal("Both ports of a serial_link must be connected.\n");
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// notify the master side of our address ranges
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slavePort.sendRangeChange();
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}
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bool
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SerialLink::SerialLinkSlavePort::respQueueFull() const
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{
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return outstandingResponses == respQueueLimit;
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}
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bool
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SerialLink::SerialLinkMasterPort::reqQueueFull() const
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{
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return transmitList.size() == reqQueueLimit;
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}
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bool
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SerialLink::SerialLinkMasterPort::recvTimingResp(PacketPtr pkt)
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{
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// all checks are done when the request is accepted on the slave
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// side, so we are guaranteed to have space for the response
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DPRINTF(SerialLink, "recvTimingResp: %s addr 0x%x\n",
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pkt->cmdString(), pkt->getAddr());
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DPRINTF(SerialLink, "Request queue size: %d\n", transmitList.size());
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// @todo: We need to pay for this and not just zero it out
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pkt->headerDelay = pkt->payloadDelay = 0;
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// This is similar to what happens for the request packets:
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// The serializer will start serialization as soon as it receives the
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// first flit, but the deserializer (at the host side in this case), will
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// have to wait to receive the whole packet. So we only account for the
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// deserialization latency.
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Cycles cycles = delay;
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cycles += Cycles(divCeil(pkt->getSize() * 8, serial_link.num_lanes));
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Tick t = serial_link.clockEdge(cycles);
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//@todo: If the processor sends two uncached requests towards HMC and the
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// second one is smaller than the first one. It may happen that the second
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// one crosses this link faster than the first one (because the packet
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// waits in the link based on its size). This can reorder the received
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// response.
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slavePort.schedTimingResp(pkt, t);
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return true;
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}
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bool
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SerialLink::SerialLinkSlavePort::recvTimingReq(PacketPtr pkt)
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{
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DPRINTF(SerialLink, "recvTimingReq: %s addr 0x%x\n",
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pkt->cmdString(), pkt->getAddr());
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// we should not see a timing request if we are already in a retry
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assert(!retryReq);
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DPRINTF(SerialLink, "Response queue size: %d outresp: %d\n",
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transmitList.size(), outstandingResponses);
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// if the request queue is full then there is no hope
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if (masterPort.reqQueueFull()) {
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DPRINTF(SerialLink, "Request queue full\n");
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retryReq = true;
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} else if ( !retryReq ) {
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// look at the response queue if we expect to see a response
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bool expects_response = pkt->needsResponse() &&
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!pkt->memInhibitAsserted();
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if (expects_response) {
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if (respQueueFull()) {
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DPRINTF(SerialLink, "Response queue full\n");
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retryReq = true;
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} else {
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// ok to send the request with space for the response
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DPRINTF(SerialLink, "Reserving space for response\n");
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assert(outstandingResponses != respQueueLimit);
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++outstandingResponses;
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// no need to set retryReq to false as this is already the
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// case
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}
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}
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if (!retryReq) {
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// @todo: We need to pay for this and not just zero it out
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pkt->headerDelay = pkt->payloadDelay = 0;
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// We assume that the serializer component at the transmitter side
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// does not need to receive the whole packet to start the
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// serialization (this assumption is consistent with the HMC
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// standard). But the deserializer waits for the complete packet
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// to check its integrity first. So everytime a packet crosses a
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// serial link, we should account for its deserialization latency
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// only.
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Cycles cycles = delay;
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cycles += Cycles(divCeil(pkt->getSize() * 8,
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serial_link.num_lanes));
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Tick t = serial_link.clockEdge(cycles);
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//@todo: If the processor sends two uncached requests towards HMC
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// and the second one is smaller than the first one. It may happen
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// that the second one crosses this link faster than the first one
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// (because the packet waits in the link based on its size).
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// This can reorder the received response.
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masterPort.schedTimingReq(pkt, t);
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}
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}
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// remember that we are now stalling a packet and that we have to
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// tell the sending master to retry once space becomes available,
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// we make no distinction whether the stalling is due to the
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// request queue or response queue being full
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return !retryReq;
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}
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void
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SerialLink::SerialLinkSlavePort::retryStalledReq()
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{
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if (retryReq) {
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DPRINTF(SerialLink, "Request waiting for retry, now retrying\n");
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retryReq = false;
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sendRetryReq();
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}
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}
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void
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SerialLink::SerialLinkMasterPort::schedTimingReq(PacketPtr pkt, Tick when)
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{
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// If we're about to put this packet at the head of the queue, we
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// need to schedule an event to do the transmit. Otherwise there
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// should already be an event scheduled for sending the head
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// packet.
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if (transmitList.empty()) {
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serial_link.schedule(sendEvent, when);
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}
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assert(transmitList.size() != reqQueueLimit);
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transmitList.emplace_back(DeferredPacket(pkt, when));
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}
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void
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SerialLink::SerialLinkSlavePort::schedTimingResp(PacketPtr pkt, Tick when)
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{
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// If we're about to put this packet at the head of the queue, we
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// need to schedule an event to do the transmit. Otherwise there
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// should already be an event scheduled for sending the head
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// packet.
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if (transmitList.empty()) {
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serial_link.schedule(sendEvent, when);
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}
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transmitList.emplace_back(DeferredPacket(pkt, when));
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}
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void
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SerialLink::SerialLinkMasterPort::trySendTiming()
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{
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assert(!transmitList.empty());
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DeferredPacket req = transmitList.front();
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assert(req.tick <= curTick());
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PacketPtr pkt = req.pkt;
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DPRINTF(SerialLink, "trySend request addr 0x%x, queue size %d\n",
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pkt->getAddr(), transmitList.size());
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if (sendTimingReq(pkt)) {
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// send successful
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transmitList.pop_front();
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DPRINTF(SerialLink, "trySend request successful\n");
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// If there are more packets to send, schedule event to try again.
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if (!transmitList.empty()) {
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DeferredPacket next_req = transmitList.front();
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DPRINTF(SerialLink, "Scheduling next send\n");
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// Make sure bandwidth limitation is met
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Cycles cycles = Cycles(divCeil(pkt->getSize() * 8,
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serial_link.num_lanes));
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Tick t = serial_link.clockEdge(cycles);
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serial_link.schedule(sendEvent, std::max(next_req.tick, t));
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}
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// if we have stalled a request due to a full request queue,
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// then send a retry at this point, also note that if the
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// request we stalled was waiting for the response queue
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// rather than the request queue we might stall it again
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slavePort.retryStalledReq();
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}
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// if the send failed, then we try again once we receive a retry,
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// and therefore there is no need to take any action
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}
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void
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SerialLink::SerialLinkSlavePort::trySendTiming()
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{
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assert(!transmitList.empty());
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DeferredPacket resp = transmitList.front();
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assert(resp.tick <= curTick());
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PacketPtr pkt = resp.pkt;
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DPRINTF(SerialLink, "trySend response addr 0x%x, outstanding %d\n",
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pkt->getAddr(), outstandingResponses);
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if (sendTimingResp(pkt)) {
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// send successful
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transmitList.pop_front();
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DPRINTF(SerialLink, "trySend response successful\n");
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assert(outstandingResponses != 0);
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--outstandingResponses;
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// If there are more packets to send, schedule event to try again.
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if (!transmitList.empty()) {
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DeferredPacket next_resp = transmitList.front();
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DPRINTF(SerialLink, "Scheduling next send\n");
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// Make sure bandwidth limitation is met
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Cycles cycles = Cycles(divCeil(pkt->getSize() * 8,
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serial_link.num_lanes));
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Tick t = serial_link.clockEdge(cycles);
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serial_link.schedule(sendEvent, std::max(next_resp.tick, t));
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}
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// if there is space in the request queue and we were stalling
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// a request, it will definitely be possible to accept it now
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// since there is guaranteed space in the response queue
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if (!masterPort.reqQueueFull() && retryReq) {
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DPRINTF(SerialLink, "Request waiting for retry, now retrying\n");
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retryReq = false;
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sendRetryReq();
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}
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}
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// if the send failed, then we try again once we receive a retry,
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// and therefore there is no need to take any action
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}
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void
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SerialLink::SerialLinkMasterPort::recvReqRetry()
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{
|
||||
trySendTiming();
|
||||
}
|
||||
|
||||
void
|
||||
SerialLink::SerialLinkSlavePort::recvRespRetry()
|
||||
{
|
||||
trySendTiming();
|
||||
}
|
||||
|
||||
Tick
|
||||
SerialLink::SerialLinkSlavePort::recvAtomic(PacketPtr pkt)
|
||||
{
|
||||
return delay * serial_link.clockPeriod() + masterPort.sendAtomic(pkt);
|
||||
}
|
||||
|
||||
void
|
||||
SerialLink::SerialLinkSlavePort::recvFunctional(PacketPtr pkt)
|
||||
{
|
||||
pkt->pushLabel(name());
|
||||
|
||||
// check the response queue
|
||||
for (auto i = transmitList.begin(); i != transmitList.end(); ++i) {
|
||||
if (pkt->checkFunctional((*i).pkt)) {
|
||||
pkt->makeResponse();
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// also check the master port's request queue
|
||||
if (masterPort.checkFunctional(pkt)) {
|
||||
return;
|
||||
}
|
||||
|
||||
pkt->popLabel();
|
||||
|
||||
// fall through if pkt still not satisfied
|
||||
masterPort.sendFunctional(pkt);
|
||||
}
|
||||
|
||||
bool
|
||||
SerialLink::SerialLinkMasterPort::checkFunctional(PacketPtr pkt)
|
||||
{
|
||||
bool found = false;
|
||||
auto i = transmitList.begin();
|
||||
|
||||
while(i != transmitList.end() && !found) {
|
||||
if (pkt->checkFunctional((*i).pkt)) {
|
||||
pkt->makeResponse();
|
||||
found = true;
|
||||
}
|
||||
++i;
|
||||
}
|
||||
|
||||
return found;
|
||||
}
|
||||
|
||||
AddrRangeList
|
||||
SerialLink::SerialLinkSlavePort::getAddrRanges() const
|
||||
{
|
||||
return ranges;
|
||||
}
|
||||
|
||||
SerialLink *
|
||||
SerialLinkParams::create()
|
||||
{
|
||||
return new SerialLink(this);
|
||||
}
|
||||
329
src/mem/serial_link.hh
Normal file
329
src/mem/serial_link.hh
Normal file
|
|
@ -0,0 +1,329 @@
|
|||
/*
|
||||
* Copyright (c) 2011-2013 ARM Limited
|
||||
* All rights reserved
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* Copyright (c) 2015 The University of Bologna
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Ali Saidi
|
||||
* Steve Reinhardt
|
||||
* Andreas Hansson
|
||||
* Erfan Azarkhish
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* Declaration of the SerialLink Class, modeling Hybrid-Memory-Cube's serial
|
||||
* interface.
|
||||
*/
|
||||
|
||||
#ifndef __MEM_SERIAL_LINK_HH__
|
||||
#define __MEM_SERIAL_LINK_HH__
|
||||
|
||||
#include <deque>
|
||||
|
||||
#include "base/types.hh"
|
||||
#include "mem/mem_object.hh"
|
||||
#include "params/SerialLink.hh"
|
||||
|
||||
/**
|
||||
* SerialLink is a simple variation of the Bridge class, with the ability to
|
||||
* account for the latency of packet serialization. We assume that the
|
||||
* serializer component at the transmitter side does not need to receive the
|
||||
* whole packet to start the serialization. But the deserializer waits for the
|
||||
* complete packet to check its integrity first.
|
||||
*/
|
||||
class SerialLink : public MemObject
|
||||
{
|
||||
protected:
|
||||
|
||||
/**
|
||||
* A deferred packet stores a packet along with its scheduled
|
||||
* transmission time
|
||||
*/
|
||||
class DeferredPacket
|
||||
{
|
||||
|
||||
public:
|
||||
|
||||
const Tick tick;
|
||||
const PacketPtr pkt;
|
||||
|
||||
DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
|
||||
{ }
|
||||
};
|
||||
|
||||
// Forward declaration to allow the slave port to have a pointer
|
||||
class SerialLinkMasterPort;
|
||||
|
||||
/**
|
||||
* The port on the side that receives requests and sends
|
||||
* responses. The slave port has a set of address ranges that it
|
||||
* is responsible for. The slave port also has a buffer for the
|
||||
* responses not yet sent.
|
||||
*/
|
||||
class SerialLinkSlavePort : public SlavePort
|
||||
{
|
||||
|
||||
private:
|
||||
|
||||
/** The serial_link to which this port belongs. */
|
||||
SerialLink& serial_link;
|
||||
|
||||
/**
|
||||
* Master port on the other side of the serial_link.
|
||||
*/
|
||||
SerialLinkMasterPort& masterPort;
|
||||
|
||||
/** Minimum request delay though this serial_link. */
|
||||
const Cycles delay;
|
||||
|
||||
/** Address ranges to pass through the serial_link */
|
||||
const AddrRangeList ranges;
|
||||
|
||||
/**
|
||||
* Response packet queue. Response packets are held in this
|
||||
* queue for a specified delay to model the processing delay
|
||||
* of the serial_link. We use a deque as we need to iterate over
|
||||
* the items for functional accesses.
|
||||
*/
|
||||
std::deque<DeferredPacket> transmitList;
|
||||
|
||||
/** Counter to track the outstanding responses. */
|
||||
unsigned int outstandingResponses;
|
||||
|
||||
/** If we should send a retry when space becomes available. */
|
||||
bool retryReq;
|
||||
|
||||
/** Max queue size for reserved responses. */
|
||||
unsigned int respQueueLimit;
|
||||
|
||||
/**
|
||||
* Is this side blocked from accepting new response packets.
|
||||
*
|
||||
* @return true if the reserved space has reached the set limit
|
||||
*/
|
||||
bool respQueueFull() const;
|
||||
|
||||
/**
|
||||
* Handle send event, scheduled when the packet at the head of
|
||||
* the response queue is ready to transmit (for timing
|
||||
* accesses only).
|
||||
*/
|
||||
void trySendTiming();
|
||||
|
||||
/** Send event for the response queue. */
|
||||
EventWrapper<SerialLinkSlavePort,
|
||||
&SerialLinkSlavePort::trySendTiming> sendEvent;
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor for the SerialLinkSlavePort.
|
||||
*
|
||||
* @param _name the port name including the owner
|
||||
* @param _serial_link the structural owner
|
||||
* @param _masterPort the master port on the other side of the
|
||||
* serial_link
|
||||
* @param _delay the delay in cycles from receiving to sending
|
||||
* @param _resp_limit the size of the response queue
|
||||
* @param _ranges a number of address ranges to forward
|
||||
*/
|
||||
SerialLinkSlavePort(const std::string& _name, SerialLink&
|
||||
_serial_link, SerialLinkMasterPort& _masterPort,
|
||||
Cycles _delay, int _resp_limit, const
|
||||
std::vector<AddrRange>& _ranges);
|
||||
|
||||
/**
|
||||
* Queue a response packet to be sent out later and also schedule
|
||||
* a send if necessary.
|
||||
*
|
||||
* @param pkt a response to send out after a delay
|
||||
* @param when tick when response packet should be sent
|
||||
*/
|
||||
void schedTimingResp(PacketPtr pkt, Tick when);
|
||||
|
||||
/**
|
||||
* Retry any stalled request that we have failed to accept at
|
||||
* an earlier point in time. This call will do nothing if no
|
||||
* request is waiting.
|
||||
*/
|
||||
void retryStalledReq();
|
||||
|
||||
protected:
|
||||
|
||||
/** When receiving a timing request from the peer port,
|
||||
pass it to the serial_link. */
|
||||
bool recvTimingReq(PacketPtr pkt);
|
||||
|
||||
/** When receiving a retry request from the peer port,
|
||||
pass it to the serial_link. */
|
||||
void recvRespRetry();
|
||||
|
||||
/** When receiving a Atomic requestfrom the peer port,
|
||||
pass it to the serial_link. */
|
||||
Tick recvAtomic(PacketPtr pkt);
|
||||
|
||||
/** When receiving a Functional request from the peer port,
|
||||
pass it to the serial_link. */
|
||||
void recvFunctional(PacketPtr pkt);
|
||||
|
||||
/** When receiving a address range request the peer port,
|
||||
pass it to the serial_link. */
|
||||
AddrRangeList getAddrRanges() const;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* Port on the side that forwards requests and receives
|
||||
* responses. The master port has a buffer for the requests not
|
||||
* yet sent.
|
||||
*/
|
||||
class SerialLinkMasterPort : public MasterPort
|
||||
{
|
||||
|
||||
private:
|
||||
|
||||
/** The serial_link to which this port belongs. */
|
||||
SerialLink& serial_link;
|
||||
|
||||
/**
|
||||
* The slave port on the other side of the serial_link.
|
||||
*/
|
||||
SerialLinkSlavePort& slavePort;
|
||||
|
||||
/** Minimum delay though this serial_link. */
|
||||
const Cycles delay;
|
||||
|
||||
/**
|
||||
* Request packet queue. Request packets are held in this
|
||||
* queue for a specified delay to model the processing delay
|
||||
* of the serial_link. We use a deque as we need to iterate over
|
||||
* the items for functional accesses.
|
||||
*/
|
||||
std::deque<DeferredPacket> transmitList;
|
||||
|
||||
/** Max queue size for request packets */
|
||||
const unsigned int reqQueueLimit;
|
||||
|
||||
/**
|
||||
* Handle send event, scheduled when the packet at the head of
|
||||
* the outbound queue is ready to transmit (for timing
|
||||
* accesses only).
|
||||
*/
|
||||
void trySendTiming();
|
||||
|
||||
/** Send event for the request queue. */
|
||||
EventWrapper<SerialLinkMasterPort,
|
||||
&SerialLinkMasterPort::trySendTiming> sendEvent;
|
||||
|
||||
public:
|
||||
|
||||
/**
|
||||
* Constructor for the SerialLinkMasterPort.
|
||||
*
|
||||
* @param _name the port name including the owner
|
||||
* @param _serial_link the structural owner
|
||||
* @param _slavePort the slave port on the other side of the
|
||||
* serial_link
|
||||
* @param _delay the delay in cycles from receiving to sending
|
||||
* @param _req_limit the size of the request queue
|
||||
*/
|
||||
SerialLinkMasterPort(const std::string& _name, SerialLink&
|
||||
_serial_link, SerialLinkSlavePort& _slavePort, Cycles
|
||||
_delay, int _req_limit);
|
||||
|
||||
/**
|
||||
* Is this side blocked from accepting new request packets.
|
||||
*
|
||||
* @return true if the occupied space has reached the set limit
|
||||
*/
|
||||
bool reqQueueFull() const;
|
||||
|
||||
/**
|
||||
* Queue a request packet to be sent out later and also schedule
|
||||
* a send if necessary.
|
||||
*
|
||||
* @param pkt a request to send out after a delay
|
||||
* @param when tick when response packet should be sent
|
||||
*/
|
||||
void schedTimingReq(PacketPtr pkt, Tick when);
|
||||
|
||||
/**
|
||||
* Check a functional request against the packets in our
|
||||
* request queue.
|
||||
*
|
||||
* @param pkt packet to check against
|
||||
*
|
||||
* @return true if we find a match
|
||||
*/
|
||||
bool checkFunctional(PacketPtr pkt);
|
||||
|
||||
protected:
|
||||
|
||||
/** When receiving a timing request from the peer port,
|
||||
pass it to the serial_link. */
|
||||
bool recvTimingResp(PacketPtr pkt);
|
||||
|
||||
/** When receiving a retry request from the peer port,
|
||||
pass it to the serial_link. */
|
||||
void recvReqRetry();
|
||||
};
|
||||
|
||||
/** Slave port of the serial_link. */
|
||||
SerialLinkSlavePort slavePort;
|
||||
|
||||
/** Master port of the serial_link. */
|
||||
SerialLinkMasterPort masterPort;
|
||||
|
||||
/** Number of parallel lanes in this serial link */
|
||||
unsigned num_lanes;
|
||||
|
||||
public:
|
||||
|
||||
virtual BaseMasterPort& getMasterPort(const std::string& if_name,
|
||||
PortID idx = InvalidPortID);
|
||||
virtual BaseSlavePort& getSlavePort(const std::string& if_name,
|
||||
PortID idx = InvalidPortID);
|
||||
|
||||
virtual void init();
|
||||
|
||||
typedef SerialLinkParams Params;
|
||||
|
||||
SerialLink(SerialLinkParams *p);
|
||||
};
|
||||
|
||||
#endif //__MEM_SERIAL_LINK_HH__
|
||||
Loading…
Reference in a new issue