603 commits

Author	SHA1	Message	Date
Gene Wu	aa601750f8	ARM: For non-cachable accesses set the UNCACHABLE flag	2010-08-23 11:18:41 -05:00
Gene Wu	7405f4b774	ARM: Implement DSB, DMB, ISB	2010-08-23 11:18:41 -05:00
Gene Wu	aabf478920	ARM: Get SCTLR TE bit from reset SCTLR	2010-08-23 11:18:41 -05:00
Gene Wu	1f032ad345	ARM: Implement CLREX	2010-08-23 11:18:41 -05:00
Gene Wu	66bcbec96e	ARM: BX instruction can be contitional if last instruction in a IT block ... Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond.	2010-08-23 11:18:41 -05:00
Min Kyu Jeong	92ae620be8	ARM: mark msr/mrs instructions as SerializeBefore/After ... Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR	2010-08-23 11:18:41 -05:00
Min Kyu Jeong	5f91ec3f46	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. ... THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.	2010-08-23 11:18:40 -05:00
Min Kyu Jeong	7acf67971c	ARM: adding genMachineCheckFault() stub for ARM that doesn't panic	2010-08-23 11:18:40 -05:00
Gene Wu	5486fa6612	ARM: DFSR status value for sync external data abort is expected to be 0x8 in ARMv7	2010-08-23 11:18:40 -05:00
Gene Wu	a993188034	ARM: Temporary local variables can't conflict with isa parser operands. ... PC is an operand, so we can't have a temp called PC	2010-08-23 11:18:40 -05:00
Ali Saidi	0c434b7f56	ARM: Exclusive accesses must be double word aligned	2010-08-23 11:18:40 -05:00
Ali Saidi	5148c693d8	ARM: Add some registers for big loads/stores to support neon.	2010-08-23 11:18:40 -05:00
Ali Saidi	fc1730044e	ARM: Decode neon memory instructions.	2010-08-23 11:18:40 -05:00
Gabe Black	d1362d582a	ARM: Clean up the ISA desc portion of the ARM memory instructions.	2010-08-23 11:18:40 -05:00
Ali Saidi	230acc291c	ARM: We don't currently support ThumbEE exceptions, so don't report that we do	2010-08-23 11:18:40 -05:00
Ali Saidi	bb5377899a	ARM: Add system for ARM/Linux and bootstrapping	2010-08-23 11:18:40 -05:00
Ali Saidi	38cf6a164d	ARM: Implement some more misc registers	2010-08-23 11:18:40 -05:00
Ali Saidi	b7b2eae6fa	ARM: Fix an un-initialized variable bug	2010-08-23 11:18:39 -05:00
Ali Saidi	f2642e2055	Loader: Make the load address mask be a parameter of the system rather than a constant. ... This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0.	2010-08-23 11:18:39 -05:00
Min Kyu Jeong	d4e83a4001	ARM: Finish the timing translation when taking a fault.	2010-08-23 11:18:39 -05:00
Dam Sunwoo	cb76111a7e	ARM: Use a stl queue for the table walker state	2010-08-23 11:18:39 -05:00
Ali Saidi	ac575a9d82	Compiler: Fixes for GCC 4.5.	2010-08-23 11:18:39 -05:00
Steve Reinhardt	f064aa3060	sim: revamp unserialization procedure ... Replace direct call to unserialize() on each SimObject with a pair of calls for better control over initialization in both ckpt and non-ckpt cases. If restoring from a checkpoint, loadState(ckpt) is called on each SimObject. The default implementation simply calls unserialize() if there is a corresponding checkpoint section, so we get backward compatibility for existing objects. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found. (Note that the default warning for a missing checkpoint section is now gone.) If not restoring from a checkpoint, we call the new initState() method on each SimObject instead. This provides a hook for state initializations that are only required when *not* restoring from a checkpoint. Given this new framework, do some cleanup of LiveProcess subclasses and X86System, which were (in some cases) emulating initState() behavior in startup via a local flag or (in other cases) erroneously doing initializations in startup() that clobbered state loaded earlier by unserialize().	2010-08-17 05:17:06 -07:00
Gabe Black	8cec870568	ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault.	2010-07-15 02:11:56 -07:00
Gabe Black	4e3183cb1e	ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index.	2010-07-13 22:41:47 -07:00
Nathan Binkert	86a93fe7b9	stats: only consider a formula initialized if there is a formula	2010-06-15 01:18:36 -07:00
Ali Saidi	d2186857b1	ARM: Fix issue with m5.fast and ARM	2010-06-03 12:20:49 -04:00
Ali Saidi	5268067f14	ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all ... Spec2k benchmarks seem to run with atomic or timing mode simple CPUs. Fixed up some constants, handling of 64 bit arguments, and marked a few more syscalls ignoreFunc.	2010-06-02 12:58:18 -05:00
Min Kyu Jeong	5d5bf8cbc7	ARM: Fix IT state not updating when an instruction memory instruction faults.	2010-06-02 12:58:18 -05:00
Dam Sunwoo	4325519fc5	ARM: Allow multiple outstanding TLB walks to queue.	2010-06-02 12:58:18 -05:00
Ali Saidi	2bad5138e4	ARM TLB: Fix bug in memAttrs getting a bogus thread context	2010-06-02 12:58:18 -05:00
Dam Sunwoo	6b00c7fa22	ARM: Support table walks in timing mode.	2010-06-02 12:58:18 -05:00
Dam Sunwoo	6c8dd32fa4	ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PCWUR, V2PCWUW,...)	2010-06-02 12:58:18 -05:00
Gabe Black	85ba2a3243	ARM: Decode the neon instruction space.	2010-06-02 12:58:18 -05:00
Gabe Black	e50e6a260f	ARM: Add a comment to vfp.cc that explains the asm statements.	2010-06-02 12:58:18 -05:00
Gabe Black	10031a0327	ARM: Move some case values out of ##included files. ... This will help keep the high level decode together and not have it spread into the subordinate decode stuff. The ##include lines still need to be on a line by themselves, though.	2010-06-02 12:58:18 -05:00
Gabe Black	22f15ab94e	ARM: Combine some redundant cases in one of the data decode functions.	2010-06-02 12:58:18 -05:00
Gabe Black	fcee2b3f31	ARM: Add comments to the classes in macromem.hh.	2010-06-02 12:58:18 -05:00
Gabe Black	362b747fdc	ARM: Move code from vfp.hh to vfp.cc.	2010-06-02 12:58:18 -05:00
Ali Saidi	35e35fc825	ARM: Make some of the trace code more compact	2010-06-02 12:58:18 -05:00
Gabe Black	0abec53564	ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.	2010-06-02 12:58:18 -05:00
Gabe Black	9223725973	ARM: Move the ISA "clear" function into isa.cc.	2010-06-02 12:58:17 -05:00
Gabe Black	b6c2548a27	ARM: Get rid of the binary dumping function in utility.hh.	2010-06-02 12:58:17 -05:00
Gabe Black	f8d2ed708b	ARM: Get rid of the empty branch.cc.	2010-06-02 12:58:17 -05:00
Gabe Black	0c574987c8	ARM: Mark some ARM static inst functions as inline.	2010-06-02 12:58:17 -05:00
Gabe Black	ba7a7b0394	ARM: Move some predecoder stuff into a .cc file. ... --HG-- rename : src/arch/arm/predecoder.hh => src/arch/arm/predecoder.cc	2010-06-02 12:58:17 -05:00
Gabe Black	358fdc2a40	ARM: Decode to specialized conditional/unconditional versions of instructions. ... This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them.	2010-06-02 12:58:17 -05:00
Gabe Black	596cbe19d4	ARM: Make sure undefined unconditional ARM instructions decode as such.	2010-06-02 12:58:17 -05:00
Gabe Black	6101e1b062	ARM: Implement a version of mcr and mrc that works in user mode.	2010-06-02 12:58:17 -05:00
Gabe Black	e91e6ff9a4	ARM: Hook the misc instructions into the thumb decoder.	2010-06-02 12:58:17 -05:00
Gabe Black	22d1a84509	ARM: Move some miscellaneous instructions out of the decoder to share with thumb.	2010-06-02 12:58:17 -05:00
Gabe Black	0e556e9dfb	ARM: Treat LDRD in ARM with an odd index as an undefined instruction.	2010-06-02 12:58:17 -05:00
Ali Saidi	3dc6a8070e	ARM: fix sizes of structs for ARM Linux	2010-06-02 12:58:17 -05:00
Ali Saidi	d3a519ef0c	ARM: Fixup native trace support and add some v7/recent stack code	2010-06-02 12:58:17 -05:00
Gabe Black	5a6bf8301a	ARM: Detect a bad offset field for the VFP Ldm/Stm instructions in the decoder.	2010-06-02 12:58:17 -05:00
Gabe Black	563db6cb99	ARM: Make sure the upc is zeroed when vectoring to a fault.	2010-06-02 12:58:17 -05:00
Ali Saidi	5d67be7b1e	ARM: Implement the getrusage syscall.	2010-06-02 12:58:17 -05:00
Gabe Black	6e39288be0	ARM: Implement the bkpt instruction.	2010-06-02 12:58:16 -05:00
Gabe Black	e9c8f68c0f	ARM: Make undefined instructions obey predication.	2010-06-02 12:58:16 -05:00
Gabe Black	05bd3eb4ec	ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.	2010-06-02 12:58:16 -05:00
Gabe Black	b93ceef538	ARM: Get rid of some of the old FP implementation.	2010-06-02 12:58:16 -05:00
Ali Saidi	c1e1de8d69	ARM: Some TLB bug fixes.	2010-06-02 12:58:16 -05:00
Ali Saidi	7de7ea3b22	ARM: Move Miscreg functions out of isa.hh	2010-06-02 12:58:16 -05:00
Ali Saidi	cb9936cfde	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	2010-06-02 12:58:16 -05:00
Ali Saidi	1546d8208b	ARM: SE needs a definition for PageTable::serialize/unserialize	2010-06-02 12:58:16 -05:00
Ali Saidi	d2ba9243f5	ARM: Add BKPT instruction ... --HG-- rename : src/arch/arm/isa/formats/unknown.isa => src/arch/arm/isa/formats/breakpoint.isa	2010-06-02 12:58:16 -05:00
Ali Saidi	b8ec214553	ARM: Implement ARM CPU interrupts	2010-06-02 12:58:16 -05:00
Ali Saidi	3aea20d143	ARM: Start over with translation from Alpha code as opposed to something that has cruft from 4 different ISAs.	2010-06-02 12:58:16 -05:00
Gabe Black	237c0617a0	ARM: Implement conversion to/from half precision.	2010-06-02 12:58:16 -05:00
Gabe Black	04e196f422	ARM: Clean up VFP	2010-06-02 12:58:16 -05:00
Gabe Black	0fe0390f73	ARM: Clean up the implementation of the VFP instructions.	2010-06-02 12:58:16 -05:00
Gabe Black	c919ab5b4f	ARM: Fix double precision load/store multiple decrement. ... When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.	2010-06-02 12:58:15 -05:00
Gabe Black	92bdf57be4	ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them to do nothing.	2010-06-02 12:58:15 -05:00
Gabe Black	4398075254	ARM: Make various bits of the FP control registers read only.	2010-06-02 12:58:15 -05:00
Gabe Black	2d08b8de91	ARM: Implement the version of VMRS that writes to the APSR.	2010-06-02 12:58:15 -05:00
Gabe Black	57c4d37c10	ARM: Ignore reads and writes to DCIMVAC.	2010-06-02 12:58:15 -05:00
Gabe Black	fd37095fa6	ARM: Make MPIDR return 0 and ignore writes.	2010-06-02 12:58:15 -05:00
Gabe Black	49b7088b91	ARM: Implement the VCMPE instruction.	2010-06-02 12:58:15 -05:00
Gabe Black	23ba9c7b96	ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR.	2010-06-02 12:58:15 -05:00
Gabe Black	1fda944716	ARM: Fix saturation of VCVT from fp to integer.	2010-06-02 12:58:15 -05:00
Gabe Black	347ab6c704	ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's after.	2010-06-02 12:58:15 -05:00
Gabe Black	fd82a47b96	ARM: Implement flush to zero for destinations as well.	2010-06-02 12:58:15 -05:00
Gabe Black	186273e5f3	ARM: Fix up nans to match ARM's expected behavior.	2010-06-02 12:58:15 -05:00
Gabe Black	98e2315f1c	ARM: Set the value of the MVFR0 and MVFR1 registers.	2010-06-02 12:58:15 -05:00
Gabe Black	8466999aef	ARM: Implement flush to zero mode for VFP, and clean up some corner cases.	2010-06-02 12:58:15 -05:00
Gabe Black	efbceff96a	ARM: Add barriers that make sure FP operations happen where they're supposed to.	2010-06-02 12:58:15 -05:00
Gabe Black	1b3b75ee68	ARM: Implement the version of VCVT float to int that rounds towards zero.	2010-06-02 12:58:15 -05:00
Gabe Black	aa05e5401c	ARM: Implement the floating/fixed point VCVT instructions.	2010-06-02 12:58:15 -05:00
Gabe Black	86a1093992	ARM: Add code to extract and record VFP exceptions.	2010-06-02 12:58:14 -05:00
Gabe Black	e478df35f5	ARM: Implement the VFP version of VCMP.	2010-06-02 12:58:14 -05:00
Gabe Black	c1f7bf7f0e	ARM: Add support for VFP vector mode.	2010-06-02 12:58:14 -05:00
Gabe Black	f245f4937b	ARM: Introduce new VFP base classes that are optionally microops.	2010-06-02 12:58:14 -05:00
Gabe Black	41012d2418	ARM: Implement VCVT between double and single width FP.	2010-06-02 12:58:14 -05:00
Gabe Black	a430f749ce	ARM: Implement vcvt between int and fp. Ignore rounding.	2010-06-02 12:58:14 -05:00
Gabe Black	a9d1de4769	ARM: Consolidate the VFP register index computation code.	2010-06-02 12:58:14 -05:00
Gabe Black	80fa3a7ccf	ARM: Implement the VFP negated multiplies.	2010-06-02 12:58:14 -05:00
Gabe Black	3111a62169	ARM: Implement the VFP versions of VMLA and VMLS.	2010-06-02 12:58:14 -05:00
Gabe Black	90d70a22cb	ARM: Implement the VFP version of vdiv and vsqrt.	2010-06-02 12:58:14 -05:00
Gabe Black	cc665240a4	ARM: Implement the VFP version of vsub.	2010-06-02 12:58:14 -05:00
Gabe Black	44759669aa	ARM: Implement the VFP version of vadd.	2010-06-02 12:58:14 -05:00
Gabe Black	9e32ff3491	ARM: Implement the VFP version of vabs.	2010-06-02 12:58:14 -05:00
Gabe Black	cd0a6a1303	ARM: Implement the VFP version of vneg.	2010-06-02 12:58:14 -05:00
Gabe Black	65f5204325	ARM: Implement the VFP version of vmul.	2010-06-02 12:58:14 -05:00
Gabe Black	19e05d7e8d	ARM: Move the VFP data operation decode into a function.	2010-06-02 12:58:14 -05:00
Gabe Black	527b735cfc	ARM: Implement and update the DFSR and IFSR registers on faults.	2010-06-02 12:58:14 -05:00
Gabe Black	4491170df6	ARM: Make integer division by zero return a fault.	2010-06-02 12:58:13 -05:00
Gabe Black	cd86e34187	ARM: Add in some missing SCTLR fields.	2010-06-02 12:58:13 -05:00
Gabe Black	c5a8a1d673	ARM: Decode ARM unconditional MRC and MCR instructions.	2010-06-02 12:58:13 -05:00
Gabe Black	98fe7b0fbe	ARM: Move the CP15 decode block into a function.	2010-06-02 12:58:13 -05:00
Gabe Black	5d9191a428	ARM: Decode the unconditional version of ARM fp instructions.	2010-06-02 12:58:13 -05:00
Gabe Black	81b7c3d264	ARM: Move the FP decode blocks into functions.	2010-06-02 12:58:13 -05:00
Gabe Black	e21f93702a	ARM: Warn/ignore when TLB maintenance operations are performed.	2010-06-02 12:58:13 -05:00
Gabe Black	eac239b4d6	ARM: Handle accesses to TLBTR.	2010-06-02 12:58:13 -05:00
Gabe Black	9fb573d91e	ARM: Handle accesses to the DACR.	2010-06-02 12:58:13 -05:00
Gabe Black	951b7edaba	ARM: Handle accesses to TTBR0 and TTBR1.	2010-06-02 12:58:13 -05:00
Gabe Black	b5cfa9361b	ARM: Convert the CP15 registers from MPU to MMU.	2010-06-02 12:58:13 -05:00
Ali Saidi	556ea0ee57	ARM: Add some support for wfi/wfe/yield/etc	2010-06-02 12:58:13 -05:00
Ali Saidi	5e6d28996a	ARM: Move PC mode bits around so they can be used for exectrace	2010-06-02 12:58:13 -05:00
Ali Saidi	aec73ba6af	ARM: Add a traceflag to print cpsr	2010-06-02 12:58:13 -05:00
Ali Saidi	65a5177b53	ARM: Undef instruction on invalid user CP15 access	2010-06-02 12:58:13 -05:00
Gabe Black	2e4ddbd234	ARM: Decode the VSTR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	6106bd18cd	ARM: Implement the vstr instruction.	2010-06-02 12:58:12 -05:00
Ali Saidi	f64c8bafd2	ARM: BXJ should be BX when there is no J support	2010-06-02 12:58:12 -05:00
Gabe Black	1fcd389fa3	ARM: Make sure macroops aren't interrupted midinstruction. ... Do this by setting the delayed commit flag for all but the last microop.	2010-06-02 12:58:12 -05:00
Gabe Black	67766cbf17	ARM: Fix the implementation of the VFP ldm and stm macroops. ... There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.	2010-06-02 12:58:12 -05:00
Gabe Black	ad9c5af945	ARM: Fix up thumb decoding of coproc instructions.	2010-06-02 12:58:12 -05:00
Gabe Black	dea707704f	ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC.	2010-06-02 12:58:12 -05:00
Gabe Black	943b77b9bb	ARM: Decode the VLDR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	4f130683e0	ARM: Implement the VLDR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	dbec303864	ARM: Decode all the various forms of vmov.	2010-06-02 12:58:12 -05:00
Gabe Black	ff3996b24d	ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.	2010-06-02 12:58:12 -05:00
Gabe Black	dd1aedc98b	ARM: Implement the various versions of VMOV.	2010-06-02 12:58:12 -05:00
Gabe Black	1f059541d6	ARM: Add a new RegImmOp base class.	2010-06-02 12:58:12 -05:00
Gabe Black	6976b4890a	ARM: Add a RegRegImmOp base class.	2010-06-02 12:58:12 -05:00
Gabe Black	186cfe3ae3	ARM: Widen the immediate fields in the misc instruction classes.	2010-06-02 12:58:12 -05:00
Gabe Black	b87ebf382f	ARM: Add a function to decode VFP modified immediate constants.	2010-06-02 12:58:12 -05:00
Gabe Black	7eb4d02dd9	ARM: Add a function to decode SIMD modified immediate constants.	2010-06-02 12:58:12 -05:00
Gabe Black	abda50173c	ARM: Add fp operands to operands.isa.	2010-06-02 12:58:12 -05:00
Gabe Black	6365d29c21	ARM: Decode the VMRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	fbf2ad5ae8	ARM: Update the set of FP related miscregs.	2010-06-02 12:58:11 -05:00
Gabe Black	aade63a8fe	ARM: Implement the VMRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	a8b56b452c	ARM: Decode the VMSR instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	06008c54eb	ARM: Implement the VMSR instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	0ff71c7c34	ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.	2010-06-02 12:58:11 -05:00
Gabe Black	c9c4dfc09d	ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.	2010-06-02 12:58:11 -05:00
Gabe Black	c3bf29bbea	ARM: Implement the udiv instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	f3e65c2de2	ARM: Implement the sdiv instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	5943f0fc84	ARM: Ignore writing a bad mode to CPSR with MSR.	2010-06-02 12:58:11 -05:00
Gabe Black	ba33db8fd6	ARM: Decode the CPS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	7861b084f6	ARM: Implement the CPS instruction.	2010-06-02 12:58:11 -05:00