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ARM: mark msr/mrs instructions as SerializeBefore/After

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Since miscellaneous registers bypass wakeup logic, force serialization
to resolve data dependencies through them
* * *
ARM: adding non-speculative/serialize flags for instructions change CPSR
This commit is contained in:
Min Kyu Jeong 2010-08-23 11:18:41 -05:00
parent 43c938d23e
commit 92ae620be8
4 changed files with 25 additions and 11 deletions
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27
src/arch/arm/isa/insts/misc.isa
View file

@ -63,7 +63,8 @@ let {{
mrsCpsrCode = "Dest = (Cpsr | CondCodes) & 0xF8FF03DF"
mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
{ "code": mrsCpsrCode,
"predicate_test": condPredicateTest }, [])
"predicate_test": condPredicateTest },
["IsSerializeAfter"])
header_output += MrsDeclare.subst(mrsCpsrIop)
decoder_output += MrsConstructor.subst(mrsCpsrIop)
exec_output += PredOpExecute.subst(mrsCpsrIop)
@ -71,7 +72,8 @@ let {{
mrsSpsrCode = "Dest = Spsr"
mrsSpsrIop = InstObjParams("mrs", "MrsSpsr", "MrsOp",
{ "code": mrsSpsrCode,
"predicate_test": predicateTest }, [])
"predicate_test": predicateTest },
["IsSerializeAfter"])
header_output += MrsDeclare.subst(mrsSpsrIop)
decoder_output += MrsConstructor.subst(mrsSpsrIop)
exec_output += PredOpExecute.subst(mrsSpsrIop)
@ -85,7 +87,8 @@ let {{
'''
msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
{ "code": msrCpsrRegCode,
"predicate_test": condPredicateTest }, [])
"predicate_test": condPredicateTest },
["IsSerializeAfter","IsNonSpeculative"])
header_output += MsrRegDeclare.subst(msrCpsrRegIop)
decoder_output += MsrRegConstructor.subst(msrCpsrRegIop)
exec_output += PredOpExecute.subst(msrCpsrRegIop)
@ -93,7 +96,8 @@ let {{
msrSpsrRegCode = "Spsr = spsrWriteByInstr(Spsr, Op1, byteMask, false);"
msrSpsrRegIop = InstObjParams("msr", "MsrSpsrReg", "MsrRegOp",
{ "code": msrSpsrRegCode,
"predicate_test": predicateTest }, [])
"predicate_test": predicateTest },
["IsSerializeAfter","IsNonSpeculative"])
header_output += MsrRegDeclare.subst(msrSpsrRegIop)
decoder_output += MsrRegConstructor.subst(msrSpsrRegIop)
exec_output += PredOpExecute.subst(msrSpsrRegIop)
@ -107,7 +111,8 @@ let {{
'''
msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
{ "code": msrCpsrImmCode,
"predicate_test": condPredicateTest }, [])
"predicate_test": condPredicateTest },
["IsSerializeAfter","IsNonSpeculative"])
header_output += MsrImmDeclare.subst(msrCpsrImmIop)
decoder_output += MsrImmConstructor.subst(msrCpsrImmIop)
exec_output += PredOpExecute.subst(msrCpsrImmIop)
@ -115,7 +120,8 @@ let {{
msrSpsrImmCode = "Spsr = spsrWriteByInstr(Spsr, imm, byteMask, false);"
msrSpsrImmIop = InstObjParams("msr", "MsrSpsrImm", "MsrImmOp",
{ "code": msrSpsrImmCode,
"predicate_test": predicateTest }, [])
"predicate_test": predicateTest },
["IsSerializeAfter","IsNonSpeculative"])
header_output += MsrImmDeclare.subst(msrSpsrImmIop)
decoder_output += MsrImmConstructor.subst(msrSpsrImmIop)
exec_output += PredOpExecute.subst(msrSpsrImmIop)
@ -609,7 +615,8 @@ let {{
'''
mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
{ "code": mcr15code,
"predicate_test": predicateTest }, [])
"predicate_test": predicateTest },
["IsSerializeAfter","IsNonSpeculative"])
header_output += RegRegOpDeclare.subst(mcr15Iop)
decoder_output += RegRegOpConstructor.subst(mcr15Iop)
exec_output += PredOpExecute.subst(mcr15Iop)
@ -623,7 +630,8 @@ let {{
mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp",
{ "code": "MiscDest = Op1",
"predicate_test": predicateTest }, [])
"predicate_test": predicateTest },
["IsSerializeAfter","IsNonSpeculative"])
header_output += RegRegOpDeclare.subst(mcr15UserIop)
decoder_output += RegRegOpConstructor.subst(mcr15UserIop)
exec_output += PredOpExecute.subst(mcr15UserIop)
@ -687,7 +695,8 @@ let {{
'''
cpsIop = InstObjParams("cps", "Cps", "ImmOp",
{ "code": cpsCode,
"predicate_test": predicateTest }, [])
"predicate_test": predicateTest },
["IsSerializeAfter","IsNonSpeculative"])
header_output += ImmOpDeclare.subst(cpsIop)
decoder_output += ImmOpConstructor.subst(cpsIop)
exec_output += PredOpExecute.subst(cpsIop)

2
src/cpu/base_dyn_inst_impl.hh
View file

@ -321,6 +321,8 @@ template <class Impl>
void
BaseDynInst<Impl>::markSrcRegReady()
{
DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
if (++readyRegs == numSrcRegs()) {
setCanIssue();
}

1
src/cpu/o3/iew_impl.hh
View file

@ -1192,6 +1192,7 @@ DefaultIEW<Impl>::executeInsts()
}
// Uncomment this if you want to see all available instructions.
// @todo This doesn't actually work anymore, we should fix it.
// printAvailableInsts();
// Execute/writeback any instructions that are available.

6
src/cpu/o3/inst_queue_impl.hh
View file

@ -896,6 +896,8 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
// handled by the IQ and thus have no dependency graph entry.
// @todo Figure out a cleaner way to handle this.
if (dest_reg >= numPhysRegs) {
DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
numPhysRegs);
continue;
}
@ -907,8 +909,8 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
DynInstPtr dep_inst = dependGraph.pop(dest_reg);
while (dep_inst) {
DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
dep_inst->readPC());
DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
"PC%#x.\n", dep_inst->seqNum, dep_inst->readPC());
// Might want to give more information to the instruction
// so that it knows which of its source registers is