2205 commits

Author	SHA1	Message	Date
Ali Saidi	3dc6a8070e	ARM: fix sizes of structs for ARM Linux	2010-06-02 12:58:17 -05:00
Ali Saidi	d3a519ef0c	ARM: Fixup native trace support and add some v7/recent stack code	2010-06-02 12:58:17 -05:00
Gabe Black	5a6bf8301a	ARM: Detect a bad offset field for the VFP Ldm/Stm instructions in the decoder.	2010-06-02 12:58:17 -05:00
Gabe Black	563db6cb99	ARM: Make sure the upc is zeroed when vectoring to a fault.	2010-06-02 12:58:17 -05:00
Ali Saidi	5d67be7b1e	ARM: Implement the getrusage syscall.	2010-06-02 12:58:17 -05:00
Gabe Black	6e39288be0	ARM: Implement the bkpt instruction.	2010-06-02 12:58:16 -05:00
Gabe Black	e9c8f68c0f	ARM: Make undefined instructions obey predication.	2010-06-02 12:58:16 -05:00
Gabe Black	05bd3eb4ec	ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.	2010-06-02 12:58:16 -05:00
Gabe Black	b93ceef538	ARM: Get rid of some of the old FP implementation.	2010-06-02 12:58:16 -05:00
Ali Saidi	c1e1de8d69	ARM: Some TLB bug fixes.	2010-06-02 12:58:16 -05:00
Ali Saidi	7de7ea3b22	ARM: Move Miscreg functions out of isa.hh	2010-06-02 12:58:16 -05:00
Ali Saidi	cb9936cfde	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	2010-06-02 12:58:16 -05:00
Ali Saidi	1546d8208b	ARM: SE needs a definition for PageTable::serialize/unserialize	2010-06-02 12:58:16 -05:00
Ali Saidi	d2ba9243f5	ARM: Add BKPT instruction ... --HG-- rename : src/arch/arm/isa/formats/unknown.isa => src/arch/arm/isa/formats/breakpoint.isa	2010-06-02 12:58:16 -05:00
Ali Saidi	b8ec214553	ARM: Implement ARM CPU interrupts	2010-06-02 12:58:16 -05:00
Ali Saidi	3aea20d143	ARM: Start over with translation from Alpha code as opposed to something that has cruft from 4 different ISAs.	2010-06-02 12:58:16 -05:00
Gabe Black	237c0617a0	ARM: Implement conversion to/from half precision.	2010-06-02 12:58:16 -05:00
Gabe Black	04e196f422	ARM: Clean up VFP	2010-06-02 12:58:16 -05:00
Gabe Black	0fe0390f73	ARM: Clean up the implementation of the VFP instructions.	2010-06-02 12:58:16 -05:00
Gabe Black	c919ab5b4f	ARM: Fix double precision load/store multiple decrement. ... When decrementing, the higher addressed half of a double word is at a 4 byte smaller displacement.	2010-06-02 12:58:15 -05:00
Gabe Black	92bdf57be4	ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make them to do nothing.	2010-06-02 12:58:15 -05:00
Gabe Black	4398075254	ARM: Make various bits of the FP control registers read only.	2010-06-02 12:58:15 -05:00
Gabe Black	2d08b8de91	ARM: Implement the version of VMRS that writes to the APSR.	2010-06-02 12:58:15 -05:00
Gabe Black	57c4d37c10	ARM: Ignore reads and writes to DCIMVAC.	2010-06-02 12:58:15 -05:00
Gabe Black	fd37095fa6	ARM: Make MPIDR return 0 and ignore writes.	2010-06-02 12:58:15 -05:00
Gabe Black	49b7088b91	ARM: Implement the VCMPE instruction.	2010-06-02 12:58:15 -05:00
Gabe Black	23ba9c7b96	ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR.	2010-06-02 12:58:15 -05:00
Gabe Black	1fda944716	ARM: Fix saturation of VCVT from fp to integer.	2010-06-02 12:58:15 -05:00
Gabe Black	347ab6c704	ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's after.	2010-06-02 12:58:15 -05:00
Gabe Black	fd82a47b96	ARM: Implement flush to zero for destinations as well.	2010-06-02 12:58:15 -05:00
Gabe Black	186273e5f3	ARM: Fix up nans to match ARM's expected behavior.	2010-06-02 12:58:15 -05:00
Gabe Black	98e2315f1c	ARM: Set the value of the MVFR0 and MVFR1 registers.	2010-06-02 12:58:15 -05:00
Gabe Black	8466999aef	ARM: Implement flush to zero mode for VFP, and clean up some corner cases.	2010-06-02 12:58:15 -05:00
Gabe Black	efbceff96a	ARM: Add barriers that make sure FP operations happen where they're supposed to.	2010-06-02 12:58:15 -05:00
Gabe Black	1b3b75ee68	ARM: Implement the version of VCVT float to int that rounds towards zero.	2010-06-02 12:58:15 -05:00
Gabe Black	aa05e5401c	ARM: Implement the floating/fixed point VCVT instructions.	2010-06-02 12:58:15 -05:00
Gabe Black	86a1093992	ARM: Add code to extract and record VFP exceptions.	2010-06-02 12:58:14 -05:00
Gabe Black	e478df35f5	ARM: Implement the VFP version of VCMP.	2010-06-02 12:58:14 -05:00
Gabe Black	c1f7bf7f0e	ARM: Add support for VFP vector mode.	2010-06-02 12:58:14 -05:00
Gabe Black	f245f4937b	ARM: Introduce new VFP base classes that are optionally microops.	2010-06-02 12:58:14 -05:00
Gabe Black	41012d2418	ARM: Implement VCVT between double and single width FP.	2010-06-02 12:58:14 -05:00
Gabe Black	a430f749ce	ARM: Implement vcvt between int and fp. Ignore rounding.	2010-06-02 12:58:14 -05:00
Gabe Black	a9d1de4769	ARM: Consolidate the VFP register index computation code.	2010-06-02 12:58:14 -05:00
Gabe Black	80fa3a7ccf	ARM: Implement the VFP negated multiplies.	2010-06-02 12:58:14 -05:00
Gabe Black	3111a62169	ARM: Implement the VFP versions of VMLA and VMLS.	2010-06-02 12:58:14 -05:00
Gabe Black	90d70a22cb	ARM: Implement the VFP version of vdiv and vsqrt.	2010-06-02 12:58:14 -05:00
Gabe Black	cc665240a4	ARM: Implement the VFP version of vsub.	2010-06-02 12:58:14 -05:00
Gabe Black	44759669aa	ARM: Implement the VFP version of vadd.	2010-06-02 12:58:14 -05:00
Gabe Black	9e32ff3491	ARM: Implement the VFP version of vabs.	2010-06-02 12:58:14 -05:00
Gabe Black	cd0a6a1303	ARM: Implement the VFP version of vneg.	2010-06-02 12:58:14 -05:00
Gabe Black	65f5204325	ARM: Implement the VFP version of vmul.	2010-06-02 12:58:14 -05:00
Gabe Black	19e05d7e8d	ARM: Move the VFP data operation decode into a function.	2010-06-02 12:58:14 -05:00
Gabe Black	527b735cfc	ARM: Implement and update the DFSR and IFSR registers on faults.	2010-06-02 12:58:14 -05:00
Gabe Black	4491170df6	ARM: Make integer division by zero return a fault.	2010-06-02 12:58:13 -05:00
Gabe Black	cd86e34187	ARM: Add in some missing SCTLR fields.	2010-06-02 12:58:13 -05:00
Gabe Black	c5a8a1d673	ARM: Decode ARM unconditional MRC and MCR instructions.	2010-06-02 12:58:13 -05:00
Gabe Black	98fe7b0fbe	ARM: Move the CP15 decode block into a function.	2010-06-02 12:58:13 -05:00
Gabe Black	5d9191a428	ARM: Decode the unconditional version of ARM fp instructions.	2010-06-02 12:58:13 -05:00
Gabe Black	81b7c3d264	ARM: Move the FP decode blocks into functions.	2010-06-02 12:58:13 -05:00
Gabe Black	e21f93702a	ARM: Warn/ignore when TLB maintenance operations are performed.	2010-06-02 12:58:13 -05:00
Gabe Black	eac239b4d6	ARM: Handle accesses to TLBTR.	2010-06-02 12:58:13 -05:00
Gabe Black	9fb573d91e	ARM: Handle accesses to the DACR.	2010-06-02 12:58:13 -05:00
Gabe Black	951b7edaba	ARM: Handle accesses to TTBR0 and TTBR1.	2010-06-02 12:58:13 -05:00
Gabe Black	b5cfa9361b	ARM: Convert the CP15 registers from MPU to MMU.	2010-06-02 12:58:13 -05:00
Ali Saidi	556ea0ee57	ARM: Add some support for wfi/wfe/yield/etc	2010-06-02 12:58:13 -05:00
Ali Saidi	5e6d28996a	ARM: Move PC mode bits around so they can be used for exectrace	2010-06-02 12:58:13 -05:00
Ali Saidi	aec73ba6af	ARM: Add a traceflag to print cpsr	2010-06-02 12:58:13 -05:00
Ali Saidi	65a5177b53	ARM: Undef instruction on invalid user CP15 access	2010-06-02 12:58:13 -05:00
Gabe Black	2e4ddbd234	ARM: Decode the VSTR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	6106bd18cd	ARM: Implement the vstr instruction.	2010-06-02 12:58:12 -05:00
Ali Saidi	f64c8bafd2	ARM: BXJ should be BX when there is no J support	2010-06-02 12:58:12 -05:00
Gabe Black	1fcd389fa3	ARM: Make sure macroops aren't interrupted midinstruction. ... Do this by setting the delayed commit flag for all but the last microop.	2010-06-02 12:58:12 -05:00
Gabe Black	67766cbf17	ARM: Fix the implementation of the VFP ldm and stm macroops. ... There were four bugs in these instructions. First, the loaded value was being stored into a floating point register as floating point, changing the value as it was transfered. Second, the meaning of the "up" bit had been reversed. Third, the statically sized microop array wasn't bit enough for all possible inputs. It's now dynamically sized and should always be big enough. Fourth, the offset was stored as an unsigned 8 bit value. Negative offsets would look like moderately large positive offsets.	2010-06-02 12:58:12 -05:00
Gabe Black	ad9c5af945	ARM: Fix up thumb decoding of coproc instructions.	2010-06-02 12:58:12 -05:00
Gabe Black	dea707704f	ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC.	2010-06-02 12:58:12 -05:00
Gabe Black	943b77b9bb	ARM: Decode the VLDR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	4f130683e0	ARM: Implement the VLDR instruction.	2010-06-02 12:58:12 -05:00
Gabe Black	dbec303864	ARM: Decode all the various forms of vmov.	2010-06-02 12:58:12 -05:00
Gabe Black	ff3996b24d	ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.	2010-06-02 12:58:12 -05:00
Gabe Black	dd1aedc98b	ARM: Implement the various versions of VMOV.	2010-06-02 12:58:12 -05:00
Gabe Black	1f059541d6	ARM: Add a new RegImmOp base class.	2010-06-02 12:58:12 -05:00
Gabe Black	6976b4890a	ARM: Add a RegRegImmOp base class.	2010-06-02 12:58:12 -05:00
Gabe Black	186cfe3ae3	ARM: Widen the immediate fields in the misc instruction classes.	2010-06-02 12:58:12 -05:00
Gabe Black	b87ebf382f	ARM: Add a function to decode VFP modified immediate constants.	2010-06-02 12:58:12 -05:00
Gabe Black	7eb4d02dd9	ARM: Add a function to decode SIMD modified immediate constants.	2010-06-02 12:58:12 -05:00
Gabe Black	abda50173c	ARM: Add fp operands to operands.isa.	2010-06-02 12:58:12 -05:00
Gabe Black	6365d29c21	ARM: Decode the VMRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	fbf2ad5ae8	ARM: Update the set of FP related miscregs.	2010-06-02 12:58:11 -05:00
Gabe Black	aade63a8fe	ARM: Implement the VMRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	a8b56b452c	ARM: Decode the VMSR instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	06008c54eb	ARM: Implement the VMSR instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	0ff71c7c34	ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.	2010-06-02 12:58:11 -05:00
Gabe Black	c9c4dfc09d	ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.	2010-06-02 12:58:11 -05:00
Gabe Black	c3bf29bbea	ARM: Implement the udiv instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	f3e65c2de2	ARM: Implement the sdiv instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	5943f0fc84	ARM: Ignore writing a bad mode to CPSR with MSR.	2010-06-02 12:58:11 -05:00
Gabe Black	ba33db8fd6	ARM: Decode the CPS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	7861b084f6	ARM: Implement the CPS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	eb1447302d	ARM: Decode the SRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	bb6fea91da	ARM: Implement the SRS instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	dbee6e0c54	ARM: Add a base class for SRS.	2010-06-02 12:58:11 -05:00
Gabe Black	239c9af90d	ARM: Implement a badMode function that says whether a mode is legal.	2010-06-02 12:58:11 -05:00
Gabe Black	a5ea52bb45	ARM: Allow flattening into any mode.	2010-06-02 12:58:11 -05:00
Gabe Black	698ee26c6b	ARM: Decode TBB and TBH.	2010-06-02 12:58:11 -05:00
Gabe Black	6fa713a66c	ARM: Decode the setend instruction.	2010-06-02 12:58:11 -05:00
Gabe Black	4683cd1655	ARM: Define the setend instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	fb23297914	ARM: Make a base class for instructions that use only an immediate.	2010-06-02 12:58:10 -05:00
Gabe Black	247acd93c4	ARM: Decode the arm version of ldrexd.	2010-06-02 12:58:10 -05:00
Gabe Black	3ad31f61c2	ARM: Decode the strex instructions.	2010-06-02 12:58:10 -05:00
Gabe Black	54ab07e636	ARM: Implement the strex instructions.	2010-06-02 12:58:10 -05:00
Gabe Black	524a8195e1	ARM: Set CPSR.E to SCTLR.EE on faults.	2010-06-02 12:58:10 -05:00
Gabe Black	683421e0c6	ARM: Warn about not implementing MPU translation, not panic about MMU. ... We'll start out with a stbu version of PMSA and switch over to VMSA for the full implementation.	2010-06-02 12:58:10 -05:00
Gabe Black	6fb5189c47	ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.	2010-06-02 12:58:10 -05:00
Gabe Black	89b1dd5582	ARM: Allow access to the RGNR register.	2010-06-02 12:58:10 -05:00
Gabe Black	c3381167c9	ARM: Make the MPUIR register report that 1 unified data region is supported.	2010-06-02 12:58:10 -05:00
Gabe Black	3aa8faf177	ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.	2010-06-02 12:58:10 -05:00
Gabe Black	faf6c727f6	ARM: Respect the E bit of the CPSR when doing loads and stores.	2010-06-02 12:58:10 -05:00
Gabe Black	b6cb6f1874	ARM: Zero the micropc when vectoring to a fault.	2010-06-02 12:58:10 -05:00
Gabe Black	1d5233958a	ARM: Implement the V7 version of alignment checking.	2010-06-02 12:58:10 -05:00
Gabe Black	7b397925af	ARM: Decode the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	a2cb503ba6	ARM: Implement the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	ec4cd00b11	ARM: Add a base class for the RFE instruction.	2010-06-02 12:58:10 -05:00
Gabe Black	1ada9d4880	ARM: Make sure some undefined thumb32 instructions fault.	2010-06-02 12:58:10 -05:00
Gabe Black	3caa75d53a	ARM: Squash the low order bits of the PC when performing a regular branch.	2010-06-02 12:58:10 -05:00
Gabe Black	36eeee0133	ARM: When changing the CPSR and branching, make sure the branch is second.	2010-06-02 12:58:09 -05:00
Gabe Black	68f2908a70	ARM: Ignore/warn when CSSELR or CCSIDR are accessed. ... These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert.	2010-06-02 12:58:09 -05:00
Gabe Black	741b243260	ARM: Ignore/warn access to the bpimva registers.	2010-06-02 12:58:09 -05:00
Gabe Black	8a7f60194e	ARM: Ignore/warn on accesses to the dccmvac register.	2010-06-02 12:58:09 -05:00
Gabe Black	89133b15da	ARM: Decode the enterx and leavex instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	6a4ea7cca9	ARM: Implement the enterx and leavex instructions. ... These enter and leave thumbEE mode. Currently thumbEE mode behaves exactly the same as Thumb mode, but at least this will make it -look- like we're enter and leaving it. The actual behavioral changes will be implemented in future changes.	2010-06-02 12:58:09 -05:00
Gabe Black	eb0823c4f2	ARM: Fix the implementation of BX to work in thumbEE mode.	2010-06-02 12:58:09 -05:00
Gabe Black	bb0d390105	ARM: When an instruction is intentionally undefined, fault on it.	2010-06-02 12:58:09 -05:00
Gabe Black	61a5e71be7	ARM: Decode the thumb version of the ldrd and strd instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	9d4a1bf2ba	ARM: Explicitly keep track of the second destination for double loads/stores.	2010-06-02 12:58:09 -05:00
Gabe Black	28023f6f3d	ARM: Decode the thumb32 load byte/memory hint instructions.	2010-06-02 12:58:09 -05:00
Gabe Black	7a9dcdf99f	ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.	2010-06-02 12:58:09 -05:00
Gabe Black	a483d44d9f	ARM: Ignore/warn on accesses to icimvau.	2010-06-02 12:58:09 -05:00
Gabe Black	630f309a77	ARM: Ignore/warn on iciallu.	2010-06-02 12:58:09 -05:00
Gabe Black	d618121670	ARM: Ignore/warn on ICIALLUIS.	2010-06-02 12:58:09 -05:00
Gabe Black	e658b6fed4	ARM: Add support for the clidr register. ... This register will always report 0 caches as implemented. It's not clear how to find out how many there really are when dealing with an arbitrary hierarchy.	2010-06-02 12:58:09 -05:00
Gabe Black	896c7617c4	ARM: Decode the unimplemented data barrier CP15 accesses. ... These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier).	2010-06-02 12:58:09 -05:00
Gabe Black	af6b1667e9	ARM: Implement a stub of CPACR. ... This register controls access to the coprocessors. This doesn't actually implement it, it allows writes which don't turn anything off. In other words, it allows the simulated program to ask for what it already has.	2010-06-02 12:58:09 -05:00
Gabe Black	660270746b	ARM: Actually write the value of sctlr in ISA.clear().	2010-06-02 12:58:08 -05:00
Gabe Black	6c9ab5d898	ARM: Replace the ARM decode of CP15 MCR and MRC instructions.	2010-06-02 12:58:08 -05:00
Gabe Black	35f0c01fea	ARM: Decode the unimplemented cp15 instruction barrier.	2010-06-02 12:58:08 -05:00
Gabe Black	7932b86298	ARM: Ignore accesses to DCCIMVAC.	2010-06-02 12:58:08 -05:00
Gabe Black	6ae4d34a12	ARM: Allow accesses to the software thread id registers.	2010-06-02 12:58:08 -05:00
Gabe Black	54850e4d23	ARM: Allow accesses to the contextidr register.	2010-06-02 12:58:08 -05:00
Gabe Black	221e0ac523	ARM: Warn about and ignore accesses to DCCISW. ... This register is supposed to "Clean and invalidate data or unified cache line by set/way." Since there isn't a good way to do that, we'll just ignore these and warn about it.	2010-06-02 12:58:08 -05:00
Gabe Black	8c1be04af6	ARM: Decode the thumb versions of the mcr and mrc instructions.	2010-06-02 12:58:08 -05:00