Gabe Black
c3381167c9
ARM: Make the MPUIR register report that 1 unified data region is supported.
2010-06-02 12:58:10 -05:00
Gabe Black
3aa8faf177
ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.
2010-06-02 12:58:10 -05:00
Gabe Black
faf6c727f6
ARM: Respect the E bit of the CPSR when doing loads and stores.
2010-06-02 12:58:10 -05:00
Gabe Black
b6cb6f1874
ARM: Zero the micropc when vectoring to a fault.
2010-06-02 12:58:10 -05:00
Gabe Black
1d5233958a
ARM: Implement the V7 version of alignment checking.
2010-06-02 12:58:10 -05:00
Gabe Black
7b397925af
ARM: Decode the RFE instruction.
2010-06-02 12:58:10 -05:00
Gabe Black
a2cb503ba6
ARM: Implement the RFE instruction.
2010-06-02 12:58:10 -05:00
Gabe Black
ec4cd00b11
ARM: Add a base class for the RFE instruction.
2010-06-02 12:58:10 -05:00
Gabe Black
1ada9d4880
ARM: Make sure some undefined thumb32 instructions fault.
2010-06-02 12:58:10 -05:00
Gabe Black
3caa75d53a
ARM: Squash the low order bits of the PC when performing a regular branch.
2010-06-02 12:58:10 -05:00
Gabe Black
36eeee0133
ARM: When changing the CPSR and branching, make sure the branch is second.
2010-06-02 12:58:09 -05:00
Gabe Black
68f2908a70
ARM: Ignore/warn when CSSELR or CCSIDR are accessed.
...
These registers provide information about the caches. Since we can't provide
that information, these will be harmlessly inert.
2010-06-02 12:58:09 -05:00
Gabe Black
741b243260
ARM: Ignore/warn access to the bpimva registers.
2010-06-02 12:58:09 -05:00
Gabe Black
8a7f60194e
ARM: Ignore/warn on accesses to the dccmvac register.
2010-06-02 12:58:09 -05:00
Gabe Black
89133b15da
ARM: Decode the enterx and leavex instructions.
2010-06-02 12:58:09 -05:00
Gabe Black
6a4ea7cca9
ARM: Implement the enterx and leavex instructions.
...
These enter and leave thumbEE mode. Currently thumbEE mode behaves exactly the
same as Thumb mode, but at least this will make it -look- like we're enter and
leaving it. The actual behavioral changes will be implemented in future
changes.
2010-06-02 12:58:09 -05:00
Gabe Black
eb0823c4f2
ARM: Fix the implementation of BX to work in thumbEE mode.
2010-06-02 12:58:09 -05:00
Gabe Black
bb0d390105
ARM: When an instruction is intentionally undefined, fault on it.
2010-06-02 12:58:09 -05:00
Gabe Black
61a5e71be7
ARM: Decode the thumb version of the ldrd and strd instructions.
2010-06-02 12:58:09 -05:00
Gabe Black
9d4a1bf2ba
ARM: Explicitly keep track of the second destination for double loads/stores.
2010-06-02 12:58:09 -05:00
Gabe Black
28023f6f3d
ARM: Decode the thumb32 load byte/memory hint instructions.
2010-06-02 12:58:09 -05:00
Gabe Black
7a9dcdf99f
ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.
2010-06-02 12:58:09 -05:00
Gabe Black
a483d44d9f
ARM: Ignore/warn on accesses to icimvau.
2010-06-02 12:58:09 -05:00
Gabe Black
630f309a77
ARM: Ignore/warn on iciallu.
2010-06-02 12:58:09 -05:00
Gabe Black
d618121670
ARM: Ignore/warn on ICIALLUIS.
2010-06-02 12:58:09 -05:00
Gabe Black
e658b6fed4
ARM: Add support for the clidr register.
...
This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
2010-06-02 12:58:09 -05:00
Gabe Black
896c7617c4
ARM: Decode the unimplemented data barrier CP15 accesses.
...
These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory
Barrier).
2010-06-02 12:58:09 -05:00
Gabe Black
af6b1667e9
ARM: Implement a stub of CPACR.
...
This register controls access to the coprocessors. This doesn't actually
implement it, it allows writes which don't turn anything off. In other words,
it allows the simulated program to ask for what it already has.
2010-06-02 12:58:09 -05:00
Gabe Black
660270746b
ARM: Actually write the value of sctlr in ISA.clear().
2010-06-02 12:58:08 -05:00
Gabe Black
6c9ab5d898
ARM: Replace the ARM decode of CP15 MCR and MRC instructions.
2010-06-02 12:58:08 -05:00
Gabe Black
35f0c01fea
ARM: Decode the unimplemented cp15 instruction barrier.
2010-06-02 12:58:08 -05:00
Gabe Black
7932b86298
ARM: Ignore accesses to DCCIMVAC.
2010-06-02 12:58:08 -05:00
Gabe Black
6ae4d34a12
ARM: Allow accesses to the software thread id registers.
2010-06-02 12:58:08 -05:00
Gabe Black
54850e4d23
ARM: Allow accesses to the contextidr register.
2010-06-02 12:58:08 -05:00
Gabe Black
221e0ac523
ARM: Warn about and ignore accesses to DCCISW.
...
This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.
2010-06-02 12:58:08 -05:00
Gabe Black
8c1be04af6
ARM: Decode the thumb versions of the mcr and mrc instructions.
2010-06-02 12:58:08 -05:00
Gabe Black
625a43e7c7
ARM: Implement the mrc and mcr instructions.
2010-06-02 12:58:08 -05:00
Gabe Black
6c1b10043f
ARM: Rename the RevOp base class to something more generic.
2010-06-02 12:58:08 -05:00
Gabe Black
f9d1bba22a
ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.
2010-06-02 12:58:08 -05:00
Gabe Black
6aa229386d
ARM: Implement a function to decode CP15 registers to MiscReg indices.
2010-06-02 12:58:08 -05:00
Gabe Black
7ff24c8777
ARM: Decode the bfi and bfc instructions.
2010-06-02 12:58:08 -05:00
Gabe Black
a37b6b6bce
ARM: Implement the bfc and bfi instructions.
2010-06-02 12:58:08 -05:00
Gabe Black
5a63887617
ARM: Decode the ubfx and sbfx instructions.
2010-06-02 12:58:08 -05:00
Gabe Black
2e717558e2
ARM: Decode miscellaneous arm mode media instructions.
2010-06-02 12:58:08 -05:00
Gabe Black
09cc401848
ARM: Implement the ubfx and sbfx instructions.
2010-06-02 12:58:08 -05:00
Gabe Black
b1158e4938
ARM: Add a register, immediate, immediate to register base for [su]bfx.
2010-06-02 12:58:08 -05:00
Gabe Black
504ac6518b
ARM: Decode the clz instruction.
2010-06-02 12:58:08 -05:00
Gabe Black
2c94bf7f30
ARM: Implement the clz instruction.
2010-06-02 12:58:08 -05:00
Gabe Black
00320a53ab
ARM: Decode the rbit instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
5cc1bb6842
ARM: Implement the rbit instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
566b2ff20c
ARM: Decode the nop instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
b9cfe9a3db
ARM: Implement nop.
2010-06-02 12:58:07 -05:00
Gabe Black
a2d8dcebba
ARM: Decode the ldrex instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
952253483b
ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.
2010-06-02 12:58:07 -05:00
Gabe Black
f7f75ad053
ARM: Implement the ldrex instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
00baeb742d
ARM: Decode the usad8 and usada8 instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
8f566e5ee3
ARM: Implement the usad8 and usada8 instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
c643b1c274
ARM: Add a base class to support usada8.
2010-06-02 12:58:07 -05:00
Gabe Black
64ade8316e
ARM: Decode the sel instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
7fa6835a0c
ARM: Implement the sel instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
498f9d925e
ARM: Add a base class for the sel instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
f581fd3f89
ARM: Decode pkh instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
9ffc5e2ae6
ARM: Implement the pkh instruction.
2010-06-02 12:58:07 -05:00
Gabe Black
c4d09747a5
ARM: Decode the sign/zero extend instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
69365876d8
ARM: Implement zero/sign extend instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
554fb3774e
ARM: Add a base class for extend and add instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
cb2e3b0ace
ARM: Generalize the saturation instruction bases for use in other instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
a1208aa66d
ARM: Decode the 8/16 bit signed/unsigned add/subtract half instructions.
2010-06-02 12:58:07 -05:00
Gabe Black
cabf766a06
ARM: Implement the 8/16 bit signed/unsigned add/subtract half instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
82614b6f3a
ARM: Fix signed most significant multiply instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
3cff58602a
ARM: Fix multiply overflow flag setting.
2010-06-02 12:58:06 -05:00
Gabe Black
90c2284714
ARM: Decode the saturation instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
61b8e33225
ARM: Implement the saturation instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
c96f03a250
ARM: Implement base classes for the saturation instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
0aff168f1a
ARM: Decode the signed add/subtract and subtract/add instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
8ba812f1fb
ARM: Implement signed add/subtract and subtract/add.
2010-06-02 12:58:06 -05:00
Gabe Black
a895514d35
ARM: Decode the unsigned 8 and 16 bit add and subtract instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
3f12eb02ab
ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts.
2010-06-02 12:58:06 -05:00
Gabe Black
29acf9516c
ARM: Decode the unsigned saturating instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
be888e67e7
ARM: Implement the unsigned saturating instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
5495ebd68d
ARM: Decode the ssub instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
fd6e9f304e
ARM: Implement the ssub instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
bcf0454864
ARM: Decode the SADD8 and SADD16 instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
87975aa691
ARM: Implement the SADD8 and SADD16 instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
d70c31437a
ARM: Support instructions that set the GE bits when they write the condition codes.
2010-06-02 12:58:06 -05:00
Gabe Black
e32aaefe8c
ARM: Decode 32 bit thumb data processing register instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
f19b605aed
ARM: Decode the 16 bit thumb versions of the REV* instructions.
2010-06-02 12:58:06 -05:00
Gabe Black
15356af288
ARM: Decode the ARM version of the REV* instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
59c726b6f4
ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format.
2010-06-02 12:58:05 -05:00
Gabe Black
aa8493d7d1
ARM: Implement the REV* instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
c981a4de2b
ARM: Add base classes suitable for the REV* instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
57443a2144
ARM: Make LDM that loads the PC perform an interworking branch.
2010-06-02 12:58:05 -05:00
Gabe Black
1344fc2668
ARM: Decode the swp and swpb instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
e157b1f52a
ARM: Implement the swp and swpb instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
1884ed65bd
ARM: Decode MRS and MSR for thumb.
2010-06-02 12:58:05 -05:00
Gabe Black
ff3b21bc2b
ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.
2010-06-02 12:58:05 -05:00
Gabe Black
f0811eb208
ARM: Define versions of MSR and MRS outside the decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
f61bb9adb9
ARM: Hook up the push/pop versions of stm/ldm in thumb.
2010-06-02 12:58:05 -05:00
Gabe Black
a76ab8e040
ARM: Hook SVC into the thumb decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
cbdebf852e
ARM: Implement SVC (was SWI) outside of the decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
34032f97d6
ARM: Trigger system calls from the SupervisorCall invoke method.
...
This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.
2010-06-02 12:58:05 -05:00
Gabe Black
52460938cb
ARM: Fix multiply operations.
...
These fixes were provided by Ali and fix the saturation condition code and
various multiply instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
4fb6fcd82d
ARM: Decode the scalar saturating add/subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
30dd622622
ARM: Decode the parallel add and subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
62e8487d57
ARM: Implement signed saturating add and/or subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
a1253ec644
ARM: Implemented prefetch instructions/decoding (pli, pld, pldw).
2010-06-02 12:58:05 -05:00
Gabe Black
61b00d3224
ARM: Decode unconditional ARM instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
b6e2f5d33f
ARM: Make sure ldm exception return writes back its base in the right mode.
...
This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.
2010-06-02 12:58:04 -05:00
Gabe Black
89060f1fd8
ARM: Rework how unrecognized/unimplemented instructions are handled.
...
Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
2010-06-02 12:58:04 -05:00
Gabe Black
aa45fafb2e
ARM: Add support for "SUBS PC, LR and related instructions".
2010-06-02 12:58:04 -05:00
Gabe Black
2419903dc0
ARM: Make ldrs into the PC and ldm exception return do interworking branches.
2010-06-02 12:58:04 -05:00
Gabe Black
28227440a7
ARM: Align the PC when using it as the base for a load.
2010-06-02 12:58:04 -05:00
Gabe Black
d63f748b53
ARM: Implement ADR as separate from ADD.
2010-06-02 12:58:04 -05:00
Gabe Black
e92dc21fde
ARM: Add support for interworking branch ALU instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
11c3361be4
ARM: Fix when the flag bits are updated for thumb.
2010-06-02 12:58:04 -05:00
Gabe Black
14d25fbad0
ARM: Don't rely on undefined behavior to get arithmetic right shift.
...
Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
2010-06-02 12:58:04 -05:00
Gabe Black
05d880f7a1
ARM: Restrict the shift amount from a register to 8 bits.
...
The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
2010-06-02 12:58:04 -05:00
Gabe Black
9ebaf8ecd5
ARM: Define the VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
3f83094af2
ARM: Decode the VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
647edea970
ARM: Fix the constant describing the number of floating point registers.
2010-06-02 12:58:04 -05:00
Gabe Black
2f3102f1ef
ARM: Add templates for VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
739f23c64c
ARM: Add base classes for VFP load/store multiple.
2010-06-02 12:58:04 -05:00
Gabe Black
cb631d87c3
ARM: Add floating point load/store microops.
2010-06-02 12:58:04 -05:00
Gabe Black
3a11412c99
ARM: Add an fp version of one of the microop indexed registers.
2010-06-02 12:58:04 -05:00
Gabe Black
d5aee75efe
ARM: Move the mmap region to where Linux actually has it.
2010-06-02 12:58:04 -05:00
Gabe Black
a8eb9d521c
ARM: Eliminate the unused rhi and rlo operands.
2010-06-02 12:58:03 -05:00
Gabe Black
b02c7f1bcd
ARM: Move the macro mem constructor out of the isa desc.
...
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
2010-06-02 12:58:03 -05:00
Gabe Black
7b62e9ad71
ARM: Make macroops panic if executed directly.
...
The macroop should never be executed, only it's microops will.
2010-06-02 12:58:03 -05:00
Ali Saidi
8fadf2691d
ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs.
2010-06-02 12:58:03 -05:00
Gabe Black
f18040a205
ARM: Split out the "basic" templates and format.
...
--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
2010-06-02 12:58:03 -05:00
Gabe Black
c175f1b993
ARM: Remove unnecessary cruft from includes.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
e29ec7d2ed
ARM: Move the inst2string function out of the isa_desc.
...
Delete the now empty formats/util.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
ae135228fc
ARM: Get rid of the unused ArmGenericCodeSubs.
2010-06-02 12:58:03 -05:00
Gabe Black
8c012e9571
ARM: Make the predecoder print out the ExtMachInst it gathered when traced.
2010-06-02 12:58:03 -05:00
Gabe Black
458bd025d4
ARM: Remove special naming for the new version of multiply.
2010-06-02 12:58:03 -05:00
Gabe Black
2196f75a25
ARM: Hook the new multiply instructions into all the decoders.
2010-06-02 12:58:03 -05:00
Gabe Black
33da368e99
ARM: Implement all integer multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
50229be27f
ARM: Add templates for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
3430b34cff
ARM: Add base classes for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
c7d2f43641
ARM: Decode plain binary immediate thumb data processing instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
dcf218155d
ARM: Define a new "movt" data processing instruction.
2010-06-02 12:58:03 -05:00
Gabe Black
b615ed1470
ARM: Hook the new branch instructions into the 32 bit thumb decoder.
2010-06-02 12:58:03 -05:00
Gabe Black
274badd201
ARM: Hook the new branch instructions into the 16 bit thumb decoder.
2010-06-02 12:58:03 -05:00
Gabe Black
b6b2f8891a
ARM: Eliminate the old style branch instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
d082705b01
ARM: Hook the new branch instructions into the ARM decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
9869343636
ARM: Implement branch instructions external to the decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
a6c1c8debb
ARM: Add new templates for branch instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
ef3972eaae
ARM: Implement new base classes for branches.
2010-06-02 12:58:02 -05:00
Gabe Black
769f3406fe
ARM: Replace the interworking branch base class with a special operand.
2010-06-02 12:58:02 -05:00
Gabe Black
b6e7029dd5
ARM: Fix PC operand handling.
2010-06-02 12:58:02 -05:00
