Commit graph

565 commits

Author SHA1 Message Date
Ali Saidi
9f15510c2c stats: update stats for previous changes. 2013-01-07 13:05:54 -05:00
Andreas Sandberg
5fb00e1df6 tests: Add CPU switching tests
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:

 * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
 * realview-switcheroo-atomic -- ARM system (atomic<->atomic)
 * realview-switcheroo-timing -- ARM system (timing<->timing)
 * realview-switcheroo-o3 -- ARM system (O3<->O3)
 * realview-switcheroo-full -- ARM system (atomic, timing, O3)

Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.

The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
2013-01-07 13:05:52 -05:00
Andreas Sandberg
e23850dd07 tests: Update the ignore regexps to reflect the M5->gem5 name change 2013-01-07 13:05:45 -05:00
Andreas Hansson
e65de3f5ca config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache
and I/O bridge such that they do not assume a single memory. The patch
involves adding a parameter to the system which is then defined based
on the memories that are to be visible from the I/O subsystem, whether
behind a cache or a bridge.

The change is needed to allow interleaved memory controllers in the
system.
2013-01-07 13:05:38 -05:00
Andreas Hansson
1da209140c cpu: Add support for protobuf input for the trace generator
This patch adds support for reading input traces encoded using
protobuf according to what is done in the CommMonitor.

A follow-up patch adds a Python script that can be used to convert the
previously used ASCII traces to protobuf equivalents. The appropriate
regression input is updated as part of this patch.
2013-01-07 13:05:37 -05:00
Andreas Sandberg
9c5ef235cc tests: Add support for skipping tests, skip EIO tests if not enabled
The EIO tests depend on the EIO support from the "encumbered"
repository, which means that they are not normally built with
gem5. This causes all EIO related tests to fail, which is both
annoying and confusing. This patch addresses this by adding support
for skipping tests if certain conditions (e.g., the presence of a
SimObject) can not be met. It introduces the following Python
functions that can be called from within a test case:

  * skip_test -- Skip a test and optionally print why the test was
                 skipped.

  * has_sim_object -- Test if a SimObject exists.

  * require_sim_object -- Test if a SimObject exists and skip, or
                          optionally fail, the test if not.

Additionally, this patch updates the EIO tests to check for the
presence of EioProcess.
2013-01-07 13:05:37 -05:00
Andreas Hansson
f456c7983d mem: Add tracing support in the communication monitor
This patch adds packet tracing to the communication monitor using a
protobuf as the mechanism for creating the trace.

If no file is specified, then the tracing is disabled. If a file is
specified, then for every packet that is successfully sent, a protobuf
message is serialized to the file.
2013-01-07 13:05:37 -05:00
Andreas Hansson
79b4477302 stats: Update DRAM regression stats to match new config
This patch updates the regression stats to reflect the change in the
traffic gen configuration.
2013-01-07 13:05:36 -05:00
Andreas Hansson
7216681561 config: Reduce DRAM controller regression traffic rate
This patch changes the traffic generator period such that it does not
completely saturate the DRAM controller and create an ever-growing
backlog in the queued port.

A separate patch updates the stats.
2013-01-07 13:05:36 -05:00
Andreas Sandberg
3db3f83a5e arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
2013-01-07 13:05:35 -05:00
Ali Saidi
90bd20aae2 tests: Always specify memory mode in every test system.
Previous to this change we didn't always set the memory mode which worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs verify
that they're operating in the correct mode and thus we need to always set it.
2013-01-07 13:05:33 -05:00
Andreas Sandberg
f32f372455 tests: Create base classes to encapsulate common test configurations
Most of the test cases currently contain a large amount of duplicated
boiler plate code. This changeset introduces a set of classes that
encapsulates most of the functionality when setting up a test
configuration.

The following base classes are introduced:
* BaseSystem - Basic system configuration that can be used for both
               SE and FS simulation.

* BaseFSSystem - Basic FS configuration uni-processor and multi-processor
                 configurations.

* BaseFSSystemUniprocessor - Basic FS configuration for uni-processor
                             configurations. This is provided as a way
			     to make existing test cases backwards
			     compatible.

Architecture specific implementations are provided for ARM, Alpha, and
X86.
2013-01-07 13:05:33 -05:00
Nilay Vaish
5ebe3210d8 regressions: stats update due to decoder changes 2013-01-04 19:00:48 -06:00
Nilay Vaish
1945f9963d x86 regressions: stats update due to new x87 instructions 2012-12-30 12:45:52 -06:00
Nilay Vaish
3b01edd7fa arm regressions: updates to config.ini, terminal files 2012-12-12 09:51:55 -06:00
Nilay Vaish
141ee38794 regressions: stats update due to stats from ruby prefetcher 2012-12-11 10:06:01 -06:00
Nilay Vaish
2fca1af71f regression test: update a couple of config.ini files 2012-12-06 10:26:12 -06:00
Nilay Vaish
2680c827be regressions: stats update due to ruby functional access patch 2012-11-10 17:18:02 -06:00
Ali Saidi
1dbf9bb4ca update stats for preceeding changes 2012-11-02 11:50:06 -05:00
Andreas Hansson
4e984e0962 stats: Update stats for fixed simple-atomic-mp config
This patch updates the stats for the regressions that were affected by
the typo in the simple-atomic-mp configuration.
2012-10-31 08:39:45 -04:00
Andreas Hansson
ab0bd51315 config: Fix a typo in the simple-atomic-mp configuration
This patch fixes a minor typo that managed to sneak into the
simple-atomic-mp regression configuration.
2012-10-31 08:39:43 -04:00
Andreas Hansson
10b70d5452 stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
2012-10-30 09:35:32 -04:00
Andreas Hansson
9cbe1cb653 config: Unify caches used in regressions and adjust L2 MSHRs
This patch unified the L1 and L2 caches used throughout the
regressions instead of declaring different, but very similar,
configurations in the different scripts.

The patch also changes the default L2 configuration to match what it
used to be for the fs and se scripts (until the last patch that
updated the regressions to also make use of the cache config). The
MSHRs and targets per MSHR are now set to a more realistic default of
20 and 12, respectively.

As a result of both the aforementioned changes, many of the regression
stats are changed. A follow-on patch will bump the stats.
2012-10-30 07:44:08 -04:00
Nilay Vaish
30f5bf5f23 regressions: update stats for ruby fs test 2012-10-27 16:05:06 -05:00
Andreas Hansson
651de2d9af config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
2012-10-26 06:42:42 -04:00
Andreas Hansson
b387d8e213 stats: Update the stats to reflect the 1GHz default system clock
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
2012-10-25 13:15:59 -04:00
Andreas Hansson
8fe556338d stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
2012-10-25 13:14:42 -04:00
Andreas Hansson
66e331c7bb config: Use SimpleDRAM in full-system, and with o3 and inorder
This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).

Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.

This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.
2012-10-25 13:14:38 -04:00
Andreas Hansson
d22796c03c config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.

The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.

As only regressions that shared the same cache configuration are
updated, no regressions are affected.
2012-10-25 04:32:44 -04:00
Andreas Hansson
a4329af937 stats: Update stats for DMA port send
This patch updates the stats after removing the zero-time send used in
the DMA port.
2012-10-23 04:49:48 -04:00
Andreas Hansson
37ded2c2cc stats: Update t1000 stats to match recent changes
This patch brings the t1000 stats up to date.
2012-10-23 04:24:32 -04:00
Nilay Vaish
de3b3ed140 regressions: update stats for eio tests 2012-10-16 14:47:31 -05:00
Nilay Vaish
b6b5cde132 regressions: update stats due to change to ruby memory system 2012-10-15 19:13:59 -05:00
Andreas Hansson
d52adc4eb6 Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
2012-10-15 08:12:21 -04:00
Andreas Hansson
88554790c3 Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.

The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.

As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.
2012-10-15 08:10:54 -04:00
Andreas Hansson
d17f5084ed Stats: Update memtest stats after setting clock
This patch updates the memtest stats to reflect the addition of a
clock other than the default one.
2012-10-15 08:10:52 -04:00
Andreas Hansson
072a91ee51 Configs: Set the memtest clock to a reasonable value
This patch changes the memtest clock from 1THz (the default) to 2GHz,
similar to the CPUs in the other regressions. This is useful as the
caches will adopt the same clock as the CPU. The bus clock rate is
scaled accordingly, and the L1-L2 bus is kept at the CPU clock while
the memory bus is at half that frequency.

A separate patch updates the affected stats.
2012-10-15 08:09:57 -04:00
Andreas Hansson
54227f9e57 Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
2012-10-15 08:09:54 -04:00
Andreas Hansson
a850fc916f Stats: Update stats for use of two-level builder
This patch updates the name of the l2 stats.
2012-10-15 08:08:06 -04:00
Andreas Hansson
3cf733bcc0 Regression: Use addTwoLevelCacheHierarchy in configs
This patch unifies the full-system regression config scripts and uses
the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up
the L1s and L2, and create the bus inbetween.

The patch is a step on the way to use the clock period to express the
cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2
bus, and these modules thus use the CPU clock.

The patch does not change the value of any stats, but plenty names,
and a follow-up patch contains the update to the stats, chaning
system.l2c to system.cpu.l2cache.
2012-10-15 08:07:09 -04:00
Nilay Vaish
0de0ce106a Regression Tests: Update statistics 2012-10-02 14:35:46 -05:00
Ali Saidi
91e74beee6 ARM: update stats for bp and squash fixes. 2012-09-25 11:49:41 -05:00
Mrinmoy Ghosh
6fc0094337 Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
2012-09-25 11:49:41 -05:00
Andreas Hansson
4f8ad7aa05 Stats: Update stats for twosys-tsunami after setting CPU clock
This patch updates the stats to reflect the addition of a clock
period other than the default 1 Tick.
2012-09-24 18:03:43 -04:00
Andreas Hansson
103a4a049c Regression: Set the clock for twosys-tsunami CPUs
This patch merely adds a clock other than the default 1 Tick for the
CPUs of both the test system and drive system for the twosys-tsunami
regression.

The CPU frequency of the driver system is choosed to be twice that of
the test system to ensure it is not the bottleneck (although in this
case it mostly serves as a demonstration of a two-system setup),
2012-09-24 18:03:41 -04:00
Andreas Hansson
6427342318 SimpleDRAM: A basic SimpleDRAM regression
--HG--
rename : tests/configs/tgen-simple-mem.py => tests/configs/tgen-simple-dram.py
rename : tests/quick/se/70.tgen/tgen-simple-mem.cfg => tests/quick/se/70.tgen/tgen-simple-dram.cfg
rename : tests/quick/se/70.tgen/tgen-simple-mem.trc => tests/quick/se/70.tgen/tgen-simple-dram.trc
2012-09-21 11:48:14 -04:00
Andreas Hansson
efea870fce TrafficGen: Add a basic traffic generator regression
This patch adds a basic regression for the traffic generator. The
regression also serves as an example of the file formats used. More
complex regressions that make use of a DRAM controller model will
follow shortly.
2012-09-21 11:48:11 -04:00
Andreas Hansson
d2b57a7473 Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
2012-09-18 10:30:04 -04:00
Andreas Hansson
ae1652b813 Stats: Remove the reference stats that are no longer present
This patch simply removes the commitCommittedInsts and
commitCommittedOps from the reference statistics, following their
removal from the CPU.
2012-09-13 08:02:55 -04:00
Nilay Vaish
fe5deb4a22 x86 Regressions: Update stats due to register predication 2012-09-11 09:34:40 -05:00