regressions: update stats for eio tests
This commit is contained in:
Nilay Vaish
parent
b6b5cde132
commit
de3b3ed140
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@ -1,14 +1,14 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000730 # Number of seconds simulated
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sim_ticks 729729000 # Number of ticks simulated
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final_tick 729729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 0.000727 # Number of seconds simulated
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sim_ticks 727072000 # Number of ticks simulated
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final_tick 727072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1176795 # Simulator instruction rate (inst/s)
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host_op_rate 1176746 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1717342738 # Simulator tick rate (ticks/s)
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host_mem_usage 221204 # Number of bytes of host memory used
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host_seconds 0.43 # Real time elapsed on the host
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host_inst_rate 1240024 # Simulator instruction rate (inst/s)
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host_op_rate 1239964 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1802997891 # Simulator tick rate (ticks/s)
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host_mem_usage 256648 # Number of bytes of host memory used
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host_seconds 0.40 # Real time elapsed on the host
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sim_insts 500001 # Number of instructions simulated
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sim_ops 500001 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory
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@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 25792 # Nu
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system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 857 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 35344628 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 39817521 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 75162149 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 35344628 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 35344628 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 35344628 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 39817521 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 75162149 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 35473791 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 39963030 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 75436821 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 35473791 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 35473791 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 35473791 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 39963030 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 75436821 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 18 # Number of system calls
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system.cpu.numCycles 1459458 # number of cpu cycles simulated
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system.cpu.numCycles 1454144 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 500001 # Number of instructions committed
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@ -79,18 +79,18 @@ system.cpu.num_mem_refs 180793 # nu
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system.cpu.num_load_insts 124443 # Number of load instructions
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system.cpu.num_store_insts 56350 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1459458 # Number of busy cycles
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system.cpu.num_busy_cycles 1454144 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 264.795716 # Cycle average of tags in use
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system.cpu.icache.tagsinuse 265.013024 # Cycle average of tags in use
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system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 264.795716 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.129295 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.129295 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::cpu.inst 265.013024 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.129401 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.129401 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 499617 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 499617 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 499617 # number of demand (read+write) hits
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@ -103,12 +103,12 @@ system.cpu.icache.demand_misses::cpu.inst 403 # n
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system.cpu.icache.demand_misses::total 403 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 403 # number of overall misses
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system.cpu.icache.overall_misses::total 403 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 22568000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 22568000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 22568000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 22568000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 22568000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 22568000 # number of overall miss cycles
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 22165000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 22165000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 22165000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 22165000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 22165000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 22165000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 500020 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 500020 # number of demand (read+write) accesses
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@ -121,12 +121,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000806
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system.cpu.icache.demand_miss_rate::total 0.000806 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.000806 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.000806 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 56000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 56000 # average overall miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
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system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 286.968386 # Cycle average of tags in use
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system.cpu.dcache.tagsinuse 287.259400 # Cycle average of tags in use
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system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 286.968386 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.070061 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.070061 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::cpu.data 287.259400 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.070132 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.070132 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits
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@ -185,14 +185,14 @@ system.cpu.dcache.demand_misses::cpu.data 454 # n
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system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses
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system.cpu.dcache.overall_misses::total 454 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 17640000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 17640000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 7784000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 7784000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 25424000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 25424000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 25424000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 25424000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 17325000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 17325000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 7645000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 7645000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 24970000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 24970000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 24970000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 24970000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses)
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@ -209,14 +209,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002511
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system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000
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system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 481.117902 # Cycle average of tags in use
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system.cpu.l2cache.tagsinuse 481.542013 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::cpu.inst 264.802343 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 216.315558 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.008081 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.006601 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.014683 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_blocks::cpu.inst 265.019675 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 216.522338 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::cpu.inst 0.008088 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.006608 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::total 0.014695 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_misses::cpu.inst 403 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::cpu.data 315 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_misses::total 718 # number of ReadReq misses
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