regressions: update stats due to change to ruby memory system
This commit is contained in:
Nilay Vaish
parent
5ffc165939
commit
b6b5cde132
18 changed files with 4300 additions and 4246 deletions
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,82 @@
|
|||
system.cpu6: completed 10000 read, 5365 write accesses @719672
|
||||
system.cpu4: completed 10000 read, 5437 write accesses @721238
|
||||
system.cpu2: completed 10000 read, 5421 write accesses @727405
|
||||
system.cpu5: completed 10000 read, 5337 write accesses @728640
|
||||
system.cpu1: completed 10000 read, 5306 write accesses @739695
|
||||
system.cpu0: completed 10000 read, 5242 write accesses @743577
|
||||
system.cpu3: completed 10000 read, 5450 write accesses @745629
|
||||
system.cpu7: completed 10000 read, 5714 write accesses @748519
|
||||
system.cpu6: completed 20000 read, 10620 write accesses @1427013
|
||||
system.cpu2: completed 20000 read, 10776 write accesses @1449780
|
||||
system.cpu4: completed 20000 read, 10676 write accesses @1454294
|
||||
system.cpu5: completed 20000 read, 10664 write accesses @1455327
|
||||
system.cpu1: completed 20000 read, 10677 write accesses @1463325
|
||||
system.cpu0: completed 20000 read, 10572 write accesses @1473996
|
||||
system.cpu7: completed 20000 read, 11108 write accesses @1487052
|
||||
system.cpu3: completed 20000 read, 10777 write accesses @1490754
|
||||
system.cpu5: completed 30000 read, 16039 write accesses @2158969
|
||||
system.cpu6: completed 30000 read, 16167 write accesses @2175252
|
||||
system.cpu2: completed 30000 read, 16167 write accesses @2180312
|
||||
system.cpu4: completed 30000 read, 16215 write accesses @2190381
|
||||
system.cpu0: completed 30000 read, 15974 write accesses @2206091
|
||||
system.cpu1: completed 30000 read, 16196 write accesses @2209395
|
||||
system.cpu7: completed 30000 read, 16345 write accesses @2219972
|
||||
system.cpu3: completed 30000 read, 16078 write accesses @2220143
|
||||
system.cpu5: completed 40000 read, 21392 write accesses @2899061
|
||||
system.cpu2: completed 40000 read, 21496 write accesses @2899829
|
||||
system.cpu6: completed 40000 read, 21553 write accesses @2911614
|
||||
system.cpu4: completed 40000 read, 21511 write accesses @2932562
|
||||
system.cpu1: completed 40000 read, 21671 write accesses @2938496
|
||||
system.cpu0: completed 40000 read, 21461 write accesses @2955945
|
||||
system.cpu3: completed 40000 read, 21481 write accesses @2956326
|
||||
system.cpu7: completed 40000 read, 21787 write accesses @2958263
|
||||
system.cpu2: completed 50000 read, 26881 write accesses @3632427
|
||||
system.cpu5: completed 50000 read, 26798 write accesses @3647589
|
||||
system.cpu6: completed 50000 read, 27058 write accesses @3655170
|
||||
system.cpu4: completed 50000 read, 26812 write accesses @3655319
|
||||
system.cpu1: completed 50000 read, 27071 write accesses @3688858
|
||||
system.cpu3: completed 50000 read, 26791 write accesses @3690833
|
||||
system.cpu0: completed 50000 read, 27081 write accesses @3690860
|
||||
system.cpu7: completed 50000 read, 27296 write accesses @3707477
|
||||
system.cpu2: completed 60000 read, 32129 write accesses @4356825
|
||||
system.cpu5: completed 60000 read, 32023 write accesses @4371741
|
||||
system.cpu6: completed 60000 read, 32443 write accesses @4376668
|
||||
system.cpu4: completed 60000 read, 32295 write accesses @4386108
|
||||
system.cpu3: completed 60000 read, 32175 write accesses @4408668
|
||||
system.cpu0: completed 60000 read, 32420 write accesses @4415861
|
||||
system.cpu1: completed 60000 read, 32486 write accesses @4431347
|
||||
system.cpu7: completed 60000 read, 32741 write accesses @4445010
|
||||
system.cpu2: completed 70000 read, 37617 write accesses @5091246
|
||||
system.cpu5: completed 70000 read, 37377 write accesses @5103537
|
||||
system.cpu4: completed 70000 read, 37661 write accesses @5110093
|
||||
system.cpu6: completed 70000 read, 37706 write accesses @5114409
|
||||
system.cpu3: completed 70000 read, 37523 write accesses @5122627
|
||||
system.cpu0: completed 70000 read, 37790 write accesses @5150115
|
||||
system.cpu7: completed 70000 read, 38053 write accesses @5173503
|
||||
system.cpu1: completed 70000 read, 37871 write accesses @5177041
|
||||
system.cpu2: completed 80000 read, 42964 write accesses @5827270
|
||||
system.cpu5: completed 80000 read, 42671 write accesses @5843646
|
||||
system.cpu4: completed 80000 read, 42873 write accesses @5844336
|
||||
system.cpu3: completed 80000 read, 42910 write accesses @5844576
|
||||
system.cpu6: completed 80000 read, 43090 write accesses @5845119
|
||||
system.cpu0: completed 80000 read, 43048 write accesses @5875184
|
||||
system.cpu1: completed 80000 read, 43196 write accesses @5885103
|
||||
system.cpu7: completed 80000 read, 43360 write accesses @5912912
|
||||
system.cpu2: completed 90000 read, 48230 write accesses @6556181
|
||||
system.cpu6: completed 90000 read, 48543 write accesses @6557564
|
||||
system.cpu4: completed 90000 read, 48345 write accesses @6563045
|
||||
system.cpu3: completed 90000 read, 48233 write accesses @6584230
|
||||
system.cpu5: completed 90000 read, 48065 write accesses @6589320
|
||||
system.cpu0: completed 90000 read, 48648 write accesses @6625439
|
||||
system.cpu1: completed 90000 read, 48656 write accesses @6633753
|
||||
system.cpu7: completed 90000 read, 48776 write accesses @6656500
|
||||
system.cpu2: completed 100000 read, 53615 write accesses @7277301
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu3: completed 10000 read, 5404 write accesses @717450
|
||||
system.cpu1: completed 10000 read, 5196 write accesses @724437
|
||||
system.cpu2: completed 10000 read, 5343 write accesses @725385
|
||||
system.cpu6: completed 10000 read, 5334 write accesses @727920
|
||||
system.cpu7: completed 10000 read, 5409 write accesses @729342
|
||||
system.cpu4: completed 10000 read, 5518 write accesses @734970
|
||||
system.cpu5: completed 10000 read, 5427 write accesses @742533
|
||||
system.cpu0: completed 10000 read, 5369 write accesses @745215
|
||||
system.cpu3: completed 20000 read, 10663 write accesses @1450297
|
||||
system.cpu1: completed 20000 read, 10544 write accesses @1453395
|
||||
system.cpu2: completed 20000 read, 10794 write accesses @1458916
|
||||
system.cpu4: completed 20000 read, 10867 write accesses @1467543
|
||||
system.cpu7: completed 20000 read, 11024 write accesses @1468498
|
||||
system.cpu5: completed 20000 read, 10707 write accesses @1475684
|
||||
system.cpu6: completed 20000 read, 10882 write accesses @1478874
|
||||
system.cpu0: completed 20000 read, 10682 write accesses @1482396
|
||||
system.cpu2: completed 30000 read, 16135 write accesses @2180653
|
||||
system.cpu6: completed 30000 read, 16248 write accesses @2190702
|
||||
system.cpu0: completed 30000 read, 15981 write accesses @2193064
|
||||
system.cpu7: completed 30000 read, 16551 write accesses @2194713
|
||||
system.cpu1: completed 30000 read, 16114 write accesses @2197452
|
||||
system.cpu4: completed 30000 read, 16285 write accesses @2201477
|
||||
system.cpu3: completed 30000 read, 16078 write accesses @2211153
|
||||
system.cpu5: completed 30000 read, 15971 write accesses @2223483
|
||||
system.cpu6: completed 40000 read, 21540 write accesses @2894242
|
||||
system.cpu2: completed 40000 read, 21379 write accesses @2909918
|
||||
system.cpu0: completed 40000 read, 21281 write accesses @2925069
|
||||
system.cpu7: completed 40000 read, 21971 write accesses @2926047
|
||||
system.cpu1: completed 40000 read, 21533 write accesses @2926905
|
||||
system.cpu4: completed 40000 read, 21566 write accesses @2928243
|
||||
system.cpu3: completed 40000 read, 21457 write accesses @2944482
|
||||
system.cpu5: completed 40000 read, 21433 write accesses @2971421
|
||||
system.cpu6: completed 50000 read, 26804 write accesses @3631185
|
||||
system.cpu2: completed 50000 read, 26805 write accesses @3647917
|
||||
system.cpu1: completed 50000 read, 26966 write accesses @3648934
|
||||
system.cpu0: completed 50000 read, 26609 write accesses @3651975
|
||||
system.cpu4: completed 50000 read, 26920 write accesses @3663191
|
||||
system.cpu7: completed 50000 read, 27389 write accesses @3665118
|
||||
system.cpu3: completed 50000 read, 26923 write accesses @3682505
|
||||
system.cpu5: completed 50000 read, 26907 write accesses @3699503
|
||||
system.cpu6: completed 60000 read, 31950 write accesses @4347584
|
||||
system.cpu0: completed 60000 read, 31929 write accesses @4376408
|
||||
system.cpu4: completed 60000 read, 32384 write accesses @4384804
|
||||
system.cpu1: completed 60000 read, 32291 write accesses @4390260
|
||||
system.cpu2: completed 60000 read, 32255 write accesses @4393199
|
||||
system.cpu7: completed 60000 read, 32753 write accesses @4398494
|
||||
system.cpu3: completed 60000 read, 32296 write accesses @4430205
|
||||
system.cpu5: completed 60000 read, 32304 write accesses @4433476
|
||||
system.cpu6: completed 70000 read, 37197 write accesses @5062593
|
||||
system.cpu0: completed 70000 read, 37408 write accesses @5107223
|
||||
system.cpu4: completed 70000 read, 37809 write accesses @5113784
|
||||
system.cpu7: completed 70000 read, 38017 write accesses @5123354
|
||||
system.cpu1: completed 70000 read, 37773 write accesses @5127282
|
||||
system.cpu2: completed 70000 read, 37716 write accesses @5127504
|
||||
system.cpu5: completed 70000 read, 37617 write accesses @5160933
|
||||
system.cpu3: completed 70000 read, 37758 write accesses @5167879
|
||||
system.cpu6: completed 80000 read, 42553 write accesses @5789514
|
||||
system.cpu7: completed 80000 read, 43160 write accesses @5844814
|
||||
system.cpu4: completed 80000 read, 43182 write accesses @5848125
|
||||
system.cpu0: completed 80000 read, 43046 write accesses @5851383
|
||||
system.cpu2: completed 80000 read, 42995 write accesses @5852199
|
||||
system.cpu1: completed 80000 read, 43208 write accesses @5860776
|
||||
system.cpu5: completed 80000 read, 43003 write accesses @5898048
|
||||
system.cpu3: completed 80000 read, 43420 write accesses @5900131
|
||||
system.cpu6: completed 90000 read, 47840 write accesses @6504240
|
||||
system.cpu7: completed 90000 read, 48495 write accesses @6570600
|
||||
system.cpu2: completed 90000 read, 48384 write accesses @6574765
|
||||
system.cpu0: completed 90000 read, 48489 write accesses @6585072
|
||||
system.cpu4: completed 90000 read, 48555 write accesses @6585987
|
||||
system.cpu1: completed 90000 read, 48451 write accesses @6586255
|
||||
system.cpu5: completed 90000 read, 48304 write accesses @6624686
|
||||
system.cpu3: completed 90000 read, 48748 write accesses @6638587
|
||||
system.cpu6: completed 100000 read, 53283 write accesses @7241726
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.007277 # Number of seconds simulated
|
||||
sim_ticks 7277301 # Number of ticks simulated
|
||||
final_tick 7277301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.007242 # Number of seconds simulated
|
||||
sim_ticks 7241726 # Number of ticks simulated
|
||||
final_tick 7241726 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 75137 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410244 # Number of bytes of host memory used
|
||||
host_seconds 96.85 # Real time elapsed on the host
|
||||
host_tick_rate 40867 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418748 # Number of bytes of host memory used
|
||||
host_seconds 177.20 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 98746 # number of read accesses completed
|
||||
system.cpu0.num_writes 53285 # number of write accesses completed
|
||||
system.cpu0.num_reads 99032 # number of read accesses completed
|
||||
system.cpu0.num_writes 53300 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98932 # number of read accesses completed
|
||||
system.cpu1.num_writes 53387 # number of write accesses completed
|
||||
system.cpu1.num_reads 99071 # number of read accesses completed
|
||||
system.cpu1.num_writes 53375 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 100001 # number of read accesses completed
|
||||
system.cpu2.num_writes 53615 # number of write accesses completed
|
||||
system.cpu2.num_reads 99029 # number of read accesses completed
|
||||
system.cpu2.num_writes 53317 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99438 # number of read accesses completed
|
||||
system.cpu3.num_writes 53391 # number of write accesses completed
|
||||
system.cpu3.num_reads 98175 # number of read accesses completed
|
||||
system.cpu3.num_writes 53115 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99851 # number of read accesses completed
|
||||
system.cpu4.num_writes 53668 # number of write accesses completed
|
||||
system.cpu4.num_reads 98923 # number of read accesses completed
|
||||
system.cpu4.num_writes 53385 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99263 # number of read accesses completed
|
||||
system.cpu5.num_writes 53077 # number of write accesses completed
|
||||
system.cpu5.num_reads 98363 # number of read accesses completed
|
||||
system.cpu5.num_writes 52848 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99775 # number of read accesses completed
|
||||
system.cpu6.num_writes 53756 # number of write accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 53283 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 98608 # number of read accesses completed
|
||||
system.cpu7.num_writes 53419 # number of write accesses completed
|
||||
system.cpu7.num_reads 99065 # number of read accesses completed
|
||||
system.cpu7.num_writes 53415 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,82 @@
|
|||
system.cpu4: completed 10000 read, 5361 write accesses @736700
|
||||
system.cpu2: completed 10000 read, 5258 write accesses @741379
|
||||
system.cpu3: completed 10000 read, 5403 write accesses @747863
|
||||
system.cpu1: completed 10000 read, 5292 write accesses @751357
|
||||
system.cpu6: completed 10000 read, 5451 write accesses @754502
|
||||
system.cpu7: completed 10000 read, 5438 write accesses @755068
|
||||
system.cpu5: completed 10000 read, 5557 write accesses @759525
|
||||
system.cpu0: completed 10000 read, 5442 write accesses @772965
|
||||
system.cpu4: completed 20000 read, 10700 write accesses @1474707
|
||||
system.cpu7: completed 20000 read, 10673 write accesses @1490391
|
||||
system.cpu2: completed 20000 read, 10490 write accesses @1492637
|
||||
system.cpu3: completed 20000 read, 10828 write accesses @1496240
|
||||
system.cpu1: completed 20000 read, 10531 write accesses @1496747
|
||||
system.cpu6: completed 20000 read, 10827 write accesses @1502187
|
||||
system.cpu5: completed 20000 read, 10968 write accesses @1509184
|
||||
system.cpu0: completed 20000 read, 10821 write accesses @1515170
|
||||
system.cpu4: completed 30000 read, 16140 write accesses @2234178
|
||||
system.cpu2: completed 30000 read, 15837 write accesses @2240133
|
||||
system.cpu1: completed 30000 read, 15925 write accesses @2244203
|
||||
system.cpu6: completed 30000 read, 16178 write accesses @2245026
|
||||
system.cpu0: completed 30000 read, 16116 write accesses @2252500
|
||||
system.cpu7: completed 30000 read, 16150 write accesses @2252680
|
||||
system.cpu5: completed 30000 read, 16546 write accesses @2254097
|
||||
system.cpu3: completed 30000 read, 16154 write accesses @2258292
|
||||
system.cpu2: completed 40000 read, 21131 write accesses @2982888
|
||||
system.cpu4: completed 40000 read, 21564 write accesses @2988433
|
||||
system.cpu6: completed 40000 read, 21517 write accesses @2995571
|
||||
system.cpu7: completed 40000 read, 21451 write accesses @3002984
|
||||
system.cpu0: completed 40000 read, 21558 write accesses @3005254
|
||||
system.cpu1: completed 40000 read, 21476 write accesses @3010475
|
||||
system.cpu3: completed 40000 read, 21590 write accesses @3015598
|
||||
system.cpu5: completed 40000 read, 21951 write accesses @3024338
|
||||
system.cpu2: completed 50000 read, 26563 write accesses @3740176
|
||||
system.cpu4: completed 50000 read, 27047 write accesses @3743329
|
||||
system.cpu7: completed 50000 read, 26749 write accesses @3757917
|
||||
system.cpu6: completed 50000 read, 26964 write accesses @3758280
|
||||
system.cpu0: completed 50000 read, 27012 write accesses @3762857
|
||||
system.cpu5: completed 50000 read, 27348 write accesses @3768681
|
||||
system.cpu1: completed 50000 read, 26902 write accesses @3773494
|
||||
system.cpu3: completed 50000 read, 27102 write accesses @3774586
|
||||
system.cpu2: completed 60000 read, 32068 write accesses @4487250
|
||||
system.cpu4: completed 60000 read, 32524 write accesses @4492613
|
||||
system.cpu7: completed 60000 read, 32123 write accesses @4501802
|
||||
system.cpu5: completed 60000 read, 32618 write accesses @4505087
|
||||
system.cpu6: completed 60000 read, 32304 write accesses @4507148
|
||||
system.cpu1: completed 60000 read, 32342 write accesses @4512477
|
||||
system.cpu0: completed 60000 read, 32196 write accesses @4513791
|
||||
system.cpu3: completed 60000 read, 32477 write accesses @4527938
|
||||
system.cpu4: completed 70000 read, 38050 write accesses @5246087
|
||||
system.cpu2: completed 70000 read, 37438 write accesses @5246857
|
||||
system.cpu6: completed 70000 read, 37522 write accesses @5247624
|
||||
system.cpu1: completed 70000 read, 37552 write accesses @5255630
|
||||
system.cpu7: completed 70000 read, 37454 write accesses @5256746
|
||||
system.cpu5: completed 70000 read, 37853 write accesses @5262449
|
||||
system.cpu3: completed 70000 read, 37751 write accesses @5263226
|
||||
system.cpu0: completed 70000 read, 37564 write accesses @5268794
|
||||
system.cpu6: completed 80000 read, 42984 write accesses @5994771
|
||||
system.cpu4: completed 80000 read, 43493 write accesses @5995916
|
||||
system.cpu5: completed 80000 read, 42965 write accesses @6000829
|
||||
system.cpu2: completed 80000 read, 42825 write accesses @6004649
|
||||
system.cpu0: completed 80000 read, 42741 write accesses @6006103
|
||||
system.cpu1: completed 80000 read, 42738 write accesses @6009758
|
||||
system.cpu7: completed 80000 read, 42872 write accesses @6009923
|
||||
system.cpu3: completed 80000 read, 43090 write accesses @6011644
|
||||
system.cpu6: completed 90000 read, 48315 write accesses @6743220
|
||||
system.cpu4: completed 90000 read, 48816 write accesses @6743546
|
||||
system.cpu1: completed 90000 read, 48145 write accesses @6749147
|
||||
system.cpu2: completed 90000 read, 48237 write accesses @6753252
|
||||
system.cpu5: completed 90000 read, 48465 write accesses @6756537
|
||||
system.cpu3: completed 90000 read, 48531 write accesses @6772036
|
||||
system.cpu0: completed 90000 read, 48152 write accesses @6774043
|
||||
system.cpu7: completed 90000 read, 48393 write accesses @6775135
|
||||
system.cpu4: completed 100000 read, 54127 write accesses @7493512
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu4: completed 10000 read, 5367 write accesses @734529
|
||||
system.cpu2: completed 10000 read, 5411 write accesses @739034
|
||||
system.cpu3: completed 10000 read, 5397 write accesses @741278
|
||||
system.cpu6: completed 10000 read, 5401 write accesses @742830
|
||||
system.cpu1: completed 10000 read, 5459 write accesses @745510
|
||||
system.cpu7: completed 10000 read, 5449 write accesses @745578
|
||||
system.cpu5: completed 10000 read, 5460 write accesses @752999
|
||||
system.cpu0: completed 10000 read, 5374 write accesses @754640
|
||||
system.cpu4: completed 20000 read, 10811 write accesses @1483097
|
||||
system.cpu6: completed 20000 read, 10717 write accesses @1490444
|
||||
system.cpu3: completed 20000 read, 10857 write accesses @1492719
|
||||
system.cpu2: completed 20000 read, 10867 write accesses @1494524
|
||||
system.cpu5: completed 20000 read, 10900 write accesses @1496108
|
||||
system.cpu1: completed 20000 read, 10872 write accesses @1496903
|
||||
system.cpu0: completed 20000 read, 10931 write accesses @1504162
|
||||
system.cpu7: completed 20000 read, 11167 write accesses @1514664
|
||||
system.cpu4: completed 30000 read, 16318 write accesses @2226152
|
||||
system.cpu6: completed 30000 read, 16244 write accesses @2235778
|
||||
system.cpu1: completed 30000 read, 16305 write accesses @2241693
|
||||
system.cpu3: completed 30000 read, 16231 write accesses @2243127
|
||||
system.cpu5: completed 30000 read, 16446 write accesses @2247293
|
||||
system.cpu2: completed 30000 read, 16424 write accesses @2250994
|
||||
system.cpu0: completed 30000 read, 16501 write accesses @2260704
|
||||
system.cpu7: completed 30000 read, 16627 write accesses @2268008
|
||||
system.cpu4: completed 40000 read, 21749 write accesses @2962709
|
||||
system.cpu1: completed 40000 read, 21593 write accesses @2979076
|
||||
system.cpu6: completed 40000 read, 21829 write accesses @2993869
|
||||
system.cpu3: completed 40000 read, 21830 write accesses @2994935
|
||||
system.cpu0: completed 40000 read, 21924 write accesses @3006797
|
||||
system.cpu5: completed 40000 read, 22012 write accesses @3007541
|
||||
system.cpu2: completed 40000 read, 21921 write accesses @3009943
|
||||
system.cpu7: completed 40000 read, 22003 write accesses @3016612
|
||||
system.cpu1: completed 50000 read, 26824 write accesses @3710601
|
||||
system.cpu4: completed 50000 read, 27284 write accesses @3716733
|
||||
system.cpu5: completed 50000 read, 27307 write accesses @3743758
|
||||
system.cpu6: completed 50000 read, 27337 write accesses @3752012
|
||||
system.cpu2: completed 50000 read, 27397 write accesses @3754564
|
||||
system.cpu0: completed 50000 read, 27281 write accesses @3754969
|
||||
system.cpu7: completed 50000 read, 27533 write accesses @3759171
|
||||
system.cpu3: completed 50000 read, 27422 write accesses @3773312
|
||||
system.cpu1: completed 60000 read, 32296 write accesses @4453312
|
||||
system.cpu4: completed 60000 read, 32758 write accesses @4481325
|
||||
system.cpu5: completed 60000 read, 32870 write accesses @4492024
|
||||
system.cpu6: completed 60000 read, 32717 write accesses @4494308
|
||||
system.cpu2: completed 60000 read, 32692 write accesses @4496082
|
||||
system.cpu0: completed 60000 read, 32771 write accesses @4507003
|
||||
system.cpu3: completed 60000 read, 32841 write accesses @4507635
|
||||
system.cpu7: completed 60000 read, 32948 write accesses @4509464
|
||||
system.cpu1: completed 70000 read, 37680 write accesses @5196500
|
||||
system.cpu4: completed 70000 read, 38348 write accesses @5238038
|
||||
system.cpu6: completed 70000 read, 38163 write accesses @5248200
|
||||
system.cpu0: completed 70000 read, 38097 write accesses @5249364
|
||||
system.cpu2: completed 70000 read, 38107 write accesses @5253167
|
||||
system.cpu5: completed 70000 read, 38242 write accesses @5256208
|
||||
system.cpu3: completed 70000 read, 38223 write accesses @5263274
|
||||
system.cpu7: completed 70000 read, 38358 write accesses @5264096
|
||||
system.cpu1: completed 80000 read, 43090 write accesses @5938080
|
||||
system.cpu4: completed 80000 read, 43794 write accesses @5986228
|
||||
system.cpu2: completed 80000 read, 43534 write accesses @5995018
|
||||
system.cpu6: completed 80000 read, 43480 write accesses @5996319
|
||||
system.cpu0: completed 80000 read, 43647 write accesses @6010543
|
||||
system.cpu3: completed 80000 read, 43541 write accesses @6012821
|
||||
system.cpu5: completed 80000 read, 43618 write accesses @6013478
|
||||
system.cpu7: completed 80000 read, 43801 write accesses @6025753
|
||||
system.cpu1: completed 90000 read, 48545 write accesses @6687745
|
||||
system.cpu4: completed 90000 read, 49359 write accesses @6726890
|
||||
system.cpu5: completed 90000 read, 48916 write accesses @6741464
|
||||
system.cpu6: completed 90000 read, 49052 write accesses @6749326
|
||||
system.cpu0: completed 90000 read, 49060 write accesses @6762829
|
||||
system.cpu2: completed 90000 read, 49003 write accesses @6764022
|
||||
system.cpu3: completed 90000 read, 48925 write accesses @6765195
|
||||
system.cpu7: completed 90000 read, 49330 write accesses @6780434
|
||||
system.cpu1: completed 100000 read, 54091 write accesses @7447945
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.007494 # Number of seconds simulated
|
||||
sim_ticks 7493512 # Number of ticks simulated
|
||||
final_tick 7493512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.007448 # Number of seconds simulated
|
||||
sim_ticks 7447945 # Number of ticks simulated
|
||||
final_tick 7447945 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 42711 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410448 # Number of bytes of host memory used
|
||||
host_seconds 175.45 # Real time elapsed on the host
|
||||
host_tick_rate 25433 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418956 # Number of bytes of host memory used
|
||||
host_seconds 292.84 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99629 # number of read accesses completed
|
||||
system.cpu0.num_writes 53203 # number of write accesses completed
|
||||
system.cpu0.num_reads 99070 # number of read accesses completed
|
||||
system.cpu0.num_writes 53923 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99934 # number of read accesses completed
|
||||
system.cpu1.num_writes 53556 # number of write accesses completed
|
||||
system.cpu1.num_reads 100000 # number of read accesses completed
|
||||
system.cpu1.num_writes 54091 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99904 # number of read accesses completed
|
||||
system.cpu2.num_writes 53683 # number of write accesses completed
|
||||
system.cpu2.num_reads 99298 # number of read accesses completed
|
||||
system.cpu2.num_writes 53915 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99658 # number of read accesses completed
|
||||
system.cpu3.num_writes 53732 # number of write accesses completed
|
||||
system.cpu3.num_reads 99379 # number of read accesses completed
|
||||
system.cpu3.num_writes 53826 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 54127 # number of write accesses completed
|
||||
system.cpu4.num_reads 99471 # number of read accesses completed
|
||||
system.cpu4.num_writes 54600 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99924 # number of read accesses completed
|
||||
system.cpu5.num_writes 53749 # number of write accesses completed
|
||||
system.cpu5.num_reads 99375 # number of read accesses completed
|
||||
system.cpu5.num_writes 54088 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99831 # number of read accesses completed
|
||||
system.cpu6.num_writes 53726 # number of write accesses completed
|
||||
system.cpu6.num_reads 99102 # number of read accesses completed
|
||||
system.cpu6.num_writes 54167 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99585 # number of read accesses completed
|
||||
system.cpu7.num_writes 53460 # number of write accesses completed
|
||||
system.cpu7.num_reads 98852 # number of read accesses completed
|
||||
system.cpu7.num_writes 54147 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,82 @@
|
|||
system.cpu4: completed 10000 read, 5358 write accesses @1929263
|
||||
system.cpu0: completed 10000 read, 5517 write accesses @1938193
|
||||
system.cpu6: completed 10000 read, 5282 write accesses @1960370
|
||||
system.cpu2: completed 10000 read, 5370 write accesses @1983069
|
||||
system.cpu3: completed 10000 read, 5219 write accesses @1986540
|
||||
system.cpu5: completed 10000 read, 5534 write accesses @2010490
|
||||
system.cpu1: completed 10000 read, 5481 write accesses @2016799
|
||||
system.cpu7: completed 10000 read, 5483 write accesses @2027000
|
||||
system.cpu0: completed 20000 read, 10906 write accesses @3889460
|
||||
system.cpu6: completed 20000 read, 10539 write accesses @3890430
|
||||
system.cpu4: completed 20000 read, 10737 write accesses @3908329
|
||||
system.cpu2: completed 20000 read, 10719 write accesses @3939180
|
||||
system.cpu3: completed 20000 read, 10494 write accesses @3943600
|
||||
system.cpu5: completed 20000 read, 10848 write accesses @3948219
|
||||
system.cpu1: completed 20000 read, 10769 write accesses @4005719
|
||||
system.cpu7: completed 20000 read, 10891 write accesses @4012914
|
||||
system.cpu6: completed 30000 read, 15919 write accesses @5839330
|
||||
system.cpu4: completed 30000 read, 15999 write accesses @5874900
|
||||
system.cpu0: completed 30000 read, 16423 write accesses @5898830
|
||||
system.cpu5: completed 30000 read, 16404 write accesses @5936061
|
||||
system.cpu1: completed 30000 read, 16153 write accesses @5948410
|
||||
system.cpu7: completed 30000 read, 16256 write accesses @5950050
|
||||
system.cpu2: completed 30000 read, 16157 write accesses @5958790
|
||||
system.cpu3: completed 30000 read, 15885 write accesses @5959680
|
||||
system.cpu4: completed 40000 read, 21342 write accesses @7808600
|
||||
system.cpu6: completed 40000 read, 21196 write accesses @7836451
|
||||
system.cpu0: completed 40000 read, 21854 write accesses @7880130
|
||||
system.cpu1: completed 40000 read, 21631 write accesses @7920239
|
||||
system.cpu7: completed 40000 read, 21703 write accesses @7933959
|
||||
system.cpu5: completed 40000 read, 21772 write accesses @7955069
|
||||
system.cpu3: completed 40000 read, 21372 write accesses @7959100
|
||||
system.cpu2: completed 40000 read, 21557 write accesses @7981970
|
||||
system.cpu6: completed 50000 read, 26595 write accesses @9809169
|
||||
system.cpu4: completed 50000 read, 26864 write accesses @9817559
|
||||
system.cpu7: completed 50000 read, 27042 write accesses @9902500
|
||||
system.cpu0: completed 50000 read, 27271 write accesses @9906269
|
||||
system.cpu1: completed 50000 read, 27124 write accesses @9934930
|
||||
system.cpu3: completed 50000 read, 26755 write accesses @9946640
|
||||
system.cpu5: completed 50000 read, 27198 write accesses @9946679
|
||||
system.cpu2: completed 50000 read, 27060 write accesses @9974740
|
||||
system.cpu6: completed 60000 read, 32039 write accesses @11769919
|
||||
system.cpu4: completed 60000 read, 32173 write accesses @11822509
|
||||
system.cpu1: completed 60000 read, 32379 write accesses @11844429
|
||||
system.cpu0: completed 60000 read, 32699 write accesses @11852900
|
||||
system.cpu7: completed 60000 read, 32457 write accesses @11873181
|
||||
system.cpu5: completed 60000 read, 32557 write accesses @11887270
|
||||
system.cpu3: completed 60000 read, 32167 write accesses @11912630
|
||||
system.cpu2: completed 60000 read, 32437 write accesses @11967610
|
||||
system.cpu4: completed 70000 read, 37476 write accesses @13774590
|
||||
system.cpu1: completed 70000 read, 37764 write accesses @13776500
|
||||
system.cpu6: completed 70000 read, 37423 write accesses @13811110
|
||||
system.cpu0: completed 70000 read, 38112 write accesses @13822360
|
||||
system.cpu7: completed 70000 read, 37768 write accesses @13852100
|
||||
system.cpu3: completed 70000 read, 37356 write accesses @13890992
|
||||
system.cpu5: completed 70000 read, 38000 write accesses @13891330
|
||||
system.cpu2: completed 70000 read, 37653 write accesses @13903529
|
||||
system.cpu4: completed 80000 read, 42652 write accesses @15714260
|
||||
system.cpu1: completed 80000 read, 43161 write accesses @15743660
|
||||
system.cpu0: completed 80000 read, 43377 write accesses @15747360
|
||||
system.cpu6: completed 80000 read, 42650 write accesses @15761321
|
||||
system.cpu7: completed 80000 read, 43147 write accesses @15846829
|
||||
system.cpu2: completed 80000 read, 42984 write accesses @15878720
|
||||
system.cpu3: completed 80000 read, 42913 write accesses @15881610
|
||||
system.cpu5: completed 80000 read, 43333 write accesses @15910140
|
||||
system.cpu4: completed 90000 read, 48050 write accesses @17730480
|
||||
system.cpu1: completed 90000 read, 48527 write accesses @17731920
|
||||
system.cpu0: completed 90000 read, 48688 write accesses @17739870
|
||||
system.cpu6: completed 90000 read, 48114 write accesses @17751610
|
||||
system.cpu7: completed 90000 read, 48607 write accesses @17816041
|
||||
system.cpu2: completed 90000 read, 48386 write accesses @17847760
|
||||
system.cpu3: completed 90000 read, 48361 write accesses @17860389
|
||||
system.cpu5: completed 90000 read, 48782 write accesses @17871890
|
||||
system.cpu4: completed 100000 read, 53373 write accesses @19665440
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu3: completed 10000 read, 5335 write accesses @606797
|
||||
system.cpu5: completed 10000 read, 5331 write accesses @607565
|
||||
system.cpu4: completed 10000 read, 5526 write accesses @608260
|
||||
system.cpu2: completed 10000 read, 5318 write accesses @614261
|
||||
system.cpu1: completed 10000 read, 5400 write accesses @614387
|
||||
system.cpu7: completed 10000 read, 5362 write accesses @615713
|
||||
system.cpu6: completed 10000 read, 5564 write accesses @615733
|
||||
system.cpu0: completed 10000 read, 5551 write accesses @616304
|
||||
system.cpu5: completed 20000 read, 10723 write accesses @1217974
|
||||
system.cpu0: completed 20000 read, 11047 write accesses @1228624
|
||||
system.cpu4: completed 20000 read, 10902 write accesses @1228676
|
||||
system.cpu1: completed 20000 read, 10777 write accesses @1228883
|
||||
system.cpu7: completed 20000 read, 10727 write accesses @1230451
|
||||
system.cpu3: completed 20000 read, 10656 write accesses @1231448
|
||||
system.cpu2: completed 20000 read, 10657 write accesses @1236334
|
||||
system.cpu6: completed 20000 read, 11082 write accesses @1236758
|
||||
system.cpu5: completed 30000 read, 15988 write accesses @1827079
|
||||
system.cpu1: completed 30000 read, 16124 write accesses @1833167
|
||||
system.cpu3: completed 30000 read, 15943 write accesses @1835575
|
||||
system.cpu6: completed 30000 read, 16327 write accesses @1840325
|
||||
system.cpu0: completed 30000 read, 16411 write accesses @1845820
|
||||
system.cpu7: completed 30000 read, 16138 write accesses @1851244
|
||||
system.cpu2: completed 30000 read, 16138 write accesses @1863740
|
||||
system.cpu4: completed 30000 read, 16319 write accesses @1864484
|
||||
system.cpu5: completed 40000 read, 21536 write accesses @2432906
|
||||
system.cpu1: completed 40000 read, 21516 write accesses @2445656
|
||||
system.cpu0: completed 40000 read, 21751 write accesses @2457852
|
||||
system.cpu3: completed 40000 read, 21310 write accesses @2457970
|
||||
system.cpu7: completed 40000 read, 21388 write accesses @2458337
|
||||
system.cpu6: completed 40000 read, 21741 write accesses @2459051
|
||||
system.cpu4: completed 40000 read, 21462 write accesses @2473826
|
||||
system.cpu2: completed 40000 read, 21429 write accesses @2476553
|
||||
system.cpu5: completed 50000 read, 27059 write accesses @3049178
|
||||
system.cpu7: completed 50000 read, 26653 write accesses @3064589
|
||||
system.cpu1: completed 50000 read, 26847 write accesses @3066332
|
||||
system.cpu3: completed 50000 read, 26520 write accesses @3067661
|
||||
system.cpu6: completed 50000 read, 27151 write accesses @3069278
|
||||
system.cpu4: completed 50000 read, 26852 write accesses @3080753
|
||||
system.cpu0: completed 50000 read, 27078 write accesses @3081059
|
||||
system.cpu2: completed 50000 read, 26858 write accesses @3093584
|
||||
system.cpu5: completed 60000 read, 32391 write accesses @3656779
|
||||
system.cpu1: completed 60000 read, 32290 write accesses @3669694
|
||||
system.cpu3: completed 60000 read, 31832 write accesses @3679631
|
||||
system.cpu0: completed 60000 read, 32411 write accesses @3682976
|
||||
system.cpu7: completed 60000 read, 31852 write accesses @3683261
|
||||
system.cpu6: completed 60000 read, 32690 write accesses @3693796
|
||||
system.cpu2: completed 60000 read, 32174 write accesses @3694259
|
||||
system.cpu4: completed 60000 read, 32211 write accesses @3697154
|
||||
system.cpu1: completed 70000 read, 37707 write accesses @4274498
|
||||
system.cpu3: completed 70000 read, 37255 write accesses @4279718
|
||||
system.cpu5: completed 70000 read, 37867 write accesses @4283684
|
||||
system.cpu0: completed 70000 read, 37805 write accesses @4287731
|
||||
system.cpu7: completed 70000 read, 37138 write accesses @4296794
|
||||
system.cpu2: completed 70000 read, 37605 write accesses @4304710
|
||||
system.cpu6: completed 70000 read, 38072 write accesses @4311342
|
||||
system.cpu4: completed 70000 read, 37624 write accesses @4316870
|
||||
system.cpu3: completed 80000 read, 42498 write accesses @4877336
|
||||
system.cpu0: completed 80000 read, 43132 write accesses @4889693
|
||||
system.cpu1: completed 80000 read, 43168 write accesses @4896265
|
||||
system.cpu5: completed 80000 read, 43273 write accesses @4899143
|
||||
system.cpu7: completed 80000 read, 42494 write accesses @4912991
|
||||
system.cpu2: completed 80000 read, 43018 write accesses @4921903
|
||||
system.cpu6: completed 80000 read, 43483 write accesses @4928537
|
||||
system.cpu4: completed 80000 read, 42951 write accesses @4931114
|
||||
system.cpu3: completed 90000 read, 47893 write accesses @5493844
|
||||
system.cpu1: completed 90000 read, 48591 write accesses @5495944
|
||||
system.cpu0: completed 90000 read, 48484 write accesses @5503496
|
||||
system.cpu5: completed 90000 read, 48798 write accesses @5509616
|
||||
system.cpu2: completed 90000 read, 48092 write accesses @5514734
|
||||
system.cpu7: completed 90000 read, 47926 write accesses @5524841
|
||||
system.cpu4: completed 90000 read, 48357 write accesses @5550818
|
||||
system.cpu6: completed 90000 read, 48791 write accesses @5555216
|
||||
system.cpu3: completed 100000 read, 53266 write accesses @6111458
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.006104 # Number of seconds simulated
|
||||
sim_ticks 6103915 # Number of ticks simulated
|
||||
final_tick 6103915 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.006111 # Number of seconds simulated
|
||||
sim_ticks 6111458 # Number of ticks simulated
|
||||
final_tick 6111458 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 78453 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 374396 # Number of bytes of host memory used
|
||||
host_seconds 77.80 # Real time elapsed on the host
|
||||
host_tick_rate 30926 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418916 # Number of bytes of host memory used
|
||||
host_seconds 197.62 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99027 # number of read accesses completed
|
||||
system.cpu0.num_writes 53493 # number of write accesses completed
|
||||
system.cpu0.num_reads 99998 # number of read accesses completed
|
||||
system.cpu0.num_writes 53877 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98254 # number of read accesses completed
|
||||
system.cpu1.num_writes 52787 # number of write accesses completed
|
||||
system.cpu1.num_reads 99919 # number of read accesses completed
|
||||
system.cpu1.num_writes 53996 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99047 # number of read accesses completed
|
||||
system.cpu2.num_writes 53306 # number of write accesses completed
|
||||
system.cpu2.num_reads 99673 # number of read accesses completed
|
||||
system.cpu2.num_writes 53416 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 98414 # number of read accesses completed
|
||||
system.cpu3.num_writes 53420 # number of write accesses completed
|
||||
system.cpu3.num_reads 100000 # number of read accesses completed
|
||||
system.cpu3.num_writes 53266 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 53741 # number of write accesses completed
|
||||
system.cpu4.num_reads 99266 # number of read accesses completed
|
||||
system.cpu4.num_writes 53358 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 98111 # number of read accesses completed
|
||||
system.cpu5.num_writes 53002 # number of write accesses completed
|
||||
system.cpu5.num_reads 99912 # number of read accesses completed
|
||||
system.cpu5.num_writes 54055 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99154 # number of read accesses completed
|
||||
system.cpu6.num_writes 52587 # number of write accesses completed
|
||||
system.cpu6.num_reads 99083 # number of read accesses completed
|
||||
system.cpu6.num_writes 53609 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99215 # number of read accesses completed
|
||||
system.cpu7.num_writes 53364 # number of write accesses completed
|
||||
system.cpu7.num_reads 99673 # number of read accesses completed
|
||||
system.cpu7.num_writes 53053 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,74 +1,82 @@
|
|||
system.cpu0: completed 10000 read, 5308 write accesses @570767
|
||||
system.cpu5: completed 10000 read, 5470 write accesses @573498
|
||||
system.cpu1: completed 10000 read, 5429 write accesses @573920
|
||||
system.cpu7: completed 10000 read, 5290 write accesses @575321
|
||||
system.cpu4: completed 10000 read, 5445 write accesses @585929
|
||||
system.cpu3: completed 10000 read, 5486 write accesses @586872
|
||||
system.cpu6: completed 10000 read, 5559 write accesses @588791
|
||||
system.cpu2: completed 10000 read, 5302 write accesses @590705
|
||||
system.cpu1: completed 20000 read, 10655 write accesses @1140898
|
||||
system.cpu7: completed 20000 read, 10580 write accesses @1148482
|
||||
system.cpu4: completed 20000 read, 10689 write accesses @1149967
|
||||
system.cpu0: completed 20000 read, 10632 write accesses @1151560
|
||||
system.cpu3: completed 20000 read, 10736 write accesses @1152482
|
||||
system.cpu5: completed 20000 read, 10944 write accesses @1160453
|
||||
system.cpu6: completed 20000 read, 10906 write accesses @1167829
|
||||
system.cpu2: completed 20000 read, 10785 write accesses @1181432
|
||||
system.cpu7: completed 30000 read, 15883 write accesses @1719841
|
||||
system.cpu1: completed 30000 read, 16166 write accesses @1721891
|
||||
system.cpu4: completed 30000 read, 16033 write accesses @1722326
|
||||
system.cpu3: completed 30000 read, 16219 write accesses @1736719
|
||||
system.cpu0: completed 30000 read, 16143 write accesses @1737446
|
||||
system.cpu5: completed 30000 read, 16313 write accesses @1738202
|
||||
system.cpu6: completed 30000 read, 16098 write accesses @1755658
|
||||
system.cpu2: completed 30000 read, 16394 write accesses @1762469
|
||||
system.cpu7: completed 40000 read, 21291 write accesses @2297271
|
||||
system.cpu1: completed 40000 read, 21590 write accesses @2298548
|
||||
system.cpu4: completed 40000 read, 21488 write accesses @2312342
|
||||
system.cpu6: completed 40000 read, 21332 write accesses @2321888
|
||||
system.cpu5: completed 40000 read, 21705 write accesses @2326997
|
||||
system.cpu3: completed 40000 read, 21707 write accesses @2330357
|
||||
system.cpu2: completed 40000 read, 21706 write accesses @2332615
|
||||
system.cpu0: completed 40000 read, 21524 write accesses @2334713
|
||||
system.cpu7: completed 50000 read, 26831 write accesses @2881244
|
||||
system.cpu1: completed 50000 read, 27020 write accesses @2890941
|
||||
system.cpu4: completed 50000 read, 27058 write accesses @2898430
|
||||
system.cpu3: completed 50000 read, 27008 write accesses @2902889
|
||||
system.cpu6: completed 50000 read, 26758 write accesses @2903882
|
||||
system.cpu5: completed 50000 read, 27004 write accesses @2909259
|
||||
system.cpu0: completed 50000 read, 27056 write accesses @2926100
|
||||
system.cpu2: completed 50000 read, 27098 write accesses @2926472
|
||||
system.cpu7: completed 60000 read, 32186 write accesses @3453644
|
||||
system.cpu4: completed 60000 read, 32482 write accesses @3465349
|
||||
system.cpu1: completed 60000 read, 32394 write accesses @3472313
|
||||
system.cpu5: completed 60000 read, 32325 write accesses @3483119
|
||||
system.cpu3: completed 60000 read, 32421 write accesses @3485537
|
||||
system.cpu6: completed 60000 read, 32185 write accesses @3493077
|
||||
system.cpu0: completed 60000 read, 32338 write accesses @3495286
|
||||
system.cpu2: completed 60000 read, 32370 write accesses @3496153
|
||||
system.cpu7: completed 70000 read, 37611 write accesses @4033523
|
||||
system.cpu4: completed 70000 read, 37774 write accesses @4042787
|
||||
system.cpu1: completed 70000 read, 37690 write accesses @4052999
|
||||
system.cpu3: completed 70000 read, 37732 write accesses @4060208
|
||||
system.cpu5: completed 70000 read, 37748 write accesses @4060547
|
||||
system.cpu2: completed 70000 read, 37645 write accesses @4064696
|
||||
system.cpu0: completed 70000 read, 37774 write accesses @4071656
|
||||
system.cpu6: completed 70000 read, 37516 write accesses @4081376
|
||||
system.cpu7: completed 80000 read, 43002 write accesses @4618082
|
||||
system.cpu4: completed 80000 read, 42974 write accesses @4622306
|
||||
system.cpu2: completed 80000 read, 43016 write accesses @4629591
|
||||
system.cpu3: completed 80000 read, 43060 write accesses @4631933
|
||||
system.cpu0: completed 80000 read, 42919 write accesses @4636700
|
||||
system.cpu5: completed 80000 read, 43162 write accesses @4639808
|
||||
system.cpu1: completed 80000 read, 42988 write accesses @4647998
|
||||
system.cpu6: completed 80000 read, 42866 write accesses @4656086
|
||||
system.cpu7: completed 90000 read, 48437 write accesses @5173289
|
||||
system.cpu4: completed 90000 read, 48464 write accesses @5207890
|
||||
system.cpu3: completed 90000 read, 48532 write accesses @5210569
|
||||
system.cpu2: completed 90000 read, 48392 write accesses @5213621
|
||||
system.cpu5: completed 90000 read, 48493 write accesses @5223220
|
||||
system.cpu0: completed 90000 read, 48496 write accesses @5233894
|
||||
system.cpu6: completed 90000 read, 48247 write accesses @5234744
|
||||
system.cpu1: completed 90000 read, 48380 write accesses @5239171
|
||||
system.cpu7: completed 100000 read, 53766 write accesses @5747338
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu5: completed 10000 read, 5478 write accesses @567161
|
||||
system.cpu3: completed 10000 read, 5277 write accesses @567758
|
||||
system.cpu1: completed 10000 read, 5424 write accesses @571139
|
||||
system.cpu2: completed 10000 read, 5363 write accesses @576050
|
||||
system.cpu6: completed 10000 read, 5463 write accesses @585533
|
||||
system.cpu4: completed 10000 read, 5420 write accesses @589179
|
||||
system.cpu7: completed 10000 read, 5472 write accesses @590379
|
||||
system.cpu0: completed 10000 read, 5369 write accesses @590533
|
||||
system.cpu5: completed 20000 read, 10791 write accesses @1146089
|
||||
system.cpu3: completed 20000 read, 10874 write accesses @1153309
|
||||
system.cpu1: completed 20000 read, 10881 write accesses @1155896
|
||||
system.cpu2: completed 20000 read, 10800 write accesses @1162820
|
||||
system.cpu0: completed 20000 read, 10720 write accesses @1163331
|
||||
system.cpu4: completed 20000 read, 10833 write accesses @1163813
|
||||
system.cpu6: completed 20000 read, 10762 write accesses @1164662
|
||||
system.cpu7: completed 20000 read, 10940 write accesses @1175272
|
||||
system.cpu3: completed 30000 read, 16099 write accesses @1730233
|
||||
system.cpu5: completed 30000 read, 16356 write accesses @1731718
|
||||
system.cpu6: completed 30000 read, 16169 write accesses @1737322
|
||||
system.cpu0: completed 30000 read, 16008 write accesses @1738364
|
||||
system.cpu1: completed 30000 read, 16522 write accesses @1739971
|
||||
system.cpu2: completed 30000 read, 16224 write accesses @1741457
|
||||
system.cpu4: completed 30000 read, 16211 write accesses @1745036
|
||||
system.cpu7: completed 30000 read, 16445 write accesses @1750339
|
||||
system.cpu5: completed 40000 read, 21741 write accesses @2306008
|
||||
system.cpu6: completed 40000 read, 21530 write accesses @2310178
|
||||
system.cpu2: completed 40000 read, 21620 write accesses @2310592
|
||||
system.cpu4: completed 40000 read, 21531 write accesses @2315393
|
||||
system.cpu0: completed 40000 read, 21438 write accesses @2316997
|
||||
system.cpu3: completed 40000 read, 21653 write accesses @2317686
|
||||
system.cpu1: completed 40000 read, 21749 write accesses @2319017
|
||||
system.cpu7: completed 40000 read, 21844 write accesses @2338046
|
||||
system.cpu3: completed 50000 read, 27002 write accesses @2880938
|
||||
system.cpu2: completed 50000 read, 27054 write accesses @2886893
|
||||
system.cpu6: completed 50000 read, 26777 write accesses @2887224
|
||||
system.cpu5: completed 50000 read, 27071 write accesses @2894287
|
||||
system.cpu4: completed 50000 read, 26806 write accesses @2897144
|
||||
system.cpu0: completed 50000 read, 26853 write accesses @2903681
|
||||
system.cpu7: completed 50000 read, 27200 write accesses @2905958
|
||||
system.cpu1: completed 50000 read, 27246 write accesses @2906447
|
||||
system.cpu2: completed 60000 read, 32371 write accesses @3448040
|
||||
system.cpu6: completed 60000 read, 32232 write accesses @3458102
|
||||
system.cpu3: completed 60000 read, 32278 write accesses @3464050
|
||||
system.cpu0: completed 60000 read, 32186 write accesses @3466844
|
||||
system.cpu4: completed 60000 read, 31956 write accesses @3470756
|
||||
system.cpu5: completed 60000 read, 32561 write accesses @3476407
|
||||
system.cpu1: completed 60000 read, 32600 write accesses @3479914
|
||||
system.cpu7: completed 60000 read, 32524 write accesses @3491585
|
||||
system.cpu2: completed 70000 read, 37778 write accesses @4027715
|
||||
system.cpu3: completed 70000 read, 37641 write accesses @4032589
|
||||
system.cpu6: completed 70000 read, 37624 write accesses @4034915
|
||||
system.cpu4: completed 70000 read, 37315 write accesses @4048771
|
||||
system.cpu0: completed 70000 read, 37650 write accesses @4058138
|
||||
system.cpu1: completed 70000 read, 38210 write accesses @4062463
|
||||
system.cpu5: completed 70000 read, 37970 write accesses @4063291
|
||||
system.cpu7: completed 70000 read, 37837 write accesses @4069993
|
||||
system.cpu2: completed 80000 read, 43081 write accesses @4605440
|
||||
system.cpu6: completed 80000 read, 43005 write accesses @4612592
|
||||
system.cpu3: completed 80000 read, 43103 write accesses @4614137
|
||||
system.cpu5: completed 80000 read, 43266 write accesses @4625729
|
||||
system.cpu0: completed 80000 read, 42925 write accesses @4631387
|
||||
system.cpu4: completed 80000 read, 42800 write accesses @4633690
|
||||
system.cpu1: completed 80000 read, 43498 write accesses @4640305
|
||||
system.cpu7: completed 80000 read, 43249 write accesses @4647178
|
||||
system.cpu2: completed 90000 read, 48427 write accesses @5170760
|
||||
system.cpu3: completed 90000 read, 48430 write accesses @5181607
|
||||
system.cpu6: completed 90000 read, 48549 write accesses @5189137
|
||||
system.cpu5: completed 90000 read, 48576 write accesses @5206014
|
||||
system.cpu4: completed 90000 read, 48077 write accesses @5207168
|
||||
system.cpu1: completed 90000 read, 48840 write accesses @5207183
|
||||
system.cpu0: completed 90000 read, 48241 write accesses @5207339
|
||||
system.cpu7: completed 90000 read, 48589 write accesses @5224757
|
||||
system.cpu2: completed 100000 read, 53907 write accesses @5753960
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.005747 # Number of seconds simulated
|
||||
sim_ticks 5747338 # Number of ticks simulated
|
||||
final_tick 5747338 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.005754 # Number of seconds simulated
|
||||
sim_ticks 5753960 # Number of ticks simulated
|
||||
final_tick 5753960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 47566 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409708 # Number of bytes of host memory used
|
||||
host_seconds 120.83 # Real time elapsed on the host
|
||||
host_tick_rate 28381 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 417808 # Number of bytes of host memory used
|
||||
host_seconds 202.74 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -157,29 +157,29 @@ system.dir_cntrl0.probeFilter.num_tag_array_reads 0
|
|||
system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes
|
||||
system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 98701 # number of read accesses completed
|
||||
system.cpu0.num_writes 53180 # number of write accesses completed
|
||||
system.cpu0.num_reads 99424 # number of read accesses completed
|
||||
system.cpu0.num_writes 53376 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 98822 # number of read accesses completed
|
||||
system.cpu1.num_writes 52970 # number of write accesses completed
|
||||
system.cpu1.num_reads 99626 # number of read accesses completed
|
||||
system.cpu1.num_writes 54012 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99173 # number of read accesses completed
|
||||
system.cpu2.num_writes 53394 # number of write accesses completed
|
||||
system.cpu2.num_reads 100000 # number of read accesses completed
|
||||
system.cpu2.num_writes 53908 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99438 # number of read accesses completed
|
||||
system.cpu3.num_writes 53653 # number of write accesses completed
|
||||
system.cpu3.num_reads 99716 # number of read accesses completed
|
||||
system.cpu3.num_writes 53812 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99047 # number of read accesses completed
|
||||
system.cpu4.num_writes 53311 # number of write accesses completed
|
||||
system.cpu4.num_reads 99512 # number of read accesses completed
|
||||
system.cpu4.num_writes 53333 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99288 # number of read accesses completed
|
||||
system.cpu5.num_writes 53451 # number of write accesses completed
|
||||
system.cpu5.num_reads 99476 # number of read accesses completed
|
||||
system.cpu5.num_writes 53666 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 98768 # number of read accesses completed
|
||||
system.cpu6.num_writes 53052 # number of write accesses completed
|
||||
system.cpu6.num_reads 99747 # number of read accesses completed
|
||||
system.cpu6.num_writes 53910 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 53766 # number of write accesses completed
|
||||
system.cpu7.num_reads 99133 # number of read accesses completed
|
||||
system.cpu7.num_writes 53472 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,26 +1,26 @@
|
|||
Real time: Sep/01/2012 13:48:23
|
||||
Real time: Oct/08/2012 22:20:34
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 43
|
||||
Elapsed_time_in_minutes: 0.716667
|
||||
Elapsed_time_in_hours: 0.0119444
|
||||
Elapsed_time_in_days: 0.000497685
|
||||
Elapsed_time_in_seconds: 79
|
||||
Elapsed_time_in_minutes: 1.31667
|
||||
Elapsed_time_in_hours: 0.0219444
|
||||
Elapsed_time_in_days: 0.000914352
|
||||
|
||||
Virtual_time_in_seconds: 43.31
|
||||
Virtual_time_in_minutes: 0.721833
|
||||
Virtual_time_in_hours: 0.0120306
|
||||
Virtual_time_in_days: 0.000501273
|
||||
Virtual_time_in_seconds: 48.17
|
||||
Virtual_time_in_minutes: 0.802833
|
||||
Virtual_time_in_hours: 0.0133806
|
||||
Virtual_time_in_days: 0.000557523
|
||||
|
||||
Ruby_current_time: 8642753
|
||||
Ruby_current_time: 8594451
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 8642753
|
||||
Ruby_cycles: 8594451
|
||||
|
||||
mbytes_resident: 60.6562
|
||||
mbytes_total: 399.672
|
||||
resident_ratio: 0.151804
|
||||
mbytes_resident: 69.9141
|
||||
mbytes_total: 408.566
|
||||
resident_ratio: 0.17113
|
||||
|
||||
ruby_cycles_executed: [ 8642754 8642754 8642754 8642754 8642754 8642754 8642754 8642754 ]
|
||||
ruby_cycles_executed: [ 8594452 8594452 8594452 8594452 8594452 8594452 8594452 8594452 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
|
@ -30,29 +30,29 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 616251 average: 15.9984 | standard deviation: 0.126869 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 616131 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 612679 average: 15.9984 | standard deviation: 0.127251 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 10 612557 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 32 max: 4776 count: 616123 average: 1795.35 | standard deviation: 414.477 | 0 1 4 5 4 6 2 4 5 3 2 2 1 4 3 0 4 16 19 24 35 84 107 158 246 394 516 799 1053 1257 1834 2502 2826 3510 4476 5278 6753 7207 7603 9693 11698 11058 12663 14078 14754 17257 16918 15782 18905 20633 18435 19307 19900 19344 21176 19234 17152 19082 20051 16188 16264 15715 14908 15416 13291 11277 12219 11916 9452 9307 8556 7808 7864 6457 5309 5581 5515 4250 3842 3580 3265 3103 2466 1908 2073 1994 1517 1313 1242 1090 1028 790 677 670 662 435 413 368 358 318 235 216 208 174 141 115 105 85 103 63 53 50 50 35 26 25 21 27 14 16 14 4 12 10 6 9 5 5 1 3 2 1 3 1 2 2 2 0 0 0 0 4 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 4737 count: 400262 average: 1795.26 | standard deviation: 414.645 | 0 1 4 2 4 4 1 2 3 2 2 0 0 3 2 0 3 10 13 11 23 53 66 110 159 266 334 537 699 799 1186 1637 1820 2298 2878 3407 4350 4680 4906 6373 7625 7226 8201 9120 9644 11229 10853 10342 12294 13400 12030 12512 12946 12569 13875 12476 11156 12382 13030 10587 10544 10172 9663 9945 8585 7315 7818 7765 6162 6022 5538 5088 5151 4134 3417 3701 3583 2767 2452 2314 2095 1997 1601 1255 1387 1294 988 884 833 737 684 490 452 419 436 288 285 220 225 214 149 143 140 122 94 73 73 51 66 34 32 32 31 24 15 10 10 18 7 11 9 3 5 7 6 7 4 2 0 3 0 1 3 1 2 1 2 0 0 0 0 4 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 32 max: 4776 count: 215861 average: 1795.51 | standard deviation: 414.166 | 0 0 0 3 0 2 1 2 2 1 0 2 1 1 1 0 1 6 6 13 12 31 41 48 87 128 182 262 354 458 648 865 1006 1212 1598 1871 2403 2527 2697 3320 4073 3832 4462 4958 5110 6028 6065 5440 6611 7233 6405 6795 6954 6775 7301 6758 5996 6700 7021 5601 5720 5543 5245 5471 4706 3962 4401 4151 3290 3285 3018 2720 2713 2323 1892 1880 1932 1483 1390 1266 1170 1106 865 653 686 700 529 429 409 353 344 300 225 251 226 147 128 148 133 104 86 73 68 52 47 42 32 34 37 29 21 18 19 11 11 15 11 9 7 5 5 1 7 3 0 2 1 3 1 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 4776 count: 607868 average: 1796.88 | standard deviation: 414.375 | 0 1 4 5 4 6 2 4 5 3 2 2 1 4 3 0 4 16 19 23 33 79 102 150 235 382 500 770 1020 1209 1785 2449 2745 3429 4369 5167 6620 7042 7423 9530 11521 10828 12435 13885 14505 16983 16670 15485 18664 20359 18181 19011 19634 19059 20930 19001 16911 18870 19850 15969 16076 15575 14760 15247 13149 11146 12125 11810 9354 9206 8478 7728 7786 6400 5234 5534 5471 4213 3806 3559 3230 3075 2450 1891 2058 1978 1499 1308 1237 1081 1020 780 667 662 659 434 408 362 357 314 235 214 208 174 140 113 104 84 103 63 53 50 50 35 26 25 21 26 14 16 14 4 12 10 6 9 5 5 1 3 2 1 3 1 2 2 2 0 0 0 0 4 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache_wCC: [binsize: 32 max: 3752 count: 8255 average: 1682.74 | standard deviation: 406.431 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 5 5 8 11 12 16 29 33 48 49 53 81 81 107 111 133 165 180 163 177 230 228 193 249 274 248 297 241 274 254 296 266 285 246 233 241 212 201 219 188 140 148 169 142 131 94 106 98 101 78 80 78 57 75 47 44 37 36 21 35 28 16 17 15 16 18 5 5 9 8 10 10 8 3 1 5 6 1 4 0 2 0 0 1 2 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 32 max: 4653 count: 612551 average: 1795.7 | standard deviation: 410.66 | 0 1 4 5 4 6 2 4 4 5 2 2 2 5 3 0 0 6 14 17 28 51 113 126 222 341 478 739 943 1172 1767 2399 2690 3474 4236 4975 6483 7278 7353 9544 11638 11194 12606 14095 14781 17182 16959 16021 18801 20784 18178 19118 19510 19480 21166 19191 16928 19138 19616 16277 16268 15657 15140 15502 13442 11313 12308 12228 9547 9169 8703 7770 7869 6263 5198 5485 5264 4033 3801 3587 3147 3163 2478 2078 2041 1979 1479 1363 1116 1041 1026 720 599 673 609 407 374 362 280 234 210 164 195 189 108 117 93 78 70 54 43 54 50 33 34 21 18 15 18 13 13 5 6 5 4 10 3 7 8 5 5 5 4 2 3 3 2 0 0 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 4653 count: 398259 average: 1796.14 | standard deviation: 410.545 | 0 1 4 2 4 4 1 2 2 3 1 0 2 3 2 0 0 4 9 13 19 34 69 77 142 213 312 496 634 789 1112 1557 1708 2226 2742 3251 4192 4713 4761 6194 7550 7329 8214 9166 9655 11143 11019 10418 12237 13560 11738 12340 12645 12602 13722 12490 11061 12504 12769 10620 10543 10215 9778 10113 8796 7377 7953 7936 6168 5941 5772 5011 5117 4169 3341 3601 3439 2674 2487 2285 2012 2017 1631 1369 1349 1275 989 894 721 679 658 468 412 453 398 269 258 217 175 160 142 102 128 123 67 76 57 44 47 33 26 32 31 19 17 11 12 10 11 10 10 3 2 4 3 7 1 3 5 2 4 4 4 1 1 2 1 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 32 max: 4626 count: 214292 average: 1794.89 | standard deviation: 410.873 | 0 0 0 3 0 2 1 2 2 2 1 2 0 2 1 0 0 2 5 4 9 17 44 49 80 128 166 243 309 383 655 842 982 1248 1494 1724 2291 2565 2592 3350 4088 3865 4392 4929 5126 6039 5940 5603 6564 7224 6440 6778 6865 6878 7444 6701 5867 6634 6847 5657 5725 5442 5362 5389 4646 3936 4355 4292 3379 3228 2931 2759 2752 2094 1857 1884 1825 1359 1314 1302 1135 1146 847 709 692 704 490 469 395 362 368 252 187 220 211 138 116 145 105 74 68 62 67 66 41 41 36 34 23 21 17 22 19 14 17 10 6 5 7 3 3 2 4 1 1 3 2 4 3 3 1 1 0 1 2 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 4653 count: 604395 average: 1797.09 | standard deviation: 410.541 | 0 1 4 5 4 6 2 4 4 5 2 2 2 5 3 0 0 5 14 16 27 51 107 121 212 329 459 718 907 1137 1731 2346 2618 3386 4136 4857 6358 7136 7189 9366 11477 10968 12372 13884 14549 16941 16662 15768 18551 20542 17864 18850 19270 19247 20917 18940 16714 18905 19436 16065 16081 15483 14980 15328 13265 11178 12186 12123 9437 9093 8626 7689 7797 6193 5141 5442 5224 3985 3768 3556 3119 3142 2458 2058 2027 1963 1464 1353 1109 1034 1018 712 590 667 604 406 370 361 279 234 209 164 191 188 105 115 92 77 68 54 43 53 50 33 33 21 17 15 18 13 13 5 6 5 4 9 3 7 8 5 5 5 4 2 3 3 2 0 0 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache_wCC: [binsize: 32 max: 4002 count: 8156 average: 1692.69 | standard deviation: 406.323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 6 5 10 12 19 21 36 35 36 53 72 88 100 118 125 142 164 178 161 226 234 211 232 241 297 253 250 242 314 268 240 233 249 251 214 233 180 212 187 174 160 174 177 135 122 105 110 76 77 81 72 70 57 43 40 48 33 31 28 21 20 20 14 16 15 10 7 7 8 8 9 6 5 1 4 1 1 0 1 0 4 1 3 2 1 1 2 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 8255
|
||||
imcomplete_wCC_Times: 8156
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 175 count: 7 average: 113.714 | standard deviation: 50.5833 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 607861
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 4737 count: 394885 average: 1796.82 | standard deviation: 414.485 | 0 1 4 2 4 4 1 2 3 2 2 0 0 3 2 0 3 10 13 11 21 49 64 105 152 257 322 518 679 769 1153 1596 1772 2247 2811 3334 4264 4563 4792 6261 7499 7072 8051 8990 9488 11054 10677 10152 12134 13228 11861 12318 12772 12386 13725 12331 11008 12241 12895 10439 10424 10080 9578 9838 8498 7238 7755 7697 6105 5957 5481 5033 5099 4100 3368 3668 3554 2742 2429 2302 2071 1979 1590 1241 1375 1283 979 882 829 732 677 483 443 413 433 287 283 216 225 211 149 141 140 122 93 72 72 50 66 34 32 32 31 24 15 10 10 17 7 11 9 3 5 7 6 7 4 2 0 3 0 1 3 1 2 1 2 0 0 0 0 4 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 3752 count: 5377 average: 1681.26 | standard deviation: 410.533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 2 5 7 9 12 19 20 30 33 41 48 51 67 73 86 117 114 112 126 154 150 130 156 175 176 190 160 172 169 194 174 183 150 145 148 141 135 148 120 92 85 107 87 77 63 68 57 65 57 55 52 34 49 33 29 25 23 12 24 18 11 14 12 11 9 2 4 5 7 7 9 6 3 1 2 4 0 3 0 2 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 4776 count: 212983 average: 1797 | standard deviation: 414.172 | 0 0 0 3 0 2 1 2 2 1 0 2 1 1 1 0 1 6 6 12 12 30 38 45 83 125 178 252 341 440 632 853 973 1182 1558 1833 2356 2479 2631 3269 4022 3756 4384 4895 5017 5929 5993 5333 6530 7131 6320 6693 6862 6673 7205 6670 5903 6629 6955 5530 5652 5495 5182 5409 4651 3908 4370 4113 3249 3249 2997 2695 2687 2300 1866 1866 1917 1471 1377 1257 1159 1096 860 650 683 695 520 426 408 349 343 297 224 249 226 147 125 146 132 103 86 73 68 52 47 41 32 34 37 29 21 18 19 11 11 15 11 9 7 5 5 1 7 3 0 2 1 3 1 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 3360 count: 2878 average: 1685.51 | standard deviation: 398.712 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 3 3 4 3 4 10 13 18 16 12 33 30 40 38 47 48 66 51 51 76 78 63 93 99 72 107 81 102 85 102 92 102 96 88 93 71 66 71 68 48 63 62 55 54 31 38 41 36 21 25 26 23 26 14 15 12 13 9 11 10 5 3 3 5 9 3 1 4 1 3 1 2 0 0 3 2 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 604388
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 4653 count: 392936 average: 1797.52 | standard deviation: 410.479 | 0 1 4 2 4 4 1 2 2 3 1 0 2 3 2 0 0 3 9 12 19 34 66 75 136 203 303 482 609 767 1090 1519 1664 2178 2685 3176 4112 4612 4654 6074 7444 7169 8063 9044 9500 10991 10831 10240 12073 13400 11535 12164 12489 12466 13560 12328 10926 12344 12645 10474 10409 10101 9677 9992 8674 7283 7879 7873 6097 5889 5722 4966 5062 4125 3303 3568 3414 2646 2464 2266 1993 2001 1620 1355 1343 1263 982 889 716 673 654 464 405 451 396 269 255 217 174 160 142 102 125 123 65 76 56 43 45 33 26 31 31 19 17 11 11 10 11 10 10 3 2 4 3 6 1 3 5 2 4 4 4 1 1 2 1 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 4002 count: 5323 average: 1694.26 | standard deviation: 402.526 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 3 2 6 10 9 14 25 22 22 38 44 48 57 75 80 101 107 120 106 160 151 122 155 152 188 178 164 160 203 176 156 136 162 162 135 160 124 146 134 114 101 121 122 94 74 63 71 52 50 45 55 44 38 33 25 28 23 19 19 16 11 14 6 12 7 5 5 6 4 4 7 2 2 0 3 0 1 0 0 0 3 0 2 0 1 1 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 4626 count: 211459 average: 1796.3 | standard deviation: 410.657 | 0 0 0 3 0 2 1 2 2 2 1 2 0 2 1 0 0 2 5 4 8 17 41 46 76 126 156 236 298 370 641 827 954 1208 1451 1681 2246 2524 2535 3292 4033 3799 4309 4840 5049 5950 5831 5528 6478 7142 6329 6686 6781 6781 7357 6612 5788 6561 6791 5591 5672 5382 5303 5336 4591 3895 4307 4250 3340 3204 2904 2723 2735 2068 1838 1874 1810 1339 1304 1290 1126 1141 838 703 684 700 482 464 393 361 364 248 185 216 208 137 115 144 105 74 67 62 66 65 40 39 36 34 23 21 17 22 19 14 16 10 6 5 7 3 3 2 4 1 1 3 2 4 3 3 1 1 0 1 2 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 3670 count: 2833 average: 1689.73 | standard deviation: 413.417 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 3 4 2 10 7 11 13 14 15 28 40 43 43 45 41 57 58 55 66 83 89 77 89 109 75 86 82 111 92 84 97 87 89 79 73 56 66 53 60 59 53 55 41 48 42 39 24 27 36 17 26 19 10 15 20 10 12 9 5 9 6 8 4 8 5 2 1 4 4 2 4 3 1 1 1 0 0 1 0 1 1 1 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -66,11 +66,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 21 count: 1234820 average: 0.00719619 | standard deviation: 0.155601 | 1231314 951 818 846 872 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 21 count: 1234820 average: 0.00719619 | standard deviation: 0.155601 | 1231314 951 818 846 872 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 22 count: 1227672 average: 0.0072389 | standard deviation: 0.160195 | 1224232 923 774 826 891 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1227672 average: 0.0072389 | standard deviation: 0.160195 | 1224232 923 774 826 891 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 616123 average: 0.000835872 | standard deviation: 0.0469998 | 615902 40 84 81 16 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 21 count: 618697 average: 0.01353 | standard deviation: 0.214574 | 615412 911 734 765 856 1 0 0 0 0 1 1 1 4 3 2 1 0 2 2 0 1 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 612551 average: 0.00100726 | standard deviation: 0.0517903 | 612293 37 99 106 16 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 22 count: 615121 average: 0.0134445 | standard deviation: 0.22016 | 611939 886 675 720 875 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
|
@ -82,337 +82,337 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 21 count: 1234820 average: 0.00719619
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 43
|
||||
user_time: 48
|
||||
system_time: 0
|
||||
page_reclaims: 11522
|
||||
page_faults: 0
|
||||
page_reclaims: 10401
|
||||
page_faults: 3
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 184
|
||||
block_inputs: 480
|
||||
block_outputs: 232
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 1848417 14787336
|
||||
total_msg_count_Data: 1831398 131860656
|
||||
total_msg_count_Response_Data: 1848370 133082640
|
||||
total_msg_count_Writeback_Control: 1856091 14848728
|
||||
total_msgs: 7384276 total_bytes: 294579360
|
||||
total_msg_count_Control: 1837698 14701584
|
||||
total_msg_count_Data: 1820943 131107896
|
||||
total_msg_count_Response_Data: 1837653 132311016
|
||||
total_msg_count_Writeback_Control: 1845363 14762904
|
||||
total_msgs: 7341657 total_bytes: 292883400
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 4.48511
|
||||
links_utilized_percent_switch_0_link_0: 4.47733 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 4.49289 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 4.4737
|
||||
links_utilized_percent_switch_0_link_0: 4.46588 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 4.48153 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 77360 5569920 [ 0 0 0 0 77360 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 77689 621512 [ 0 0 0 77689 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 77364 618912 [ 0 0 77364 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 76700 5522400 [ 0 0 76700 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 995 71640 [ 0 0 0 0 995 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 76730 5524560 [ 0 0 0 0 76730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 77065 616520 [ 0 0 0 77065 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 76731 613848 [ 0 0 76731 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 76026 5473872 [ 0 0 76026 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 1040 74880 [ 0 0 0 0 1040 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 4.47412
|
||||
links_utilized_percent_switch_1_link_0: 4.46635 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 4.48189 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 4.46364
|
||||
links_utilized_percent_switch_1_link_0: 4.45628 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 4.471 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 77170 5556240 [ 0 0 0 0 77170 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 77501 620008 [ 0 0 0 77501 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 77173 617384 [ 0 0 77173 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Data: 76458 5504976 [ 0 0 76458 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1047 75384 [ 0 0 0 0 1047 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 76567 5512824 [ 0 0 0 0 76567 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 76882 615056 [ 0 0 0 76882 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 76569 612552 [ 0 0 76569 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Data: 75853 5461416 [ 0 0 75853 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1030 74160 [ 0 0 0 0 1030 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 4.45232
|
||||
links_utilized_percent_switch_2_link_0: 4.44489 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 4.45975 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 4.44318
|
||||
links_utilized_percent_switch_2_link_0: 4.43569 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 4.45067 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 77121 616968 [ 0 0 0 77121 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 76801 614408 [ 0 0 76801 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 76122 5480784 [ 0 0 76122 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 999 71928 [ 0 0 0 0 999 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 76213 5487336 [ 0 0 0 0 76213 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 76529 612232 [ 0 0 0 76529 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 76216 609728 [ 0 0 76216 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 75497 5435784 [ 0 0 75497 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1037 74664 [ 0 0 0 0 1037 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 4.4511
|
||||
links_utilized_percent_switch_3_link_0: 4.44343 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 4.45876 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 4.44459
|
||||
links_utilized_percent_switch_3_link_0: 4.43679 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 4.45238 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 76774 5527728 [ 0 0 0 0 76774 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 77103 616824 [ 0 0 0 77103 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 76775 614200 [ 0 0 76775 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 76039 5474808 [ 0 0 76039 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1066 76752 [ 0 0 0 0 1066 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 76230 5488560 [ 0 0 0 0 76230 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 76565 612520 [ 0 0 0 76565 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 76231 609848 [ 0 0 76231 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 75505 5436360 [ 0 0 75505 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1060 76320 [ 0 0 0 0 1060 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 4.47992
|
||||
links_utilized_percent_switch_4_link_0: 4.47268 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 4.48716 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4: 4.47109
|
||||
links_utilized_percent_switch_4_link_0: 4.46353 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 4.47864 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 77282 5564304 [ 0 0 0 0 77282 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 77591 620728 [ 0 0 0 77591 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 77282 618256 [ 0 0 77282 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Data: 76562 5512464 [ 0 0 76562 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 1032 74304 [ 0 0 0 0 1032 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 76691 5521752 [ 0 0 0 0 76691 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 77013 616104 [ 0 0 0 77013 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 76694 613552 [ 0 0 76694 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Data: 76026 5473872 [ 0 0 76026 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 989 71208 [ 0 0 0 0 989 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_5_inlinks: 2
|
||||
switch_5_outlinks: 2
|
||||
links_utilized_percent_switch_5: 4.45778
|
||||
links_utilized_percent_switch_5_link_0: 4.44972 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 4.46585 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5: 4.47561
|
||||
links_utilized_percent_switch_5_link_0: 4.46773 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 4.4835 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 76881 5535432 [ 0 0 0 0 76881 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 77228 617824 [ 0 0 0 77228 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 76883 615064 [ 0 0 76883 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Data: 76151 5482872 [ 0 0 76151 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1078 77616 [ 0 0 0 0 1078 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 76762 5526864 [ 0 0 0 0 76762 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 77096 616768 [ 0 0 0 77096 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 76764 614112 [ 0 0 76764 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Data: 76109 5479848 [ 0 0 76109 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 991 71352 [ 0 0 0 0 991 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_6_inlinks: 2
|
||||
switch_6_outlinks: 2
|
||||
links_utilized_percent_switch_6: 4.46993
|
||||
links_utilized_percent_switch_6_link_0: 4.46316 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 4.4767 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6: 4.47463
|
||||
links_utilized_percent_switch_6_link_0: 4.46749 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 4.48176 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 77119 5552568 [ 0 0 0 0 77119 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 77408 619264 [ 0 0 0 77408 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 77121 616968 [ 0 0 77121 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Data: 76391 5500152 [ 0 0 76391 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 1020 73440 [ 0 0 0 0 1020 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 76761 5526792 [ 0 0 0 0 76761 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 77064 616512 [ 0 0 0 77064 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 76763 614104 [ 0 0 76763 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Data: 76075 5477400 [ 0 0 76075 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 992 71424 [ 0 0 0 0 992 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_7_inlinks: 2
|
||||
switch_7_outlinks: 2
|
||||
links_utilized_percent_switch_7: 4.44875
|
||||
links_utilized_percent_switch_7_link_0: 4.44123 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 4.45627 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7: 4.46521
|
||||
links_utilized_percent_switch_7_link_0: 4.45799 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 4.47243 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 76737 5525064 [ 0 0 0 0 76737 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 77056 616448 [ 0 0 0 77056 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 76740 613920 [ 0 0 76740 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Data: 76043 5475096 [ 0 0 76043 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 76597 5514984 [ 0 0 0 0 76597 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 76907 615256 [ 0 0 0 76907 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 76598 612784 [ 0 0 76598 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Data: 75890 5464080 [ 0 0 75890 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 1017 73224 [ 0 0 0 0 1017 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_8_inlinks: 2
|
||||
switch_8_outlinks: 2
|
||||
links_utilized_percent_switch_8: 35.2892
|
||||
links_utilized_percent_switch_8_link_0: 35.3495 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 35.229 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8: 35.2846
|
||||
links_utilized_percent_switch_8_link_0: 35.3449 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 35.2243 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_8_link_0_Control: 616139 4929112 [ 0 0 616139 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Data: 610466 43953552 [ 0 0 610466 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 607869 43766568 [ 0 0 0 0 607869 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 618697 4949576 [ 0 0 0 618697 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Control: 612566 4900528 [ 0 0 612566 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Data: 606981 43702632 [ 0 0 606981 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 604395 43516440 [ 0 0 0 0 604395 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 615121 4920968 [ 0 0 0 615121 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_9_inlinks: 9
|
||||
switch_9_outlinks: 9
|
||||
links_utilized_percent_switch_9: 7.88981
|
||||
links_utilized_percent_switch_9_link_0: 4.47733 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 4.46635 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 4.44489 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 4.44343 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 4.4727 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 4.44972 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 4.46316 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 4.44123 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 35.3495 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9: 7.88847
|
||||
links_utilized_percent_switch_9_link_0: 4.46588 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 4.45628 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 4.43569 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 4.43679 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 4.46353 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 4.46773 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 4.46749 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 4.45799 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 35.3449 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 77360 5569920 [ 0 0 0 0 77360 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 77689 621512 [ 0 0 0 77689 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 77170 5556240 [ 0 0 0 0 77170 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 77501 620008 [ 0 0 0 77501 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 77121 616968 [ 0 0 0 77121 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 76774 5527728 [ 0 0 0 0 76774 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 77103 616824 [ 0 0 0 77103 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 77282 5564304 [ 0 0 0 0 77282 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 77591 620728 [ 0 0 0 77591 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 76881 5535432 [ 0 0 0 0 76881 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 77228 617824 [ 0 0 0 77228 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 77119 5552568 [ 0 0 0 0 77119 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 77408 619264 [ 0 0 0 77408 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 76737 5525064 [ 0 0 0 0 76737 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 77056 616448 [ 0 0 0 77056 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 616139 4929112 [ 0 0 616139 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Data: 610466 43953552 [ 0 0 610466 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 76730 5524560 [ 0 0 0 0 76730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 77065 616520 [ 0 0 0 77065 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 76567 5512824 [ 0 0 0 0 76567 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 76882 615056 [ 0 0 0 76882 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 76213 5487336 [ 0 0 0 0 76213 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 76529 612232 [ 0 0 0 76529 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 76230 5488560 [ 0 0 0 0 76230 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 76565 612520 [ 0 0 0 76565 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 76691 5521752 [ 0 0 0 0 76691 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 77013 616104 [ 0 0 0 77013 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 76762 5526864 [ 0 0 0 0 76762 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 77096 616768 [ 0 0 0 77096 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 76761 5526792 [ 0 0 0 0 76761 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 77064 616512 [ 0 0 0 77064 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 76597 5514984 [ 0 0 0 0 76597 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 76907 615256 [ 0 0 0 76907 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 612566 4900528 [ 0 0 612566 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Data: 606981 43702632 [ 0 0 606981 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 77364
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 77364
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 76731
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 76731
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 65.016%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 34.984%
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 65.0962%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 34.9038%
|
||||
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 77364 100%
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 76731 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [50042 50017 50024 50037 50299 50232 49853 49771 ] 400275
|
||||
Load [49593 49882 49908 50150 49949 49848 49638 49304 ] 398272
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [27243 26866 27097 26703 27065 26941 26948 27004 ] 215867
|
||||
Data [77282 76881 77119 76737 77360 77170 76800 76774 ] 616123
|
||||
Fwd_GETX [1032 1078 1020 1018 995 1047 999 1066 ] 8255
|
||||
Store [27101 26882 26855 26448 26782 26721 26578 26927 ] 214294
|
||||
Data [76691 76762 76761 76597 76730 76567 76213 76230 ] 612551
|
||||
Fwd_GETX [989 991 992 1017 1040 1030 1037 1060 ] 8156
|
||||
Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
Replacement [77281 76879 77117 76736 77360 77169 76797 76771 ] 616110
|
||||
Writeback_Ack [76243 75800 76094 75713 76359 76118 75798 75703 ] 607828
|
||||
Writeback_Nack [316 350 294 325 335 336 324 334 ] 2614
|
||||
Replacement [76690 76760 76759 76594 76727 76565 76212 76227 ] 612534
|
||||
Writeback_Ack [75699 75765 75764 75577 75686 75534 75170 75167 ] 604362
|
||||
Writeback_Nack [325 340 308 313 339 318 322 338 ] 2603
|
||||
|
||||
- Transitions -
|
||||
I Load [50042 50017 50024 50037 50299 50232 49853 49771 ] 400275
|
||||
I Load [49593 49882 49908 50150 49949 49848 49638 49304 ] 398272
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [27243 26866 27097 26703 27065 26941 26948 27004 ] 215867
|
||||
I Store [27101 26882 26855 26448 26782 26721 26578 26927 ] 214294
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I Replacement [716 728 726 693 660 711 675 732 ] 5641
|
||||
I Replacement [664 651 684 704 701 712 715 722 ] 5553
|
||||
|
||||
II Writeback_Nack [316 350 294 325 335 336 324 334 ] 2614
|
||||
II Writeback_Nack [325 340 308 313 339 318 322 338 ] 2603
|
||||
|
||||
M Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M Fwd_GETX [716 728 726 693 660 711 675 732 ] 5641
|
||||
M Fwd_GETX [664 651 684 704 701 712 715 722 ] 5553
|
||||
M Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
M Replacement [76565 76151 76391 76043 76700 76458 76122 76039 ] 610469
|
||||
M Replacement [76026 76109 76075 75890 76026 75853 75497 75505 ] 606981
|
||||
|
||||
MI Fwd_GETX [316 350 294 325 335 336 324 334 ] 2614
|
||||
MI Fwd_GETX [325 340 308 313 339 318 322 338 ] 2603
|
||||
MI Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Writeback_Ack [76243 75800 76094 75713 76359 76118 75798 75703 ] 607828
|
||||
MI Writeback_Ack [75699 75765 75764 75577 75686 75534 75170 75167 ] 604362
|
||||
MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Data [50041 50016 50022 50034 50297 50229 49853 49770 ] 400262
|
||||
IS Data [49590 49880 49906 50150 49949 49846 49635 49303 ] 398259
|
||||
|
||||
IM Data [27241 26865 27097 26703 27063 26941 26947 27004 ] 215861
|
||||
IM Data [27101 26882 26855 26447 26781 26721 26578 26927 ] 214292
|
||||
|
||||
Cache Stats: system.l1_cntrl1.cacheMemory
|
||||
system.l1_cntrl1.cacheMemory_total_misses: 77173
|
||||
system.l1_cntrl1.cacheMemory_total_demand_misses: 77173
|
||||
system.l1_cntrl1.cacheMemory_total_misses: 76569
|
||||
system.l1_cntrl1.cacheMemory_total_demand_misses: 76569
|
||||
system.l1_cntrl1.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.cacheMemory_request_type_LD: 65.0901%
|
||||
system.l1_cntrl1.cacheMemory_request_type_ST: 34.9099%
|
||||
system.l1_cntrl1.cacheMemory_request_type_LD: 65.1021%
|
||||
system.l1_cntrl1.cacheMemory_request_type_ST: 34.8979%
|
||||
|
||||
system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 77173 100%
|
||||
system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 76569 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl2.cacheMemory
|
||||
system.l1_cntrl2.cacheMemory_total_misses: 76801
|
||||
system.l1_cntrl2.cacheMemory_total_demand_misses: 76801
|
||||
system.l1_cntrl2.cacheMemory_total_misses: 76216
|
||||
system.l1_cntrl2.cacheMemory_total_demand_misses: 76216
|
||||
system.l1_cntrl2.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl2.cacheMemory_request_type_LD: 64.9119%
|
||||
system.l1_cntrl2.cacheMemory_request_type_ST: 35.0881%
|
||||
system.l1_cntrl2.cacheMemory_request_type_LD: 65.1281%
|
||||
system.l1_cntrl2.cacheMemory_request_type_ST: 34.8719%
|
||||
|
||||
system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76801 100%
|
||||
system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76216 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl3.cacheMemory
|
||||
system.l1_cntrl3.cacheMemory_total_misses: 76775
|
||||
system.l1_cntrl3.cacheMemory_total_demand_misses: 76775
|
||||
system.l1_cntrl3.cacheMemory_total_misses: 76231
|
||||
system.l1_cntrl3.cacheMemory_total_demand_misses: 76231
|
||||
system.l1_cntrl3.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl3.cacheMemory_request_type_LD: 64.8271%
|
||||
system.l1_cntrl3.cacheMemory_request_type_ST: 35.1729%
|
||||
system.l1_cntrl3.cacheMemory_request_type_LD: 64.6771%
|
||||
system.l1_cntrl3.cacheMemory_request_type_ST: 35.3229%
|
||||
|
||||
system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76775 100%
|
||||
system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76231 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl4.cacheMemory
|
||||
system.l1_cntrl4.cacheMemory_total_misses: 77285
|
||||
system.l1_cntrl4.cacheMemory_total_demand_misses: 77285
|
||||
system.l1_cntrl4.cacheMemory_total_misses: 76694
|
||||
system.l1_cntrl4.cacheMemory_total_demand_misses: 76694
|
||||
system.l1_cntrl4.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl4.cacheMemory_request_type_LD: 64.75%
|
||||
system.l1_cntrl4.cacheMemory_request_type_ST: 35.25%
|
||||
system.l1_cntrl4.cacheMemory_request_type_LD: 64.6635%
|
||||
system.l1_cntrl4.cacheMemory_request_type_ST: 35.3365%
|
||||
|
||||
system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 77285 100%
|
||||
system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 76694 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl5.cacheMemory
|
||||
system.l1_cntrl5.cacheMemory_total_misses: 76883
|
||||
system.l1_cntrl5.cacheMemory_total_demand_misses: 76883
|
||||
system.l1_cntrl5.cacheMemory_total_misses: 76764
|
||||
system.l1_cntrl5.cacheMemory_total_demand_misses: 76764
|
||||
system.l1_cntrl5.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl5.cacheMemory_request_type_LD: 65.056%
|
||||
system.l1_cntrl5.cacheMemory_request_type_ST: 34.944%
|
||||
system.l1_cntrl5.cacheMemory_request_type_LD: 64.981%
|
||||
system.l1_cntrl5.cacheMemory_request_type_ST: 35.019%
|
||||
|
||||
system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 76883 100%
|
||||
system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 76764 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl6.cacheMemory
|
||||
system.l1_cntrl6.cacheMemory_total_misses: 77121
|
||||
system.l1_cntrl6.cacheMemory_total_demand_misses: 77121
|
||||
system.l1_cntrl6.cacheMemory_total_misses: 76763
|
||||
system.l1_cntrl6.cacheMemory_total_demand_misses: 76763
|
||||
system.l1_cntrl6.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl6.cacheMemory_request_type_LD: 64.8643%
|
||||
system.l1_cntrl6.cacheMemory_request_type_ST: 35.1357%
|
||||
system.l1_cntrl6.cacheMemory_request_type_LD: 65.0157%
|
||||
system.l1_cntrl6.cacheMemory_request_type_ST: 34.9843%
|
||||
|
||||
system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 77121 100%
|
||||
system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 76763 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl7.cacheMemory
|
||||
system.l1_cntrl7.cacheMemory_total_misses: 76740
|
||||
system.l1_cntrl7.cacheMemory_total_demand_misses: 76740
|
||||
system.l1_cntrl7.cacheMemory_total_misses: 76598
|
||||
system.l1_cntrl7.cacheMemory_total_demand_misses: 76598
|
||||
system.l1_cntrl7.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl7.cacheMemory_request_type_LD: 65.2033%
|
||||
system.l1_cntrl7.cacheMemory_request_type_ST: 34.7967%
|
||||
system.l1_cntrl7.cacheMemory_request_type_LD: 65.4717%
|
||||
system.l1_cntrl7.cacheMemory_request_type_ST: 34.5283%
|
||||
|
||||
system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 76740 100%
|
||||
system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 76598 100%
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1215736
|
||||
memory_reads: 607873
|
||||
memory_writes: 607828
|
||||
memory_refreshes: 60020
|
||||
memory_total_request_delays: 87259380
|
||||
memory_delays_per_request: 71.7749
|
||||
memory_delays_in_input_queue: 1519458
|
||||
memory_delays_behind_head_of_bank_queue: 40027777
|
||||
memory_delays_stalled_at_head_of_bank_queue: 45712145
|
||||
memory_stalls_for_bank_busy: 7071199
|
||||
memory_total_requests: 1208787
|
||||
memory_reads: 604397
|
||||
memory_writes: 604365
|
||||
memory_refreshes: 59684
|
||||
memory_total_request_delays: 86764072
|
||||
memory_delays_per_request: 71.7778
|
||||
memory_delays_in_input_queue: 1509968
|
||||
memory_delays_behind_head_of_bank_queue: 39767134
|
||||
memory_delays_stalled_at_head_of_bank_queue: 45486970
|
||||
memory_stalls_for_bank_busy: 7019107
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 11246699
|
||||
memory_stalls_for_arbitration: 9161203
|
||||
memory_stalls_for_bus: 12538876
|
||||
memory_stalls_for_anti_starvation: 11191838
|
||||
memory_stalls_for_arbitration: 9120916
|
||||
memory_stalls_for_bus: 12483705
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 4625197
|
||||
memory_stalls_for_read_read_turnaround: 1068971
|
||||
accesses_per_bank: 38200 37933 37788 38170 38170 38159 38358 38044 38330 38092 38142 38320 37763 37679 37948 38038 37829 37792 38064 38023 38122 37894 38063 37979 37916 37422 38015 37136 37884 38037 38326 38100
|
||||
memory_stalls_for_read_write_turnaround: 4604021
|
||||
memory_stalls_for_read_read_turnaround: 1067383
|
||||
accesses_per_bank: 38081 37280 38059 37993 37808 37669 38264 38058 37708 37676 37829 37380 37422 38256 37284 38186 37917 37744 38412 38248 37780 37359 37760 37766 37532 37908 37452 37826 37364 37732 37412 37622
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [786348 ] 786348
|
||||
GETX [784980 ] 784980
|
||||
GETS [0 ] 0
|
||||
PUTX [607852 ] 607852
|
||||
PUTX_NotOwner [2614 ] 2614
|
||||
PUTX [604378 ] 604378
|
||||
PUTX_NotOwner [2603 ] 2603
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [607869 ] 607869
|
||||
Memory_Ack [607828 ] 607828
|
||||
Memory_Data [604396 ] 604396
|
||||
Memory_Ack [604362 ] 604362
|
||||
|
||||
- Transitions -
|
||||
I GETX [607884 ] 607884
|
||||
I GETX [604409 ] 604409
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [8255 ] 8255
|
||||
M PUTX [607852 ] 607852
|
||||
M PUTX_NotOwner [2614 ] 2614
|
||||
M GETX [8156 ] 8156
|
||||
M PUTX [604378 ] 604378
|
||||
M PUTX_NotOwner [2603 ] 2603
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
|
|
@ -428,21 +428,21 @@ M_DWRI Memory_Ack [0 ] 0
|
|||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [65216 ] 65216
|
||||
IM GETX [64832 ] 64832
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [607869 ] 607869
|
||||
IM Memory_Data [604396 ] 604396
|
||||
|
||||
MI GETX [104993 ] 104993
|
||||
MI GETX [107583 ] 107583
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [607828 ] 607828
|
||||
MI Memory_Ack [604362 ] 604362
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
|
|
|
|||
|
|
@ -1,74 +1,82 @@
|
|||
system.cpu0: completed 10000 read, 5375 write accesses @856398
|
||||
system.cpu7: completed 10000 read, 5367 write accesses @862743
|
||||
system.cpu4: completed 10000 read, 5441 write accesses @863378
|
||||
system.cpu5: completed 10000 read, 5493 write accesses @863384
|
||||
system.cpu6: completed 10000 read, 5390 write accesses @871145
|
||||
system.cpu2: completed 10000 read, 5481 write accesses @872080
|
||||
system.cpu3: completed 10000 read, 5307 write accesses @887641
|
||||
system.cpu1: completed 10000 read, 5435 write accesses @888236
|
||||
system.cpu0: completed 20000 read, 10720 write accesses @1697024
|
||||
system.cpu4: completed 20000 read, 10674 write accesses @1708688
|
||||
system.cpu2: completed 20000 read, 10679 write accesses @1718143
|
||||
system.cpu7: completed 20000 read, 10680 write accesses @1726961
|
||||
system.cpu5: completed 20000 read, 10844 write accesses @1731599
|
||||
system.cpu6: completed 20000 read, 10755 write accesses @1744688
|
||||
system.cpu1: completed 20000 read, 10834 write accesses @1760840
|
||||
system.cpu3: completed 20000 read, 10861 write accesses @1783274
|
||||
system.cpu0: completed 30000 read, 16096 write accesses @2576060
|
||||
system.cpu7: completed 30000 read, 16150 write accesses @2587892
|
||||
system.cpu2: completed 30000 read, 16059 write accesses @2589422
|
||||
system.cpu4: completed 30000 read, 16216 write accesses @2589611
|
||||
system.cpu5: completed 30000 read, 16311 write accesses @2606290
|
||||
system.cpu1: completed 30000 read, 16085 write accesses @2614280
|
||||
system.cpu6: completed 30000 read, 16250 write accesses @2617742
|
||||
system.cpu3: completed 30000 read, 16179 write accesses @2640821
|
||||
system.cpu0: completed 40000 read, 21491 write accesses @3463636
|
||||
system.cpu5: completed 40000 read, 21654 write accesses @3466586
|
||||
system.cpu4: completed 40000 read, 21608 write accesses @3466694
|
||||
system.cpu6: completed 40000 read, 21630 write accesses @3468467
|
||||
system.cpu2: completed 40000 read, 21509 write accesses @3470109
|
||||
system.cpu7: completed 40000 read, 21495 write accesses @3471086
|
||||
system.cpu1: completed 40000 read, 21461 write accesses @3476351
|
||||
system.cpu3: completed 40000 read, 21515 write accesses @3523754
|
||||
system.cpu4: completed 50000 read, 27063 write accesses @4330388
|
||||
system.cpu6: completed 50000 read, 27077 write accesses @4332246
|
||||
system.cpu5: completed 50000 read, 27022 write accesses @4334407
|
||||
system.cpu1: completed 50000 read, 26821 write accesses @4334861
|
||||
system.cpu2: completed 50000 read, 27005 write accesses @4339007
|
||||
system.cpu0: completed 50000 read, 27011 write accesses @4351000
|
||||
system.cpu7: completed 50000 read, 27023 write accesses @4371905
|
||||
system.cpu3: completed 50000 read, 26894 write accesses @4421954
|
||||
system.cpu6: completed 60000 read, 32380 write accesses @5185697
|
||||
system.cpu2: completed 60000 read, 32320 write accesses @5197049
|
||||
system.cpu1: completed 60000 read, 32167 write accesses @5197304
|
||||
system.cpu4: completed 60000 read, 32460 write accesses @5201909
|
||||
system.cpu5: completed 60000 read, 32453 write accesses @5222405
|
||||
system.cpu0: completed 60000 read, 32443 write accesses @5224148
|
||||
system.cpu7: completed 60000 read, 32400 write accesses @5229110
|
||||
system.cpu3: completed 60000 read, 32209 write accesses @5281507
|
||||
system.cpu6: completed 70000 read, 37664 write accesses @6045459
|
||||
system.cpu4: completed 70000 read, 37836 write accesses @6058226
|
||||
system.cpu1: completed 70000 read, 37476 write accesses @6063535
|
||||
system.cpu2: completed 70000 read, 37820 write accesses @6074654
|
||||
system.cpu5: completed 70000 read, 37785 write accesses @6097069
|
||||
system.cpu7: completed 70000 read, 37611 write accesses @6097865
|
||||
system.cpu0: completed 70000 read, 37769 write accesses @6104873
|
||||
system.cpu3: completed 70000 read, 37585 write accesses @6142157
|
||||
system.cpu4: completed 80000 read, 43086 write accesses @6914689
|
||||
system.cpu6: completed 80000 read, 42941 write accesses @6923107
|
||||
system.cpu1: completed 80000 read, 42761 write accesses @6929131
|
||||
system.cpu2: completed 80000 read, 43045 write accesses @6933740
|
||||
system.cpu5: completed 80000 read, 43067 write accesses @6962084
|
||||
system.cpu7: completed 80000 read, 43014 write accesses @6974408
|
||||
system.cpu0: completed 80000 read, 43066 write accesses @6974987
|
||||
system.cpu3: completed 80000 read, 43041 write accesses @7015199
|
||||
system.cpu4: completed 90000 read, 48630 write accesses @7775720
|
||||
system.cpu1: completed 90000 read, 48156 write accesses @7793810
|
||||
system.cpu6: completed 90000 read, 48441 write accesses @7801463
|
||||
system.cpu2: completed 90000 read, 48518 write accesses @7804520
|
||||
system.cpu5: completed 90000 read, 48378 write accesses @7834475
|
||||
system.cpu0: completed 90000 read, 48500 write accesses @7849400
|
||||
system.cpu7: completed 90000 read, 48425 write accesses @7864016
|
||||
system.cpu3: completed 90000 read, 48443 write accesses @7889702
|
||||
system.cpu4: completed 100000 read, 54108 write accesses @8642753
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu4: completed 10000 read, 5220 write accesses @847627
|
||||
system.cpu7: completed 10000 read, 5333 write accesses @853307
|
||||
system.cpu1: completed 10000 read, 5223 write accesses @856720
|
||||
system.cpu2: completed 10000 read, 5343 write accesses @856757
|
||||
system.cpu0: completed 10000 read, 5346 write accesses @859240
|
||||
system.cpu3: completed 10000 read, 5325 write accesses @862609
|
||||
system.cpu5: completed 10000 read, 5417 write accesses @867929
|
||||
system.cpu6: completed 10000 read, 5429 write accesses @870556
|
||||
system.cpu7: completed 20000 read, 10546 write accesses @1710362
|
||||
system.cpu3: completed 20000 read, 10676 write accesses @1715625
|
||||
system.cpu2: completed 20000 read, 10865 write accesses @1717913
|
||||
system.cpu1: completed 20000 read, 10472 write accesses @1718245
|
||||
system.cpu4: completed 20000 read, 10710 write accesses @1723388
|
||||
system.cpu0: completed 20000 read, 10695 write accesses @1731500
|
||||
system.cpu6: completed 20000 read, 10923 write accesses @1732721
|
||||
system.cpu5: completed 20000 read, 10714 write accesses @1741949
|
||||
system.cpu3: completed 30000 read, 16111 write accesses @2561534
|
||||
system.cpu7: completed 30000 read, 15801 write accesses @2564909
|
||||
system.cpu0: completed 30000 read, 15963 write accesses @2570530
|
||||
system.cpu2: completed 30000 read, 16167 write accesses @2572444
|
||||
system.cpu4: completed 30000 read, 16049 write accesses @2589273
|
||||
system.cpu6: completed 30000 read, 16204 write accesses @2590810
|
||||
system.cpu5: completed 30000 read, 15952 write accesses @2600828
|
||||
system.cpu1: completed 30000 read, 15999 write accesses @2614055
|
||||
system.cpu7: completed 40000 read, 21145 write accesses @3411914
|
||||
system.cpu0: completed 40000 read, 21350 write accesses @3420253
|
||||
system.cpu2: completed 40000 read, 21529 write accesses @3428587
|
||||
system.cpu3: completed 40000 read, 21460 write accesses @3434840
|
||||
system.cpu6: completed 40000 read, 21523 write accesses @3443024
|
||||
system.cpu4: completed 40000 read, 21533 write accesses @3467265
|
||||
system.cpu5: completed 40000 read, 21305 write accesses @3470138
|
||||
system.cpu1: completed 40000 read, 21461 write accesses @3492145
|
||||
system.cpu7: completed 50000 read, 26466 write accesses @4272276
|
||||
system.cpu2: completed 50000 read, 26738 write accesses @4280117
|
||||
system.cpu0: completed 50000 read, 26773 write accesses @4295924
|
||||
system.cpu6: completed 50000 read, 26837 write accesses @4299550
|
||||
system.cpu3: completed 50000 read, 26845 write accesses @4312607
|
||||
system.cpu5: completed 50000 read, 26698 write accesses @4316933
|
||||
system.cpu4: completed 50000 read, 26954 write accesses @4344468
|
||||
system.cpu1: completed 50000 read, 26769 write accesses @4358867
|
||||
system.cpu7: completed 60000 read, 31755 write accesses @5113250
|
||||
system.cpu0: completed 60000 read, 32149 write accesses @5156117
|
||||
system.cpu2: completed 60000 read, 32096 write accesses @5160599
|
||||
system.cpu6: completed 60000 read, 32168 write accesses @5173313
|
||||
system.cpu3: completed 60000 read, 32243 write accesses @5178563
|
||||
system.cpu5: completed 60000 read, 32247 write accesses @5183771
|
||||
system.cpu4: completed 60000 read, 32381 write accesses @5220290
|
||||
system.cpu1: completed 60000 read, 32294 write accesses @5220865
|
||||
system.cpu7: completed 70000 read, 37125 write accesses @5977718
|
||||
system.cpu0: completed 70000 read, 37636 write accesses @6026353
|
||||
system.cpu6: completed 70000 read, 37517 write accesses @6027404
|
||||
system.cpu2: completed 70000 read, 37549 write accesses @6039275
|
||||
system.cpu3: completed 70000 read, 37632 write accesses @6040322
|
||||
system.cpu5: completed 70000 read, 37704 write accesses @6061913
|
||||
system.cpu1: completed 70000 read, 37680 write accesses @6066326
|
||||
system.cpu4: completed 70000 read, 37794 write accesses @6080683
|
||||
system.cpu7: completed 80000 read, 42401 write accesses @6837718
|
||||
system.cpu0: completed 80000 read, 43037 write accesses @6872986
|
||||
system.cpu6: completed 80000 read, 42861 write accesses @6886837
|
||||
system.cpu3: completed 80000 read, 43022 write accesses @6895964
|
||||
system.cpu2: completed 80000 read, 43017 write accesses @6904754
|
||||
system.cpu5: completed 80000 read, 43129 write accesses @6910157
|
||||
system.cpu1: completed 80000 read, 42955 write accesses @6929917
|
||||
system.cpu4: completed 80000 read, 43333 write accesses @6955798
|
||||
system.cpu7: completed 90000 read, 47777 write accesses @7715699
|
||||
system.cpu0: completed 90000 read, 48512 write accesses @7730512
|
||||
system.cpu6: completed 90000 read, 48227 write accesses @7747760
|
||||
system.cpu1: completed 90000 read, 48224 write accesses @7775090
|
||||
system.cpu2: completed 90000 read, 48474 write accesses @7775105
|
||||
system.cpu3: completed 90000 read, 48528 write accesses @7778761
|
||||
system.cpu5: completed 90000 read, 48627 write accesses @7786116
|
||||
system.cpu4: completed 90000 read, 48988 write accesses @7814863
|
||||
system.cpu7: completed 100000 read, 53297 write accesses @8594451
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.008643 # Number of seconds simulated
|
||||
sim_ticks 8642753 # Number of ticks simulated
|
||||
final_tick 8642753 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.008594 # Number of seconds simulated
|
||||
sim_ticks 8594451 # Number of ticks simulated
|
||||
final_tick 8594451 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 200801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 409268 # Number of bytes of host memory used
|
||||
host_seconds 43.04 # Real time elapsed on the host
|
||||
host_tick_rate 108749 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418376 # Number of bytes of host memory used
|
||||
host_seconds 79.03 # Real time elapsed on the host
|
||||
system.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
|
@ -55,29 +55,29 @@ system.l1_cntrl3.cacheMemory.num_tag_array_reads 0
|
|||
system.l1_cntrl3.cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l1_cntrl3.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l1_cntrl3.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99336 # number of read accesses completed
|
||||
system.cpu0.num_writes 53454 # number of write accesses completed
|
||||
system.cpu0.num_reads 99932 # number of read accesses completed
|
||||
system.cpu0.num_writes 53945 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99686 # number of read accesses completed
|
||||
system.cpu1.num_writes 53261 # number of write accesses completed
|
||||
system.cpu1.num_reads 99540 # number of read accesses completed
|
||||
system.cpu1.num_writes 53424 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99694 # number of read accesses completed
|
||||
system.cpu2.num_writes 53721 # number of write accesses completed
|
||||
system.cpu2.num_reads 99404 # number of read accesses completed
|
||||
system.cpu2.num_writes 53533 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 98699 # number of read accesses completed
|
||||
system.cpu3.num_writes 53080 # number of write accesses completed
|
||||
system.cpu3.num_reads 99305 # number of read accesses completed
|
||||
system.cpu3.num_writes 53683 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 100000 # number of read accesses completed
|
||||
system.cpu4.num_writes 54108 # number of write accesses completed
|
||||
system.cpu4.num_reads 99222 # number of read accesses completed
|
||||
system.cpu4.num_writes 53970 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99065 # number of read accesses completed
|
||||
system.cpu5.num_writes 53284 # number of write accesses completed
|
||||
system.cpu5.num_reads 99453 # number of read accesses completed
|
||||
system.cpu5.num_writes 53665 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99678 # number of read accesses completed
|
||||
system.cpu6.num_writes 53683 # number of write accesses completed
|
||||
system.cpu6.num_reads 99859 # number of read accesses completed
|
||||
system.cpu6.num_writes 53616 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 98986 # number of read accesses completed
|
||||
system.cpu7.num_writes 53291 # number of write accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 53297 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,74 +1,74 @@
|
|||
system.cpu1: completed 10000 read, 5306 write accesses @32059956
|
||||
system.cpu6: completed 10000 read, 5293 write accesses @32275139
|
||||
system.cpu7: completed 10000 read, 5474 write accesses @32325344
|
||||
system.cpu3: completed 10000 read, 5220 write accesses @32355571
|
||||
system.cpu2: completed 10000 read, 5392 write accesses @32378350
|
||||
system.cpu4: completed 10000 read, 5411 write accesses @32427761
|
||||
system.cpu5: completed 10000 read, 5317 write accesses @32754271
|
||||
system.cpu0: completed 10000 read, 5539 write accesses @32833317
|
||||
system.cpu1: completed 20000 read, 10662 write accesses @55871338
|
||||
system.cpu3: completed 20000 read, 10529 write accesses @56061050
|
||||
system.cpu2: completed 20000 read, 10630 write accesses @56140317
|
||||
system.cpu4: completed 20000 read, 10816 write accesses @56432989
|
||||
system.cpu7: completed 20000 read, 10899 write accesses @56513495
|
||||
system.cpu6: completed 20000 read, 10845 write accesses @56565627
|
||||
system.cpu5: completed 20000 read, 10626 write accesses @57072718
|
||||
system.cpu0: completed 20000 read, 11113 write accesses @57586418
|
||||
system.cpu2: completed 30000 read, 16017 write accesses @79407742
|
||||
system.cpu1: completed 30000 read, 16151 write accesses @79725766
|
||||
system.cpu3: completed 30000 read, 15856 write accesses @79754749
|
||||
system.cpu6: completed 30000 read, 16195 write accesses @80206236
|
||||
system.cpu4: completed 30000 read, 16333 write accesses @80758801
|
||||
system.cpu7: completed 30000 read, 16467 write accesses @80845126
|
||||
system.cpu5: completed 30000 read, 16040 write accesses @81280754
|
||||
system.cpu0: completed 30000 read, 16740 write accesses @81836055
|
||||
system.cpu3: completed 40000 read, 21110 write accesses @102187140
|
||||
system.cpu1: completed 40000 read, 21543 write accesses @102788912
|
||||
system.cpu2: completed 40000 read, 21441 write accesses @103129249
|
||||
system.cpu6: completed 40000 read, 21490 write accesses @103224826
|
||||
system.cpu7: completed 40000 read, 21781 write accesses @104248123
|
||||
system.cpu4: completed 40000 read, 21750 write accesses @104259134
|
||||
system.cpu5: completed 40000 read, 21538 write accesses @104623876
|
||||
system.cpu0: completed 40000 read, 22049 write accesses @105025965
|
||||
system.cpu3: completed 50000 read, 26445 write accesses @126560435
|
||||
system.cpu1: completed 50000 read, 27002 write accesses @127296516
|
||||
system.cpu6: completed 50000 read, 26751 write accesses @127652113
|
||||
system.cpu2: completed 50000 read, 26915 write accesses @127863043
|
||||
system.cpu5: completed 50000 read, 26795 write accesses @128758388
|
||||
system.cpu7: completed 50000 read, 27154 write accesses @128837444
|
||||
system.cpu4: completed 50000 read, 27195 write accesses @128884190
|
||||
system.cpu0: completed 50000 read, 27370 write accesses @129107611
|
||||
system.cpu3: completed 60000 read, 31813 write accesses @150500482
|
||||
system.cpu1: completed 60000 read, 32357 write accesses @151324410
|
||||
system.cpu6: completed 60000 read, 32276 write accesses @152241130
|
||||
system.cpu2: completed 60000 read, 32455 write accesses @152510509
|
||||
system.cpu4: completed 60000 read, 32625 write accesses @152799581
|
||||
system.cpu5: completed 60000 read, 32145 write accesses @152911895
|
||||
system.cpu7: completed 60000 read, 32658 write accesses @153053742
|
||||
system.cpu0: completed 60000 read, 32669 write accesses @153243898
|
||||
system.cpu3: completed 70000 read, 37148 write accesses @174290350
|
||||
system.cpu1: completed 70000 read, 37719 write accesses @175320592
|
||||
system.cpu6: completed 70000 read, 37631 write accesses @176658170
|
||||
system.cpu4: completed 70000 read, 37993 write accesses @176957081
|
||||
system.cpu2: completed 70000 read, 37835 write accesses @177152761
|
||||
system.cpu5: completed 70000 read, 37525 write accesses @177243860
|
||||
system.cpu7: completed 70000 read, 38186 write accesses @177800828
|
||||
system.cpu0: completed 70000 read, 38119 write accesses @178467538
|
||||
system.cpu3: completed 80000 read, 42562 write accesses @198146360
|
||||
system.cpu1: completed 80000 read, 43234 write accesses @199454254
|
||||
system.cpu4: completed 80000 read, 43314 write accesses @200406450
|
||||
system.cpu5: completed 80000 read, 42980 write accesses @200646810
|
||||
system.cpu2: completed 80000 read, 43306 write accesses @200927158
|
||||
system.cpu6: completed 80000 read, 43086 write accesses @200956315
|
||||
system.cpu7: completed 80000 read, 43539 write accesses @201412026
|
||||
system.cpu0: completed 80000 read, 43547 write accesses @202267757
|
||||
system.cpu3: completed 90000 read, 47828 write accesses @222074356
|
||||
system.cpu1: completed 90000 read, 48627 write accesses @223900144
|
||||
system.cpu5: completed 90000 read, 48291 write accesses @224840552
|
||||
system.cpu4: completed 90000 read, 48802 write accesses @224884716
|
||||
system.cpu6: completed 90000 read, 48479 write accesses @224938254
|
||||
system.cpu2: completed 90000 read, 48708 write accesses @225566271
|
||||
system.cpu7: completed 90000 read, 48770 write accesses @225725770
|
||||
system.cpu0: completed 90000 read, 48880 write accesses @226596871
|
||||
system.cpu3: completed 100000 read, 53214 write accesses @246648467
|
||||
system.cpu0: completed 10000 read, 5290 write accesses @74885500
|
||||
system.cpu7: completed 10000 read, 5447 write accesses @78072500
|
||||
system.cpu2: completed 10000 read, 5330 write accesses @78536500
|
||||
system.cpu5: completed 10000 read, 5401 write accesses @79479500
|
||||
system.cpu3: completed 10000 read, 5406 write accesses @80479500
|
||||
system.cpu1: completed 10000 read, 5452 write accesses @80823500
|
||||
system.cpu4: completed 10000 read, 5330 write accesses @82914500
|
||||
system.cpu6: completed 10000 read, 5363 write accesses @83627000
|
||||
system.cpu7: completed 20000 read, 10668 write accesses @150917000
|
||||
system.cpu0: completed 20000 read, 10683 write accesses @151253500
|
||||
system.cpu5: completed 20000 read, 10718 write accesses @151911500
|
||||
system.cpu2: completed 20000 read, 10688 write accesses @152119000
|
||||
system.cpu3: completed 20000 read, 10954 write accesses @159391000
|
||||
system.cpu6: completed 20000 read, 10780 write accesses @160278500
|
||||
system.cpu1: completed 20000 read, 10888 write accesses @160835000
|
||||
system.cpu4: completed 20000 read, 10745 write accesses @162137000
|
||||
system.cpu2: completed 30000 read, 16060 write accesses @225600500
|
||||
system.cpu0: completed 30000 read, 16073 write accesses @226217000
|
||||
system.cpu7: completed 30000 read, 15898 write accesses @227550500
|
||||
system.cpu5: completed 30000 read, 16102 write accesses @230201000
|
||||
system.cpu3: completed 30000 read, 16375 write accesses @233880500
|
||||
system.cpu1: completed 30000 read, 16184 write accesses @234964500
|
||||
system.cpu6: completed 30000 read, 16132 write accesses @236785500
|
||||
system.cpu4: completed 30000 read, 16103 write accesses @242571500
|
||||
system.cpu7: completed 40000 read, 21206 write accesses @298942500
|
||||
system.cpu2: completed 40000 read, 21441 write accesses @299465500
|
||||
system.cpu0: completed 40000 read, 21388 write accesses @302202500
|
||||
system.cpu5: completed 40000 read, 21578 write accesses @308632000
|
||||
system.cpu6: completed 40000 read, 21492 write accesses @314697500
|
||||
system.cpu3: completed 40000 read, 22088 write accesses @315960000
|
||||
system.cpu4: completed 40000 read, 21590 write accesses @317147500
|
||||
system.cpu1: completed 40000 read, 21566 write accesses @317423500
|
||||
system.cpu7: completed 50000 read, 26570 write accesses @373251000
|
||||
system.cpu2: completed 50000 read, 26788 write accesses @373919000
|
||||
system.cpu0: completed 50000 read, 26897 write accesses @382805000
|
||||
system.cpu5: completed 50000 read, 27003 write accesses @384437500
|
||||
system.cpu3: completed 50000 read, 27349 write accesses @389623000
|
||||
system.cpu4: completed 50000 read, 26792 write accesses @389830500
|
||||
system.cpu6: completed 50000 read, 27002 write accesses @392270000
|
||||
system.cpu1: completed 50000 read, 26853 write accesses @392392000
|
||||
system.cpu7: completed 60000 read, 31855 write accesses @449936000
|
||||
system.cpu2: completed 60000 read, 32201 write accesses @452901500
|
||||
system.cpu0: completed 60000 read, 32209 write accesses @457331000
|
||||
system.cpu5: completed 60000 read, 32356 write accesses @458864500
|
||||
system.cpu4: completed 60000 read, 32204 write accesses @464577500
|
||||
system.cpu3: completed 60000 read, 32813 write accesses @468126500
|
||||
system.cpu6: completed 60000 read, 32463 write accesses @469913500
|
||||
system.cpu1: completed 60000 read, 32376 write accesses @472262000
|
||||
system.cpu7: completed 70000 read, 37203 write accesses @526760000
|
||||
system.cpu2: completed 70000 read, 37525 write accesses @530661000
|
||||
system.cpu5: completed 70000 read, 37749 write accesses @533141500
|
||||
system.cpu0: completed 70000 read, 37615 write accesses @537691500
|
||||
system.cpu3: completed 70000 read, 38216 write accesses @538787500
|
||||
system.cpu4: completed 70000 read, 37614 write accesses @545810500
|
||||
system.cpu6: completed 70000 read, 37722 write accesses @546307000
|
||||
system.cpu1: completed 70000 read, 37746 write accesses @546660500
|
||||
system.cpu7: completed 80000 read, 42460 write accesses @600681000
|
||||
system.cpu5: completed 80000 read, 42949 write accesses @604308500
|
||||
system.cpu2: completed 80000 read, 42841 write accesses @606628000
|
||||
system.cpu0: completed 80000 read, 43072 write accesses @615043500
|
||||
system.cpu3: completed 80000 read, 43808 write accesses @615907000
|
||||
system.cpu4: completed 80000 read, 43047 write accesses @622672500
|
||||
system.cpu6: completed 80000 read, 43213 write accesses @622720000
|
||||
system.cpu1: completed 80000 read, 43140 write accesses @626035000
|
||||
system.cpu2: completed 90000 read, 48140 write accesses @675974000
|
||||
system.cpu7: completed 90000 read, 48058 write accesses @680921000
|
||||
system.cpu5: completed 90000 read, 48486 write accesses @683376500
|
||||
system.cpu3: completed 90000 read, 49174 write accesses @687533500
|
||||
system.cpu0: completed 90000 read, 48447 write accesses @690023000
|
||||
system.cpu6: completed 90000 read, 48621 write accesses @702298000
|
||||
system.cpu4: completed 90000 read, 48429 write accesses @703717000
|
||||
system.cpu1: completed 90000 read, 48600 write accesses @705675000
|
||||
system.cpu2: completed 100000 read, 53454 write accesses @753126500
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 2 2012 08:30:56
|
||||
gem5 started Jul 2 2012 09:08:41
|
||||
gem5 executing on zizzer
|
||||
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest
|
||||
gem5 compiled Oct 15 2012 19:23:25
|
||||
gem5 started Oct 15 2012 19:23:52
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 223713460 because maximum number of loads reached
|
||||
Exiting @ tick 753126500 because maximum number of loads reached
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue