tests: Always specify memory mode in every test system.

Previous to this change we didn't always set the memory mode which worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs verify
that they're operating in the correct mode and thus we need to always set it.
This commit is contained in:
Ali Saidi 2013-01-07 13:05:33 -05:00
parent f32f372455
commit 90bd20aae2
7 changed files with 16 additions and 7 deletions

View file

@ -40,7 +40,8 @@ cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = SimpleDRAM(),
membus = CoherentBus())
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller

View file

@ -53,7 +53,8 @@ cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = SimpleDRAM(),
membus = CoherentBus())
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)

View file

@ -38,7 +38,8 @@ import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
mem_mode = "timing")
for cpu in cpus:
# create the interrupt controller

View file

@ -35,7 +35,10 @@ nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
system = System(cpu = cpus,
physmem = SimpleDRAM(),
membus = CoherentBus(),
mem_mode = "timing")
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')

View file

@ -40,7 +40,8 @@ cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = ruby_memory,
membus = CoherentBus())
membus = CoherentBus(),
mem_mode = "timing")
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()

View file

@ -42,7 +42,8 @@ cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = SimpleDRAM(),
membus = CoherentBus())
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller

View file

@ -37,7 +37,8 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
L2Cache(size = '2MB'))
system = System(cpu = cpu,
physmem = SimpleMemory(),
membus = CoherentBus())
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller