diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index baeab677a..a92c61ba1 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -40,7 +40,8 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleDRAM(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index a4dddb08f..a33a2ac06 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -53,7 +53,8 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleDRAM(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 cpu.connectAllPorts(system.membus)
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 9bdef5eef..126e71ed5 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -38,7 +38,8 @@ import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
+                mem_mode = "timing")
 
 for cpu in cpus:
     # create the interrupt controller
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 6f3bddc6f..c3a4929bb 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -35,7 +35,10 @@ nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
+system = System(cpu = cpus,
+                physmem = SimpleDRAM(),
+                membus = CoherentBus(),
+                mem_mode = "timing")
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index a45939f36..26dbb000b 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -40,7 +40,8 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = ruby_memory,
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.physmem.port = system.membus.master
 # create the interrupt controller
 cpu.createInterruptController()
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 30c2f413e..474d13902 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -42,7 +42,8 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleDRAM(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 5a851ba25..b366f01e5 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -37,7 +37,8 @@ cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
                               L2Cache(size = '2MB'))
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
-                membus = CoherentBus())
+                membus = CoherentBus(),
+                mem_mode = "timing")
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller