Andreas Hansson 3cf733bcc0 Regression: Use addTwoLevelCacheHierarchy in configs ... This patch unifies the full-system regression config scripts and uses the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up the L1s and L2, and create the bus inbetween. The patch is a step on the way to use the clock period to express the cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2 bus, and these modules thus use the CPU clock. The patch does not change the value of any stats, but plenty names, and a follow-up patch contains the update to the stats, chaning system.l2c to system.cpu.l2cache.		2012-10-15 08:07:09 -04:00
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configs	Regression: Use addTwoLevelCacheHierarchy in configs	2012-10-15 08:07:09 -04:00
long	Regression Tests: Update statistics	2012-10-02 14:35:46 -05:00
quick	Regression Tests: Update statistics	2012-10-02 14:35:46 -05:00
test-progs/hello	X86: Add a 32 bit hello world test binary.	2012-05-27 19:01:09 -07:00
diff-out	tests: fix diff-out script for op/inst stat changes.	2012-02-12 18:35:59 -06:00
halt.sh	Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.	2006-07-21 15:56:35 -04:00
run.py	SE/FS: Make both SE and FS tests available all the time.	2012-01-28 07:24:45 -08:00
SConscript	SimpleDRAM: A basic SimpleDRAM regression	2012-09-21 11:48:14 -04:00