Andreas Hansson 88554790c3 Mem: Use cycles to express cache-related latencies ... This patch changes the cache-related latencies from an absolute time expressed in Ticks, to a number of cycles that can be scaled with the clock period of the caches. Ultimately this patch serves to enable future work that involves dynamic frequency scaling. As an immediate benefit it also makes it more convenient to specify cache performance without implicitly assuming a specific CPU core operating frequency. The stat blocked_cycles that actually counter in ticks is now updated to count in cycles. As the timing is now rounded to the clock edges of the cache, there are some regressions that change. Plenty of them have very minor changes, whereas some regressions with a short run-time are perturbed quite significantly. A follow-on patch updates all the statistics for the regressions.		2012-10-15 08:10:54 -04:00
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configs	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
long	Stats: Update stats for new default L1-to-L2 bus clock and width	2012-10-15 08:09:54 -04:00
quick	Stats: Update memtest stats after setting clock	2012-10-15 08:10:52 -04:00
test-progs/hello	X86: Add a 32 bit hello world test binary.	2012-05-27 19:01:09 -07:00
diff-out	tests: fix diff-out script for op/inst stat changes.	2012-02-12 18:35:59 -06:00
halt.sh	Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.	2006-07-21 15:56:35 -04:00
run.py	SE/FS: Make both SE and FS tests available all the time.	2012-01-28 07:24:45 -08:00
SConscript	SimpleDRAM: A basic SimpleDRAM regression	2012-09-21 11:48:14 -04:00