Andreas Hansson 88554790c3 Mem: Use cycles to express cache-related latencies ... This patch changes the cache-related latencies from an absolute time expressed in Ticks, to a number of cycles that can be scaled with the clock period of the caches. Ultimately this patch serves to enable future work that involves dynamic frequency scaling. As an immediate benefit it also makes it more convenient to specify cache performance without implicitly assuming a specific CPU core operating frequency. The stat blocked_cycles that actually counter in ticks is now updated to count in cycles. As the timing is now rounded to the clock edges of the cache, there are some regressions that change. Plenty of them have very minor changes, whereas some regressions with a short run-time are perturbed quite significantly. A follow-on patch updates all the statistics for the regressions.		2012-10-15 08:10:54 -04:00
..
inorder-timing.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
memtest-ruby.py	Configs: Set the memtest clock to a reasonable value	2012-10-15 08:09:57 -04:00
memtest.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
o3-timing-checker.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
o3-timing-mp-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
o3-timing-mp.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
o3-timing-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
o3-timing.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
pc-o3-timing.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
pc-simple-atomic.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
pc-simple-timing-ruby.py	Regression: Fix topologies path in failing pc-simple-timing-ruby	2012-07-21 17:24:01 -04:00
pc-simple-timing.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
realview-o3-checker.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
realview-o3-dual.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
realview-o3.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
realview-simple-atomic-dual.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
realview-simple-atomic.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
realview-simple-timing-dual.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
realview-simple-timing.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
rubytest-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
simple-atomic-dummychecker.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
simple-atomic-mp-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
simple-atomic-mp.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
simple-atomic.py	Bus: Split the bus into a non-coherent and coherent bus	2012-05-31 13:30:04 -04:00
simple-timing-mp-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
simple-timing-mp.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
simple-timing-ruby.py	regress: ruby stat additions and config changes	2012-07-10 22:51:55 -07:00
simple-timing.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
t1000-simple-atomic.py	Fix the SPARC fs regression by adding a call to createInterruptController.	2012-03-08 02:10:03 -08:00
tgen-simple-dram.py	SimpleDRAM: A basic SimpleDRAM regression	2012-09-21 11:48:14 -04:00
tgen-simple-mem.py	TrafficGen: Add a basic traffic generator regression	2012-09-21 11:48:11 -04:00
tsunami-inorder.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
tsunami-o3-dual.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
tsunami-o3.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
tsunami-simple-atomic-dual.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
tsunami-simple-atomic.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
tsunami-simple-timing-dual.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
tsunami-simple-timing.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
twosys-tsunami-simple-atomic.py	Regression: Set the clock for twosys-tsunami CPUs	2012-09-24 18:03:41 -04:00