regressions: stats update due to ruby functional access patch
This commit is contained in:
parent
90c45c29fe
commit
2680c827be
25 changed files with 2393 additions and 2391 deletions
|
@ -198,7 +198,7 @@ version=0
|
|||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
@ -286,7 +286,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -350,7 +350,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -414,7 +414,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -478,7 +478,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -542,7 +542,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -606,7 +606,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -670,7 +670,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -734,7 +734,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -6,77 +6,77 @@ Warning: rounding error > tolerance
|
|||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu3: completed 10000 read, 5404 write accesses @717450
|
||||
system.cpu1: completed 10000 read, 5196 write accesses @724437
|
||||
system.cpu2: completed 10000 read, 5343 write accesses @725385
|
||||
system.cpu6: completed 10000 read, 5334 write accesses @727920
|
||||
system.cpu7: completed 10000 read, 5409 write accesses @729342
|
||||
system.cpu4: completed 10000 read, 5518 write accesses @734970
|
||||
system.cpu5: completed 10000 read, 5427 write accesses @742533
|
||||
system.cpu0: completed 10000 read, 5369 write accesses @745215
|
||||
system.cpu3: completed 20000 read, 10663 write accesses @1450297
|
||||
system.cpu1: completed 20000 read, 10544 write accesses @1453395
|
||||
system.cpu2: completed 20000 read, 10794 write accesses @1458916
|
||||
system.cpu4: completed 20000 read, 10867 write accesses @1467543
|
||||
system.cpu7: completed 20000 read, 11024 write accesses @1468498
|
||||
system.cpu5: completed 20000 read, 10707 write accesses @1475684
|
||||
system.cpu6: completed 20000 read, 10882 write accesses @1478874
|
||||
system.cpu0: completed 20000 read, 10682 write accesses @1482396
|
||||
system.cpu2: completed 30000 read, 16135 write accesses @2180653
|
||||
system.cpu6: completed 30000 read, 16248 write accesses @2190702
|
||||
system.cpu0: completed 30000 read, 15981 write accesses @2193064
|
||||
system.cpu7: completed 30000 read, 16551 write accesses @2194713
|
||||
system.cpu1: completed 30000 read, 16114 write accesses @2197452
|
||||
system.cpu4: completed 30000 read, 16285 write accesses @2201477
|
||||
system.cpu3: completed 30000 read, 16078 write accesses @2211153
|
||||
system.cpu5: completed 30000 read, 15971 write accesses @2223483
|
||||
system.cpu6: completed 40000 read, 21540 write accesses @2894242
|
||||
system.cpu2: completed 40000 read, 21379 write accesses @2909918
|
||||
system.cpu0: completed 40000 read, 21281 write accesses @2925069
|
||||
system.cpu7: completed 40000 read, 21971 write accesses @2926047
|
||||
system.cpu1: completed 40000 read, 21533 write accesses @2926905
|
||||
system.cpu4: completed 40000 read, 21566 write accesses @2928243
|
||||
system.cpu3: completed 40000 read, 21457 write accesses @2944482
|
||||
system.cpu5: completed 40000 read, 21433 write accesses @2971421
|
||||
system.cpu6: completed 50000 read, 26804 write accesses @3631185
|
||||
system.cpu2: completed 50000 read, 26805 write accesses @3647917
|
||||
system.cpu1: completed 50000 read, 26966 write accesses @3648934
|
||||
system.cpu0: completed 50000 read, 26609 write accesses @3651975
|
||||
system.cpu4: completed 50000 read, 26920 write accesses @3663191
|
||||
system.cpu7: completed 50000 read, 27389 write accesses @3665118
|
||||
system.cpu3: completed 50000 read, 26923 write accesses @3682505
|
||||
system.cpu5: completed 50000 read, 26907 write accesses @3699503
|
||||
system.cpu6: completed 60000 read, 31950 write accesses @4347584
|
||||
system.cpu0: completed 60000 read, 31929 write accesses @4376408
|
||||
system.cpu4: completed 60000 read, 32384 write accesses @4384804
|
||||
system.cpu1: completed 60000 read, 32291 write accesses @4390260
|
||||
system.cpu2: completed 60000 read, 32255 write accesses @4393199
|
||||
system.cpu7: completed 60000 read, 32753 write accesses @4398494
|
||||
system.cpu3: completed 60000 read, 32296 write accesses @4430205
|
||||
system.cpu5: completed 60000 read, 32304 write accesses @4433476
|
||||
system.cpu6: completed 70000 read, 37197 write accesses @5062593
|
||||
system.cpu0: completed 70000 read, 37408 write accesses @5107223
|
||||
system.cpu4: completed 70000 read, 37809 write accesses @5113784
|
||||
system.cpu7: completed 70000 read, 38017 write accesses @5123354
|
||||
system.cpu1: completed 70000 read, 37773 write accesses @5127282
|
||||
system.cpu2: completed 70000 read, 37716 write accesses @5127504
|
||||
system.cpu5: completed 70000 read, 37617 write accesses @5160933
|
||||
system.cpu3: completed 70000 read, 37758 write accesses @5167879
|
||||
system.cpu6: completed 80000 read, 42553 write accesses @5789514
|
||||
system.cpu7: completed 80000 read, 43160 write accesses @5844814
|
||||
system.cpu4: completed 80000 read, 43182 write accesses @5848125
|
||||
system.cpu0: completed 80000 read, 43046 write accesses @5851383
|
||||
system.cpu2: completed 80000 read, 42995 write accesses @5852199
|
||||
system.cpu1: completed 80000 read, 43208 write accesses @5860776
|
||||
system.cpu5: completed 80000 read, 43003 write accesses @5898048
|
||||
system.cpu3: completed 80000 read, 43420 write accesses @5900131
|
||||
system.cpu6: completed 90000 read, 47840 write accesses @6504240
|
||||
system.cpu7: completed 90000 read, 48495 write accesses @6570600
|
||||
system.cpu2: completed 90000 read, 48384 write accesses @6574765
|
||||
system.cpu0: completed 90000 read, 48489 write accesses @6585072
|
||||
system.cpu4: completed 90000 read, 48555 write accesses @6585987
|
||||
system.cpu1: completed 90000 read, 48451 write accesses @6586255
|
||||
system.cpu5: completed 90000 read, 48304 write accesses @6624686
|
||||
system.cpu3: completed 90000 read, 48748 write accesses @6638587
|
||||
system.cpu6: completed 100000 read, 53283 write accesses @7241726
|
||||
system.cpu3: completed 10000 read, 5414 write accesses @719275
|
||||
system.cpu1: completed 10000 read, 5207 write accesses @725827
|
||||
system.cpu2: completed 10000 read, 5346 write accesses @726254
|
||||
system.cpu6: completed 10000 read, 5345 write accesses @729597
|
||||
system.cpu7: completed 10000 read, 5419 write accesses @731574
|
||||
system.cpu4: completed 10000 read, 5529 write accesses @736931
|
||||
system.cpu5: completed 10000 read, 5440 write accesses @744470
|
||||
system.cpu0: completed 10000 read, 5379 write accesses @746243
|
||||
system.cpu3: completed 20000 read, 10692 write accesses @1453209
|
||||
system.cpu1: completed 20000 read, 10572 write accesses @1457166
|
||||
system.cpu2: completed 20000 read, 10817 write accesses @1460941
|
||||
system.cpu7: completed 20000 read, 11051 write accesses @1471674
|
||||
system.cpu4: completed 20000 read, 10890 write accesses @1471936
|
||||
system.cpu5: completed 20000 read, 10727 write accesses @1478654
|
||||
system.cpu6: completed 20000 read, 10906 write accesses @1482356
|
||||
system.cpu0: completed 20000 read, 10698 write accesses @1484885
|
||||
system.cpu2: completed 30000 read, 16174 write accesses @2184715
|
||||
system.cpu6: completed 30000 read, 16276 write accesses @2193615
|
||||
system.cpu0: completed 30000 read, 16014 write accesses @2197245
|
||||
system.cpu7: completed 30000 read, 16583 write accesses @2199803
|
||||
system.cpu1: completed 30000 read, 16153 write accesses @2202627
|
||||
system.cpu4: completed 30000 read, 16326 write accesses @2206424
|
||||
system.cpu3: completed 30000 read, 16120 write accesses @2214933
|
||||
system.cpu5: completed 30000 read, 16017 write accesses @2228709
|
||||
system.cpu6: completed 40000 read, 21587 write accesses @2901116
|
||||
system.cpu2: completed 40000 read, 21416 write accesses @2916609
|
||||
system.cpu0: completed 40000 read, 21318 write accesses @2930718
|
||||
system.cpu1: completed 40000 read, 21576 write accesses @2933338
|
||||
system.cpu7: completed 40000 read, 22016 write accesses @2933661
|
||||
system.cpu4: completed 40000 read, 21632 write accesses @2934839
|
||||
system.cpu3: completed 40000 read, 21495 write accesses @2950362
|
||||
system.cpu5: completed 40000 read, 21476 write accesses @2978482
|
||||
system.cpu6: completed 50000 read, 26852 write accesses @3637893
|
||||
system.cpu2: completed 50000 read, 26885 write accesses @3654740
|
||||
system.cpu1: completed 50000 read, 27034 write accesses @3657767
|
||||
system.cpu0: completed 50000 read, 26670 write accesses @3659997
|
||||
system.cpu4: completed 50000 read, 26987 write accesses @3671541
|
||||
system.cpu7: completed 50000 read, 27458 write accesses @3674943
|
||||
system.cpu3: completed 50000 read, 26989 write accesses @3692057
|
||||
system.cpu5: completed 50000 read, 26964 write accesses @3706034
|
||||
system.cpu6: completed 60000 read, 32004 write accesses @4355566
|
||||
system.cpu0: completed 60000 read, 32011 write accesses @4386276
|
||||
system.cpu4: completed 60000 read, 32458 write accesses @4393617
|
||||
system.cpu1: completed 60000 read, 32363 write accesses @4400443
|
||||
system.cpu2: completed 60000 read, 32317 write accesses @4403435
|
||||
system.cpu7: completed 60000 read, 32808 write accesses @4408380
|
||||
system.cpu3: completed 60000 read, 32368 write accesses @4439846
|
||||
system.cpu5: completed 60000 read, 32369 write accesses @4442699
|
||||
system.cpu6: completed 70000 read, 37273 write accesses @5071946
|
||||
system.cpu0: completed 70000 read, 37486 write accesses @5119164
|
||||
system.cpu4: completed 70000 read, 37898 write accesses @5125200
|
||||
system.cpu7: completed 70000 read, 38069 write accesses @5133382
|
||||
system.cpu1: completed 70000 read, 37837 write accesses @5136537
|
||||
system.cpu2: completed 70000 read, 37818 write accesses @5139253
|
||||
system.cpu5: completed 70000 read, 37708 write accesses @5173290
|
||||
system.cpu3: completed 70000 read, 37836 write accesses @5178083
|
||||
system.cpu6: completed 80000 read, 42670 write accesses @5803436
|
||||
system.cpu7: completed 80000 read, 43237 write accesses @5856290
|
||||
system.cpu4: completed 80000 read, 43274 write accesses @5860905
|
||||
system.cpu2: completed 80000 read, 43098 write accesses @5864154
|
||||
system.cpu0: completed 80000 read, 43136 write accesses @5865993
|
||||
system.cpu1: completed 80000 read, 43319 write accesses @5873155
|
||||
system.cpu5: completed 80000 read, 43110 write accesses @5912619
|
||||
system.cpu3: completed 80000 read, 43527 write accesses @5915226
|
||||
system.cpu6: completed 90000 read, 47938 write accesses @6517300
|
||||
system.cpu7: completed 90000 read, 48616 write accesses @6584472
|
||||
system.cpu2: completed 90000 read, 48495 write accesses @6590070
|
||||
system.cpu0: completed 90000 read, 48585 write accesses @6598491
|
||||
system.cpu1: completed 90000 read, 48584 write accesses @6599764
|
||||
system.cpu4: completed 90000 read, 48685 write accesses @6602186
|
||||
system.cpu5: completed 90000 read, 48384 write accesses @6637212
|
||||
system.cpu3: completed 90000 read, 48869 write accesses @6654178
|
||||
system.cpu6: completed 100000 read, 53414 write accesses @7257449
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memte
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 1 2012 14:01:54
|
||||
gem5 started Sep 1 2012 14:03:16
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
gem5 compiled Nov 9 2012 13:23:52
|
||||
gem5 started Nov 10 2012 16:11:14
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 7277301 because maximum number of loads reached
|
||||
Exiting @ tick 7257449 because maximum number of loads reached
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.007242 # Number of seconds simulated
|
||||
sim_ticks 7241726 # Number of ticks simulated
|
||||
final_tick 7241726 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.007257 # Number of seconds simulated
|
||||
sim_ticks 7257449 # Number of ticks simulated
|
||||
final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 40867 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418748 # Number of bytes of host memory used
|
||||
host_seconds 177.20 # Real time elapsed on the host
|
||||
host_tick_rate 69452 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 419088 # Number of bytes of host memory used
|
||||
host_seconds 104.50 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99032 # number of read accesses completed
|
||||
system.cpu0.num_writes 53300 # number of write accesses completed
|
||||
system.cpu0.num_reads 99060 # number of read accesses completed
|
||||
system.cpu0.num_writes 53442 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99071 # number of read accesses completed
|
||||
system.cpu1.num_writes 53375 # number of write accesses completed
|
||||
system.cpu1.num_reads 99097 # number of read accesses completed
|
||||
system.cpu1.num_writes 53480 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99029 # number of read accesses completed
|
||||
system.cpu2.num_writes 53317 # number of write accesses completed
|
||||
system.cpu2.num_reads 99034 # number of read accesses completed
|
||||
system.cpu2.num_writes 53431 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 98175 # number of read accesses completed
|
||||
system.cpu3.num_writes 53115 # number of write accesses completed
|
||||
system.cpu3.num_reads 98135 # number of read accesses completed
|
||||
system.cpu3.num_writes 53229 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 98923 # number of read accesses completed
|
||||
system.cpu4.num_writes 53385 # number of write accesses completed
|
||||
system.cpu4.num_reads 98915 # number of read accesses completed
|
||||
system.cpu4.num_writes 53496 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 98363 # number of read accesses completed
|
||||
system.cpu5.num_writes 52848 # number of write accesses completed
|
||||
system.cpu5.num_reads 98351 # number of read accesses completed
|
||||
system.cpu5.num_writes 52957 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 100000 # number of read accesses completed
|
||||
system.cpu6.num_writes 53283 # number of write accesses completed
|
||||
system.cpu6.num_writes 53414 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99065 # number of read accesses completed
|
||||
system.cpu7.num_writes 53415 # number of write accesses completed
|
||||
system.cpu7.num_reads 99052 # number of read accesses completed
|
||||
system.cpu7.num_writes 53517 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
@ -197,7 +197,7 @@ version=0
|
|||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
@ -283,7 +283,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -345,7 +345,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -407,7 +407,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -469,7 +469,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -531,7 +531,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -593,7 +593,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -655,7 +655,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
@ -717,7 +717,7 @@ type=RubyCache
|
|||
assoc=2
|
||||
dataAccessLatency=1
|
||||
dataArrayBanks=1
|
||||
is_icache=false
|
||||
is_icache=true
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
resourceStalls=false
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -6,77 +6,77 @@ Warning: rounding error > tolerance
|
|||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu4: completed 10000 read, 5367 write accesses @734529
|
||||
system.cpu2: completed 10000 read, 5411 write accesses @739034
|
||||
system.cpu3: completed 10000 read, 5397 write accesses @741278
|
||||
system.cpu6: completed 10000 read, 5401 write accesses @742830
|
||||
system.cpu1: completed 10000 read, 5459 write accesses @745510
|
||||
system.cpu7: completed 10000 read, 5449 write accesses @745578
|
||||
system.cpu5: completed 10000 read, 5460 write accesses @752999
|
||||
system.cpu0: completed 10000 read, 5374 write accesses @754640
|
||||
system.cpu4: completed 20000 read, 10811 write accesses @1483097
|
||||
system.cpu6: completed 20000 read, 10717 write accesses @1490444
|
||||
system.cpu3: completed 20000 read, 10857 write accesses @1492719
|
||||
system.cpu2: completed 20000 read, 10867 write accesses @1494524
|
||||
system.cpu5: completed 20000 read, 10900 write accesses @1496108
|
||||
system.cpu1: completed 20000 read, 10872 write accesses @1496903
|
||||
system.cpu0: completed 20000 read, 10931 write accesses @1504162
|
||||
system.cpu7: completed 20000 read, 11167 write accesses @1514664
|
||||
system.cpu4: completed 30000 read, 16318 write accesses @2226152
|
||||
system.cpu6: completed 30000 read, 16244 write accesses @2235778
|
||||
system.cpu1: completed 30000 read, 16305 write accesses @2241693
|
||||
system.cpu3: completed 30000 read, 16231 write accesses @2243127
|
||||
system.cpu5: completed 30000 read, 16446 write accesses @2247293
|
||||
system.cpu2: completed 30000 read, 16424 write accesses @2250994
|
||||
system.cpu0: completed 30000 read, 16501 write accesses @2260704
|
||||
system.cpu7: completed 30000 read, 16627 write accesses @2268008
|
||||
system.cpu4: completed 40000 read, 21749 write accesses @2962709
|
||||
system.cpu1: completed 40000 read, 21593 write accesses @2979076
|
||||
system.cpu6: completed 40000 read, 21829 write accesses @2993869
|
||||
system.cpu3: completed 40000 read, 21830 write accesses @2994935
|
||||
system.cpu0: completed 40000 read, 21924 write accesses @3006797
|
||||
system.cpu5: completed 40000 read, 22012 write accesses @3007541
|
||||
system.cpu2: completed 40000 read, 21921 write accesses @3009943
|
||||
system.cpu7: completed 40000 read, 22003 write accesses @3016612
|
||||
system.cpu1: completed 50000 read, 26824 write accesses @3710601
|
||||
system.cpu4: completed 50000 read, 27284 write accesses @3716733
|
||||
system.cpu5: completed 50000 read, 27307 write accesses @3743758
|
||||
system.cpu6: completed 50000 read, 27337 write accesses @3752012
|
||||
system.cpu2: completed 50000 read, 27397 write accesses @3754564
|
||||
system.cpu0: completed 50000 read, 27281 write accesses @3754969
|
||||
system.cpu7: completed 50000 read, 27533 write accesses @3759171
|
||||
system.cpu3: completed 50000 read, 27422 write accesses @3773312
|
||||
system.cpu1: completed 60000 read, 32296 write accesses @4453312
|
||||
system.cpu4: completed 60000 read, 32758 write accesses @4481325
|
||||
system.cpu5: completed 60000 read, 32870 write accesses @4492024
|
||||
system.cpu6: completed 60000 read, 32717 write accesses @4494308
|
||||
system.cpu2: completed 60000 read, 32692 write accesses @4496082
|
||||
system.cpu0: completed 60000 read, 32771 write accesses @4507003
|
||||
system.cpu3: completed 60000 read, 32841 write accesses @4507635
|
||||
system.cpu7: completed 60000 read, 32948 write accesses @4509464
|
||||
system.cpu1: completed 70000 read, 37680 write accesses @5196500
|
||||
system.cpu4: completed 70000 read, 38348 write accesses @5238038
|
||||
system.cpu6: completed 70000 read, 38163 write accesses @5248200
|
||||
system.cpu0: completed 70000 read, 38097 write accesses @5249364
|
||||
system.cpu2: completed 70000 read, 38107 write accesses @5253167
|
||||
system.cpu5: completed 70000 read, 38242 write accesses @5256208
|
||||
system.cpu3: completed 70000 read, 38223 write accesses @5263274
|
||||
system.cpu7: completed 70000 read, 38358 write accesses @5264096
|
||||
system.cpu1: completed 80000 read, 43090 write accesses @5938080
|
||||
system.cpu4: completed 80000 read, 43794 write accesses @5986228
|
||||
system.cpu2: completed 80000 read, 43534 write accesses @5995018
|
||||
system.cpu6: completed 80000 read, 43480 write accesses @5996319
|
||||
system.cpu0: completed 80000 read, 43647 write accesses @6010543
|
||||
system.cpu3: completed 80000 read, 43541 write accesses @6012821
|
||||
system.cpu5: completed 80000 read, 43618 write accesses @6013478
|
||||
system.cpu7: completed 80000 read, 43801 write accesses @6025753
|
||||
system.cpu1: completed 90000 read, 48545 write accesses @6687745
|
||||
system.cpu4: completed 90000 read, 49359 write accesses @6726890
|
||||
system.cpu5: completed 90000 read, 48916 write accesses @6741464
|
||||
system.cpu6: completed 90000 read, 49052 write accesses @6749326
|
||||
system.cpu0: completed 90000 read, 49060 write accesses @6762829
|
||||
system.cpu2: completed 90000 read, 49003 write accesses @6764022
|
||||
system.cpu3: completed 90000 read, 48925 write accesses @6765195
|
||||
system.cpu7: completed 90000 read, 49330 write accesses @6780434
|
||||
system.cpu1: completed 100000 read, 54091 write accesses @7447945
|
||||
system.cpu4: completed 10000 read, 5384 write accesses @736811
|
||||
system.cpu2: completed 10000 read, 5431 write accesses @741663
|
||||
system.cpu3: completed 10000 read, 5419 write accesses @743259
|
||||
system.cpu6: completed 10000 read, 5421 write accesses @744711
|
||||
system.cpu1: completed 10000 read, 5468 write accesses @746689
|
||||
system.cpu7: completed 10000 read, 5469 write accesses @749047
|
||||
system.cpu5: completed 10000 read, 5472 write accesses @754994
|
||||
system.cpu0: completed 10000 read, 5388 write accesses @756139
|
||||
system.cpu4: completed 20000 read, 10856 write accesses @1488457
|
||||
system.cpu6: completed 20000 read, 10762 write accesses @1496537
|
||||
system.cpu3: completed 20000 read, 10893 write accesses @1497640
|
||||
system.cpu2: completed 20000 read, 10913 write accesses @1499528
|
||||
system.cpu1: completed 20000 read, 10915 write accesses @1501147
|
||||
system.cpu5: completed 20000 read, 10940 write accesses @1501565
|
||||
system.cpu0: completed 20000 read, 10965 write accesses @1509146
|
||||
system.cpu7: completed 20000 read, 11211 write accesses @1521247
|
||||
system.cpu4: completed 30000 read, 16373 write accesses @2232859
|
||||
system.cpu6: completed 30000 read, 16310 write accesses @2243138
|
||||
system.cpu1: completed 30000 read, 16344 write accesses @2248607
|
||||
system.cpu3: completed 30000 read, 16284 write accesses @2250192
|
||||
system.cpu5: completed 30000 read, 16495 write accesses @2256239
|
||||
system.cpu2: completed 30000 read, 16462 write accesses @2257403
|
||||
system.cpu0: completed 30000 read, 16546 write accesses @2267589
|
||||
system.cpu7: completed 30000 read, 16686 write accesses @2276820
|
||||
system.cpu4: completed 40000 read, 21821 write accesses @2970628
|
||||
system.cpu1: completed 40000 read, 21645 write accesses @2986508
|
||||
system.cpu6: completed 40000 read, 21885 write accesses @3003138
|
||||
system.cpu3: completed 40000 read, 21913 write accesses @3005806
|
||||
system.cpu0: completed 40000 read, 21991 write accesses @3015243
|
||||
system.cpu2: completed 40000 read, 21983 write accesses @3018443
|
||||
system.cpu5: completed 40000 read, 22100 write accesses @3018770
|
||||
system.cpu7: completed 40000 read, 22078 write accesses @3026905
|
||||
system.cpu1: completed 50000 read, 26888 write accesses @3720134
|
||||
system.cpu4: completed 50000 read, 27367 write accesses @3727830
|
||||
system.cpu5: completed 50000 read, 27400 write accesses @3756563
|
||||
system.cpu6: completed 50000 read, 27445 write accesses @3765617
|
||||
system.cpu0: completed 50000 read, 27362 write accesses @3766392
|
||||
system.cpu2: completed 50000 read, 27480 write accesses @3766450
|
||||
system.cpu7: completed 50000 read, 27602 write accesses @3771563
|
||||
system.cpu3: completed 50000 read, 27534 write accesses @3787807
|
||||
system.cpu1: completed 60000 read, 32398 write accesses @4468300
|
||||
system.cpu4: completed 60000 read, 32885 write accesses @4497782
|
||||
system.cpu6: completed 60000 read, 32813 write accesses @4508741
|
||||
system.cpu5: completed 60000 read, 32994 write accesses @4508801
|
||||
system.cpu2: completed 60000 read, 32805 write accesses @4511691
|
||||
system.cpu0: completed 60000 read, 32863 write accesses @4522150
|
||||
system.cpu7: completed 60000 read, 33053 write accesses @4522963
|
||||
system.cpu3: completed 60000 read, 32978 write accesses @4526216
|
||||
system.cpu1: completed 70000 read, 37795 write accesses @5212426
|
||||
system.cpu4: completed 70000 read, 38486 write accesses @5255127
|
||||
system.cpu6: completed 70000 read, 38275 write accesses @5264021
|
||||
system.cpu0: completed 70000 read, 38240 write accesses @5269711
|
||||
system.cpu2: completed 70000 read, 38228 write accesses @5271599
|
||||
system.cpu5: completed 70000 read, 38377 write accesses @5273821
|
||||
system.cpu3: completed 70000 read, 38352 write accesses @5281424
|
||||
system.cpu7: completed 70000 read, 38495 write accesses @5282895
|
||||
system.cpu1: completed 80000 read, 43235 write accesses @5956895
|
||||
system.cpu4: completed 80000 read, 43938 write accesses @6003922
|
||||
system.cpu2: completed 80000 read, 43701 write accesses @6017667
|
||||
system.cpu6: completed 80000 read, 43637 write accesses @6018509
|
||||
system.cpu0: completed 80000 read, 43785 write accesses @6030447
|
||||
system.cpu3: completed 80000 read, 43662 write accesses @6031678
|
||||
system.cpu5: completed 80000 read, 43785 write accesses @6033507
|
||||
system.cpu7: completed 80000 read, 43943 write accesses @6044217
|
||||
system.cpu1: completed 90000 read, 48720 write accesses @6710800
|
||||
system.cpu4: completed 90000 read, 49489 write accesses @6748575
|
||||
system.cpu5: completed 90000 read, 49087 write accesses @6765200
|
||||
system.cpu6: completed 90000 read, 49235 write accesses @6773660
|
||||
system.cpu2: completed 90000 read, 49166 write accesses @6786163
|
||||
system.cpu0: completed 90000 read, 49224 write accesses @6787374
|
||||
system.cpu3: completed 90000 read, 49083 write accesses @6788359
|
||||
system.cpu7: completed 90000 read, 49489 write accesses @6802943
|
||||
system.cpu1: completed 100000 read, 54285 write accesses @7473494
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memt
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 1 2012 14:10:16
|
||||
gem5 started Sep 1 2012 14:11:41
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
gem5 compiled Nov 9 2012 13:27:59
|
||||
gem5 started Nov 10 2012 16:11:47
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 7493512 because maximum number of loads reached
|
||||
Exiting @ tick 7473494 because maximum number of loads reached
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.007448 # Number of seconds simulated
|
||||
sim_ticks 7447945 # Number of ticks simulated
|
||||
final_tick 7447945 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.007473 # Number of seconds simulated
|
||||
sim_ticks 7473494 # Number of ticks simulated
|
||||
final_tick 7473494 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 25433 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418956 # Number of bytes of host memory used
|
||||
host_seconds 292.84 # Real time elapsed on the host
|
||||
host_tick_rate 40647 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 419288 # Number of bytes of host memory used
|
||||
host_seconds 183.86 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99070 # number of read accesses completed
|
||||
system.cpu0.num_writes 53923 # number of write accesses completed
|
||||
system.cpu0.num_reads 99081 # number of read accesses completed
|
||||
system.cpu0.num_writes 54103 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 100000 # number of read accesses completed
|
||||
system.cpu1.num_writes 54091 # number of write accesses completed
|
||||
system.cpu1.num_writes 54285 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99298 # number of read accesses completed
|
||||
system.cpu2.num_writes 53915 # number of write accesses completed
|
||||
system.cpu2.num_reads 99329 # number of read accesses completed
|
||||
system.cpu2.num_writes 54088 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99379 # number of read accesses completed
|
||||
system.cpu3.num_writes 53826 # number of write accesses completed
|
||||
system.cpu3.num_reads 99401 # number of read accesses completed
|
||||
system.cpu3.num_writes 54011 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99471 # number of read accesses completed
|
||||
system.cpu4.num_writes 54600 # number of write accesses completed
|
||||
system.cpu4.num_reads 99475 # number of read accesses completed
|
||||
system.cpu4.num_writes 54793 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99375 # number of read accesses completed
|
||||
system.cpu5.num_writes 54088 # number of write accesses completed
|
||||
system.cpu5.num_reads 99357 # number of read accesses completed
|
||||
system.cpu5.num_writes 54276 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99102 # number of read accesses completed
|
||||
system.cpu6.num_writes 54167 # number of write accesses completed
|
||||
system.cpu6.num_reads 99105 # number of read accesses completed
|
||||
system.cpu6.num_writes 54372 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 98852 # number of read accesses completed
|
||||
system.cpu7.num_writes 54147 # number of write accesses completed
|
||||
system.cpu7.num_reads 98859 # number of read accesses completed
|
||||
system.cpu7.num_writes 54325 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
@ -200,7 +200,7 @@ version=0
|
|||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -6,77 +6,77 @@ Warning: rounding error > tolerance
|
|||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu3: completed 10000 read, 5335 write accesses @606797
|
||||
system.cpu5: completed 10000 read, 5331 write accesses @607565
|
||||
system.cpu4: completed 10000 read, 5526 write accesses @608260
|
||||
system.cpu2: completed 10000 read, 5318 write accesses @614261
|
||||
system.cpu1: completed 10000 read, 5400 write accesses @614387
|
||||
system.cpu7: completed 10000 read, 5362 write accesses @615713
|
||||
system.cpu6: completed 10000 read, 5564 write accesses @615733
|
||||
system.cpu0: completed 10000 read, 5551 write accesses @616304
|
||||
system.cpu5: completed 20000 read, 10723 write accesses @1217974
|
||||
system.cpu0: completed 20000 read, 11047 write accesses @1228624
|
||||
system.cpu4: completed 20000 read, 10902 write accesses @1228676
|
||||
system.cpu1: completed 20000 read, 10777 write accesses @1228883
|
||||
system.cpu7: completed 20000 read, 10727 write accesses @1230451
|
||||
system.cpu3: completed 20000 read, 10656 write accesses @1231448
|
||||
system.cpu2: completed 20000 read, 10657 write accesses @1236334
|
||||
system.cpu6: completed 20000 read, 11082 write accesses @1236758
|
||||
system.cpu5: completed 30000 read, 15988 write accesses @1827079
|
||||
system.cpu1: completed 30000 read, 16124 write accesses @1833167
|
||||
system.cpu3: completed 30000 read, 15943 write accesses @1835575
|
||||
system.cpu6: completed 30000 read, 16327 write accesses @1840325
|
||||
system.cpu0: completed 30000 read, 16411 write accesses @1845820
|
||||
system.cpu7: completed 30000 read, 16138 write accesses @1851244
|
||||
system.cpu2: completed 30000 read, 16138 write accesses @1863740
|
||||
system.cpu4: completed 30000 read, 16319 write accesses @1864484
|
||||
system.cpu5: completed 40000 read, 21536 write accesses @2432906
|
||||
system.cpu1: completed 40000 read, 21516 write accesses @2445656
|
||||
system.cpu0: completed 40000 read, 21751 write accesses @2457852
|
||||
system.cpu3: completed 40000 read, 21310 write accesses @2457970
|
||||
system.cpu7: completed 40000 read, 21388 write accesses @2458337
|
||||
system.cpu6: completed 40000 read, 21741 write accesses @2459051
|
||||
system.cpu4: completed 40000 read, 21462 write accesses @2473826
|
||||
system.cpu2: completed 40000 read, 21429 write accesses @2476553
|
||||
system.cpu5: completed 50000 read, 27059 write accesses @3049178
|
||||
system.cpu7: completed 50000 read, 26653 write accesses @3064589
|
||||
system.cpu1: completed 50000 read, 26847 write accesses @3066332
|
||||
system.cpu3: completed 50000 read, 26520 write accesses @3067661
|
||||
system.cpu6: completed 50000 read, 27151 write accesses @3069278
|
||||
system.cpu4: completed 50000 read, 26852 write accesses @3080753
|
||||
system.cpu0: completed 50000 read, 27078 write accesses @3081059
|
||||
system.cpu2: completed 50000 read, 26858 write accesses @3093584
|
||||
system.cpu5: completed 60000 read, 32391 write accesses @3656779
|
||||
system.cpu1: completed 60000 read, 32290 write accesses @3669694
|
||||
system.cpu3: completed 60000 read, 31832 write accesses @3679631
|
||||
system.cpu0: completed 60000 read, 32411 write accesses @3682976
|
||||
system.cpu7: completed 60000 read, 31852 write accesses @3683261
|
||||
system.cpu6: completed 60000 read, 32690 write accesses @3693796
|
||||
system.cpu2: completed 60000 read, 32174 write accesses @3694259
|
||||
system.cpu4: completed 60000 read, 32211 write accesses @3697154
|
||||
system.cpu1: completed 70000 read, 37707 write accesses @4274498
|
||||
system.cpu3: completed 70000 read, 37255 write accesses @4279718
|
||||
system.cpu5: completed 70000 read, 37867 write accesses @4283684
|
||||
system.cpu0: completed 70000 read, 37805 write accesses @4287731
|
||||
system.cpu7: completed 70000 read, 37138 write accesses @4296794
|
||||
system.cpu2: completed 70000 read, 37605 write accesses @4304710
|
||||
system.cpu6: completed 70000 read, 38072 write accesses @4311342
|
||||
system.cpu4: completed 70000 read, 37624 write accesses @4316870
|
||||
system.cpu3: completed 80000 read, 42498 write accesses @4877336
|
||||
system.cpu0: completed 80000 read, 43132 write accesses @4889693
|
||||
system.cpu1: completed 80000 read, 43168 write accesses @4896265
|
||||
system.cpu5: completed 80000 read, 43273 write accesses @4899143
|
||||
system.cpu7: completed 80000 read, 42494 write accesses @4912991
|
||||
system.cpu2: completed 80000 read, 43018 write accesses @4921903
|
||||
system.cpu6: completed 80000 read, 43483 write accesses @4928537
|
||||
system.cpu4: completed 80000 read, 42951 write accesses @4931114
|
||||
system.cpu3: completed 90000 read, 47893 write accesses @5493844
|
||||
system.cpu1: completed 90000 read, 48591 write accesses @5495944
|
||||
system.cpu0: completed 90000 read, 48484 write accesses @5503496
|
||||
system.cpu5: completed 90000 read, 48798 write accesses @5509616
|
||||
system.cpu2: completed 90000 read, 48092 write accesses @5514734
|
||||
system.cpu7: completed 90000 read, 47926 write accesses @5524841
|
||||
system.cpu4: completed 90000 read, 48357 write accesses @5550818
|
||||
system.cpu6: completed 90000 read, 48791 write accesses @5555216
|
||||
system.cpu3: completed 100000 read, 53266 write accesses @6111458
|
||||
system.cpu3: completed 10000 read, 5373 write accesses @610961
|
||||
system.cpu5: completed 10000 read, 5365 write accesses @611018
|
||||
system.cpu4: completed 10000 read, 5553 write accesses @613027
|
||||
system.cpu2: completed 10000 read, 5350 write accesses @617677
|
||||
system.cpu1: completed 10000 read, 5430 write accesses @618344
|
||||
system.cpu0: completed 10000 read, 5583 write accesses @619157
|
||||
system.cpu7: completed 10000 read, 5389 write accesses @620153
|
||||
system.cpu6: completed 10000 read, 5612 write accesses @620650
|
||||
system.cpu5: completed 20000 read, 10789 write accesses @1225454
|
||||
system.cpu1: completed 20000 read, 10846 write accesses @1236230
|
||||
system.cpu4: completed 20000 read, 10993 write accesses @1237289
|
||||
system.cpu0: completed 20000 read, 11135 write accesses @1237437
|
||||
system.cpu7: completed 20000 read, 10790 write accesses @1238914
|
||||
system.cpu3: completed 20000 read, 10722 write accesses @1239177
|
||||
system.cpu6: completed 20000 read, 11153 write accesses @1244507
|
||||
system.cpu2: completed 20000 read, 10728 write accesses @1245295
|
||||
system.cpu5: completed 30000 read, 16089 write accesses @1837067
|
||||
system.cpu1: completed 30000 read, 16220 write accesses @1844516
|
||||
system.cpu3: completed 30000 read, 16042 write accesses @1846213
|
||||
system.cpu6: completed 30000 read, 16442 write accesses @1852618
|
||||
system.cpu0: completed 30000 read, 16510 write accesses @1857227
|
||||
system.cpu7: completed 30000 read, 16238 write accesses @1862399
|
||||
system.cpu2: completed 30000 read, 16227 write accesses @1874504
|
||||
system.cpu4: completed 30000 read, 16481 write accesses @1879909
|
||||
system.cpu5: completed 40000 read, 21666 write accesses @2447180
|
||||
system.cpu1: completed 40000 read, 21716 write accesses @2464865
|
||||
system.cpu0: completed 40000 read, 21907 write accesses @2473366
|
||||
system.cpu7: completed 40000 read, 21535 write accesses @2473664
|
||||
system.cpu3: completed 40000 read, 21446 write accesses @2475585
|
||||
system.cpu6: completed 40000 read, 21928 write accesses @2479522
|
||||
system.cpu4: completed 40000 read, 21651 write accesses @2491724
|
||||
system.cpu2: completed 40000 read, 21571 write accesses @2492947
|
||||
system.cpu5: completed 50000 read, 27225 write accesses @3067865
|
||||
system.cpu7: completed 50000 read, 26823 write accesses @3086290
|
||||
system.cpu3: completed 50000 read, 26661 write accesses @3087077
|
||||
system.cpu1: completed 50000 read, 27045 write accesses @3088502
|
||||
system.cpu6: completed 50000 read, 27350 write accesses @3091373
|
||||
system.cpu0: completed 50000 read, 27240 write accesses @3099902
|
||||
system.cpu4: completed 50000 read, 27063 write accesses @3101501
|
||||
system.cpu2: completed 50000 read, 27064 write accesses @3114914
|
||||
system.cpu5: completed 60000 read, 32586 write accesses @3679414
|
||||
system.cpu1: completed 60000 read, 32546 write accesses @3694760
|
||||
system.cpu3: completed 60000 read, 32032 write accesses @3702088
|
||||
system.cpu7: completed 60000 read, 32061 write accesses @3707072
|
||||
system.cpu0: completed 60000 read, 32607 write accesses @3710014
|
||||
system.cpu2: completed 60000 read, 32411 write accesses @3717514
|
||||
system.cpu6: completed 60000 read, 32905 write accesses @3719411
|
||||
system.cpu4: completed 60000 read, 32455 write accesses @3724218
|
||||
system.cpu1: completed 70000 read, 37971 write accesses @4303479
|
||||
system.cpu3: completed 70000 read, 37478 write accesses @4307612
|
||||
system.cpu5: completed 70000 read, 38121 write accesses @4312096
|
||||
system.cpu0: completed 70000 read, 38044 write accesses @4316156
|
||||
system.cpu7: completed 70000 read, 37345 write accesses @4323040
|
||||
system.cpu2: completed 70000 read, 37853 write accesses @4334714
|
||||
system.cpu6: completed 70000 read, 38341 write accesses @4338265
|
||||
system.cpu4: completed 70000 read, 37883 write accesses @4348139
|
||||
system.cpu3: completed 80000 read, 42790 write accesses @4909950
|
||||
system.cpu0: completed 80000 read, 43447 write accesses @4922258
|
||||
system.cpu1: completed 80000 read, 43458 write accesses @4929896
|
||||
system.cpu5: completed 80000 read, 43556 write accesses @4929946
|
||||
system.cpu7: completed 80000 read, 42733 write accesses @4945136
|
||||
system.cpu2: completed 80000 read, 43278 write accesses @4954988
|
||||
system.cpu6: completed 80000 read, 43794 write accesses @4962728
|
||||
system.cpu4: completed 80000 read, 43313 write accesses @4970893
|
||||
system.cpu3: completed 90000 read, 48235 write accesses @5529277
|
||||
system.cpu1: completed 90000 read, 48908 write accesses @5532854
|
||||
system.cpu0: completed 90000 read, 48795 write accesses @5538200
|
||||
system.cpu5: completed 90000 read, 49134 write accesses @5544337
|
||||
system.cpu2: completed 90000 read, 48427 write accesses @5551687
|
||||
system.cpu7: completed 90000 read, 48273 write accesses @5561660
|
||||
system.cpu4: completed 90000 read, 48720 write accesses @5589754
|
||||
system.cpu6: completed 90000 read, 49134 write accesses @5592253
|
||||
system.cpu0: completed 100000 read, 54250 write accesses @6151475
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
|
||||
Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Jul 28 2012 11:35:39
|
||||
gem5 started Jul 28 2012 11:36:05
|
||||
gem5 executing on zizzer
|
||||
gem5 compiled Nov 9 2012 13:32:04
|
||||
gem5 started Nov 10 2012 16:12:27
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 19665440 because maximum number of loads reached
|
||||
Exiting @ tick 6151475 because maximum number of loads reached
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.006111 # Number of seconds simulated
|
||||
sim_ticks 6111458 # Number of ticks simulated
|
||||
final_tick 6111458 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.006151 # Number of seconds simulated
|
||||
sim_ticks 6151475 # Number of ticks simulated
|
||||
final_tick 6151475 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 30926 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418916 # Number of bytes of host memory used
|
||||
host_seconds 197.62 # Real time elapsed on the host
|
||||
host_tick_rate 48581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 419240 # Number of bytes of host memory used
|
||||
host_seconds 126.62 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0
|
|||
system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99998 # number of read accesses completed
|
||||
system.cpu0.num_writes 53877 # number of write accesses completed
|
||||
system.cpu0.num_reads 100000 # number of read accesses completed
|
||||
system.cpu0.num_writes 54250 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99919 # number of read accesses completed
|
||||
system.cpu1.num_writes 53996 # number of write accesses completed
|
||||
system.cpu1.num_reads 99858 # number of read accesses completed
|
||||
system.cpu1.num_writes 54337 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99673 # number of read accesses completed
|
||||
system.cpu2.num_writes 53416 # number of write accesses completed
|
||||
system.cpu2.num_reads 99660 # number of read accesses completed
|
||||
system.cpu2.num_writes 53758 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 100000 # number of read accesses completed
|
||||
system.cpu3.num_writes 53266 # number of write accesses completed
|
||||
system.cpu3.num_reads 99997 # number of read accesses completed
|
||||
system.cpu3.num_writes 53569 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99266 # number of read accesses completed
|
||||
system.cpu4.num_writes 53358 # number of write accesses completed
|
||||
system.cpu4.num_reads 99232 # number of read accesses completed
|
||||
system.cpu4.num_writes 53727 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99912 # number of read accesses completed
|
||||
system.cpu5.num_writes 54055 # number of write accesses completed
|
||||
system.cpu5.num_reads 99852 # number of read accesses completed
|
||||
system.cpu5.num_writes 54401 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99083 # number of read accesses completed
|
||||
system.cpu6.num_writes 53609 # number of write accesses completed
|
||||
system.cpu6.num_reads 99007 # number of read accesses completed
|
||||
system.cpu6.num_writes 53961 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99673 # number of read accesses completed
|
||||
system.cpu7.num_writes 53053 # number of write accesses completed
|
||||
system.cpu7.num_reads 99727 # number of read accesses completed
|
||||
system.cpu7.num_writes 53437 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
@ -200,7 +200,7 @@ version=0
|
|||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -6,77 +6,77 @@ Warning: rounding error > tolerance
|
|||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu5: completed 10000 read, 5478 write accesses @567161
|
||||
system.cpu3: completed 10000 read, 5277 write accesses @567758
|
||||
system.cpu1: completed 10000 read, 5424 write accesses @571139
|
||||
system.cpu2: completed 10000 read, 5363 write accesses @576050
|
||||
system.cpu6: completed 10000 read, 5463 write accesses @585533
|
||||
system.cpu4: completed 10000 read, 5420 write accesses @589179
|
||||
system.cpu7: completed 10000 read, 5472 write accesses @590379
|
||||
system.cpu0: completed 10000 read, 5369 write accesses @590533
|
||||
system.cpu5: completed 20000 read, 10791 write accesses @1146089
|
||||
system.cpu3: completed 20000 read, 10874 write accesses @1153309
|
||||
system.cpu1: completed 20000 read, 10881 write accesses @1155896
|
||||
system.cpu2: completed 20000 read, 10800 write accesses @1162820
|
||||
system.cpu0: completed 20000 read, 10720 write accesses @1163331
|
||||
system.cpu4: completed 20000 read, 10833 write accesses @1163813
|
||||
system.cpu6: completed 20000 read, 10762 write accesses @1164662
|
||||
system.cpu7: completed 20000 read, 10940 write accesses @1175272
|
||||
system.cpu3: completed 30000 read, 16099 write accesses @1730233
|
||||
system.cpu5: completed 30000 read, 16356 write accesses @1731718
|
||||
system.cpu6: completed 30000 read, 16169 write accesses @1737322
|
||||
system.cpu0: completed 30000 read, 16008 write accesses @1738364
|
||||
system.cpu1: completed 30000 read, 16522 write accesses @1739971
|
||||
system.cpu2: completed 30000 read, 16224 write accesses @1741457
|
||||
system.cpu4: completed 30000 read, 16211 write accesses @1745036
|
||||
system.cpu7: completed 30000 read, 16445 write accesses @1750339
|
||||
system.cpu5: completed 40000 read, 21741 write accesses @2306008
|
||||
system.cpu6: completed 40000 read, 21530 write accesses @2310178
|
||||
system.cpu2: completed 40000 read, 21620 write accesses @2310592
|
||||
system.cpu4: completed 40000 read, 21531 write accesses @2315393
|
||||
system.cpu0: completed 40000 read, 21438 write accesses @2316997
|
||||
system.cpu3: completed 40000 read, 21653 write accesses @2317686
|
||||
system.cpu1: completed 40000 read, 21749 write accesses @2319017
|
||||
system.cpu7: completed 40000 read, 21844 write accesses @2338046
|
||||
system.cpu3: completed 50000 read, 27002 write accesses @2880938
|
||||
system.cpu2: completed 50000 read, 27054 write accesses @2886893
|
||||
system.cpu6: completed 50000 read, 26777 write accesses @2887224
|
||||
system.cpu5: completed 50000 read, 27071 write accesses @2894287
|
||||
system.cpu4: completed 50000 read, 26806 write accesses @2897144
|
||||
system.cpu0: completed 50000 read, 26853 write accesses @2903681
|
||||
system.cpu7: completed 50000 read, 27200 write accesses @2905958
|
||||
system.cpu1: completed 50000 read, 27246 write accesses @2906447
|
||||
system.cpu2: completed 60000 read, 32371 write accesses @3448040
|
||||
system.cpu6: completed 60000 read, 32232 write accesses @3458102
|
||||
system.cpu3: completed 60000 read, 32278 write accesses @3464050
|
||||
system.cpu0: completed 60000 read, 32186 write accesses @3466844
|
||||
system.cpu4: completed 60000 read, 31956 write accesses @3470756
|
||||
system.cpu5: completed 60000 read, 32561 write accesses @3476407
|
||||
system.cpu1: completed 60000 read, 32600 write accesses @3479914
|
||||
system.cpu7: completed 60000 read, 32524 write accesses @3491585
|
||||
system.cpu2: completed 70000 read, 37778 write accesses @4027715
|
||||
system.cpu3: completed 70000 read, 37641 write accesses @4032589
|
||||
system.cpu6: completed 70000 read, 37624 write accesses @4034915
|
||||
system.cpu4: completed 70000 read, 37315 write accesses @4048771
|
||||
system.cpu0: completed 70000 read, 37650 write accesses @4058138
|
||||
system.cpu1: completed 70000 read, 38210 write accesses @4062463
|
||||
system.cpu5: completed 70000 read, 37970 write accesses @4063291
|
||||
system.cpu7: completed 70000 read, 37837 write accesses @4069993
|
||||
system.cpu2: completed 80000 read, 43081 write accesses @4605440
|
||||
system.cpu6: completed 80000 read, 43005 write accesses @4612592
|
||||
system.cpu3: completed 80000 read, 43103 write accesses @4614137
|
||||
system.cpu5: completed 80000 read, 43266 write accesses @4625729
|
||||
system.cpu0: completed 80000 read, 42925 write accesses @4631387
|
||||
system.cpu4: completed 80000 read, 42800 write accesses @4633690
|
||||
system.cpu1: completed 80000 read, 43498 write accesses @4640305
|
||||
system.cpu7: completed 80000 read, 43249 write accesses @4647178
|
||||
system.cpu2: completed 90000 read, 48427 write accesses @5170760
|
||||
system.cpu3: completed 90000 read, 48430 write accesses @5181607
|
||||
system.cpu6: completed 90000 read, 48549 write accesses @5189137
|
||||
system.cpu5: completed 90000 read, 48576 write accesses @5206014
|
||||
system.cpu4: completed 90000 read, 48077 write accesses @5207168
|
||||
system.cpu1: completed 90000 read, 48840 write accesses @5207183
|
||||
system.cpu0: completed 90000 read, 48241 write accesses @5207339
|
||||
system.cpu7: completed 90000 read, 48589 write accesses @5224757
|
||||
system.cpu2: completed 100000 read, 53907 write accesses @5753960
|
||||
system.cpu5: completed 10000 read, 5516 write accesses @570851
|
||||
system.cpu3: completed 10000 read, 5324 write accesses @572812
|
||||
system.cpu1: completed 10000 read, 5481 write accesses @576530
|
||||
system.cpu2: completed 10000 read, 5411 write accesses @581924
|
||||
system.cpu6: completed 10000 read, 5498 write accesses @589277
|
||||
system.cpu4: completed 10000 read, 5455 write accesses @592697
|
||||
system.cpu7: completed 10000 read, 5509 write accesses @593396
|
||||
system.cpu0: completed 10000 read, 5411 write accesses @595334
|
||||
system.cpu5: completed 20000 read, 10869 write accesses @1154450
|
||||
system.cpu3: completed 20000 read, 10943 write accesses @1161279
|
||||
system.cpu1: completed 20000 read, 10969 write accesses @1165235
|
||||
system.cpu2: completed 20000 read, 10883 write accesses @1170873
|
||||
system.cpu4: completed 20000 read, 10908 write accesses @1171882
|
||||
system.cpu0: completed 20000 read, 10807 write accesses @1172431
|
||||
system.cpu6: completed 20000 read, 10859 write accesses @1174037
|
||||
system.cpu7: completed 20000 read, 11017 write accesses @1183706
|
||||
system.cpu5: completed 30000 read, 16441 write accesses @1743020
|
||||
system.cpu3: completed 30000 read, 16218 write accesses @1743361
|
||||
system.cpu0: completed 30000 read, 16106 write accesses @1749355
|
||||
system.cpu6: completed 30000 read, 16285 write accesses @1751262
|
||||
system.cpu2: completed 30000 read, 16334 write accesses @1752944
|
||||
system.cpu1: completed 30000 read, 16624 write accesses @1754412
|
||||
system.cpu4: completed 30000 read, 16300 write accesses @1756493
|
||||
system.cpu7: completed 30000 read, 16545 write accesses @1761662
|
||||
system.cpu5: completed 40000 read, 21903 write accesses @2321871
|
||||
system.cpu2: completed 40000 read, 21777 write accesses @2328122
|
||||
system.cpu6: completed 40000 read, 21684 write accesses @2328788
|
||||
system.cpu0: completed 40000 read, 21584 write accesses @2333159
|
||||
system.cpu4: completed 40000 read, 21691 write accesses @2333509
|
||||
system.cpu3: completed 40000 read, 21802 write accesses @2335052
|
||||
system.cpu1: completed 40000 read, 21911 write accesses @2336699
|
||||
system.cpu7: completed 40000 read, 21984 write accesses @2354153
|
||||
system.cpu3: completed 50000 read, 27199 write accesses @2900098
|
||||
system.cpu6: completed 50000 read, 26980 write accesses @2908928
|
||||
system.cpu2: completed 50000 read, 27238 write accesses @2909195
|
||||
system.cpu5: completed 50000 read, 27250 write accesses @2913605
|
||||
system.cpu4: completed 50000 read, 26997 write accesses @2920489
|
||||
system.cpu0: completed 50000 read, 27072 write accesses @2924735
|
||||
system.cpu1: completed 50000 read, 27407 write accesses @2925503
|
||||
system.cpu7: completed 50000 read, 27387 write accesses @2927681
|
||||
system.cpu2: completed 60000 read, 32632 write accesses @3474793
|
||||
system.cpu6: completed 60000 read, 32472 write accesses @3482759
|
||||
system.cpu3: completed 60000 read, 32504 write accesses @3487367
|
||||
system.cpu0: completed 60000 read, 32401 write accesses @3493294
|
||||
system.cpu4: completed 60000 read, 32171 write accesses @3498890
|
||||
system.cpu5: completed 60000 read, 32778 write accesses @3503066
|
||||
system.cpu1: completed 60000 read, 32891 write accesses @3509381
|
||||
system.cpu7: completed 60000 read, 32765 write accesses @3516772
|
||||
system.cpu2: completed 70000 read, 38066 write accesses @4058828
|
||||
system.cpu3: completed 70000 read, 37916 write accesses @4058910
|
||||
system.cpu6: completed 70000 read, 37885 write accesses @4063852
|
||||
system.cpu4: completed 70000 read, 37622 write accesses @4080369
|
||||
system.cpu0: completed 70000 read, 37925 write accesses @4085861
|
||||
system.cpu5: completed 70000 read, 38249 write accesses @4094801
|
||||
system.cpu1: completed 70000 read, 38488 write accesses @4095495
|
||||
system.cpu7: completed 70000 read, 38117 write accesses @4097708
|
||||
system.cpu2: completed 80000 read, 43433 write accesses @4639406
|
||||
system.cpu3: completed 80000 read, 43416 write accesses @4647614
|
||||
system.cpu6: completed 80000 read, 43333 write accesses @4648301
|
||||
system.cpu5: completed 80000 read, 43562 write accesses @4662354
|
||||
system.cpu0: completed 80000 read, 43227 write accesses @4664558
|
||||
system.cpu4: completed 80000 read, 43117 write accesses @4665549
|
||||
system.cpu1: completed 80000 read, 43838 write accesses @4675271
|
||||
system.cpu7: completed 80000 read, 43557 write accesses @4676998
|
||||
system.cpu2: completed 90000 read, 48793 write accesses @5208478
|
||||
system.cpu3: completed 90000 read, 48771 write accesses @5220479
|
||||
system.cpu6: completed 90000 read, 48900 write accesses @5227295
|
||||
system.cpu5: completed 90000 read, 48930 write accesses @5242795
|
||||
system.cpu1: completed 90000 read, 49220 write accesses @5246394
|
||||
system.cpu0: completed 90000 read, 48602 write accesses @5246963
|
||||
system.cpu4: completed 90000 read, 48456 write accesses @5248509
|
||||
system.cpu7: completed 90000 read, 48936 write accesses @5260982
|
||||
system.cpu2: completed 100000 read, 54294 write accesses @5795833
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alp
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 1 2012 13:53:26
|
||||
gem5 started Sep 1 2012 13:54:47
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
gem5 compiled Nov 9 2012 13:19:47
|
||||
gem5 started Nov 10 2012 16:10:39
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 5747338 because maximum number of loads reached
|
||||
Exiting @ tick 5795833 because maximum number of loads reached
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.005754 # Number of seconds simulated
|
||||
sim_ticks 5753960 # Number of ticks simulated
|
||||
final_tick 5753960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.005796 # Number of seconds simulated
|
||||
sim_ticks 5795833 # Number of ticks simulated
|
||||
final_tick 5795833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 28381 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 417808 # Number of bytes of host memory used
|
||||
host_seconds 202.74 # Real time elapsed on the host
|
||||
host_tick_rate 44806 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 419160 # Number of bytes of host memory used
|
||||
host_seconds 129.36 # Real time elapsed on the host
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
@ -157,29 +157,29 @@ system.dir_cntrl0.probeFilter.num_tag_array_reads 0
|
|||
system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes
|
||||
system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99424 # number of read accesses completed
|
||||
system.cpu0.num_writes 53376 # number of write accesses completed
|
||||
system.cpu0.num_reads 99395 # number of read accesses completed
|
||||
system.cpu0.num_writes 53721 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99626 # number of read accesses completed
|
||||
system.cpu1.num_writes 54012 # number of write accesses completed
|
||||
system.cpu1.num_reads 99652 # number of read accesses completed
|
||||
system.cpu1.num_writes 54399 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 100000 # number of read accesses completed
|
||||
system.cpu2.num_writes 53908 # number of write accesses completed
|
||||
system.cpu2.num_writes 54294 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99716 # number of read accesses completed
|
||||
system.cpu3.num_writes 53812 # number of write accesses completed
|
||||
system.cpu3.num_reads 99790 # number of read accesses completed
|
||||
system.cpu3.num_writes 54193 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99512 # number of read accesses completed
|
||||
system.cpu4.num_writes 53333 # number of write accesses completed
|
||||
system.cpu4.num_reads 99482 # number of read accesses completed
|
||||
system.cpu4.num_writes 53726 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99476 # number of read accesses completed
|
||||
system.cpu5.num_writes 53666 # number of write accesses completed
|
||||
system.cpu5.num_reads 99470 # number of read accesses completed
|
||||
system.cpu5.num_writes 54029 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99747 # number of read accesses completed
|
||||
system.cpu6.num_writes 53910 # number of write accesses completed
|
||||
system.cpu6.num_reads 99753 # number of read accesses completed
|
||||
system.cpu6.num_writes 54335 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99133 # number of read accesses completed
|
||||
system.cpu7.num_writes 53472 # number of write accesses completed
|
||||
system.cpu7.num_reads 99102 # number of read accesses completed
|
||||
system.cpu7.num_writes 53848 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
@ -197,7 +197,7 @@ version=0
|
|||
[system.dir_cntrl0.directory]
|
||||
type=RubyDirectoryMemory
|
||||
map_levels=4
|
||||
numa_high_bit=6
|
||||
numa_high_bit=5
|
||||
size=268435456
|
||||
use_map=false
|
||||
version=0
|
||||
|
|
|
@ -1,26 +1,26 @@
|
|||
Real time: Oct/08/2012 22:20:34
|
||||
Real time: Nov/10/2012 16:33:28
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 79
|
||||
Elapsed_time_in_minutes: 1.31667
|
||||
Elapsed_time_in_hours: 0.0219444
|
||||
Elapsed_time_in_days: 0.000914352
|
||||
Elapsed_time_in_seconds: 47
|
||||
Elapsed_time_in_minutes: 0.783333
|
||||
Elapsed_time_in_hours: 0.0130556
|
||||
Elapsed_time_in_days: 0.000543981
|
||||
|
||||
Virtual_time_in_seconds: 48.17
|
||||
Virtual_time_in_minutes: 0.802833
|
||||
Virtual_time_in_hours: 0.0133806
|
||||
Virtual_time_in_days: 0.000557523
|
||||
Virtual_time_in_seconds: 46.6
|
||||
Virtual_time_in_minutes: 0.776667
|
||||
Virtual_time_in_hours: 0.0129444
|
||||
Virtual_time_in_days: 0.000539352
|
||||
|
||||
Ruby_current_time: 8594451
|
||||
Ruby_current_time: 8664886
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 8594451
|
||||
Ruby_cycles: 8664886
|
||||
|
||||
mbytes_resident: 69.9141
|
||||
mbytes_total: 408.566
|
||||
resident_ratio: 0.17113
|
||||
mbytes_resident: 70.3164
|
||||
mbytes_total: 408.891
|
||||
resident_ratio: 0.171978
|
||||
|
||||
ruby_cycles_executed: [ 8594452 8594452 8594452 8594452 8594452 8594452 8594452 8594452 ]
|
||||
ruby_cycles_executed: [ 8664887 8664887 8664887 8664887 8664887 8664887 8664887 8664887 ]
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
|
||||
|
@ -30,29 +30,29 @@ Directory-0:0
|
|||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 612679 average: 15.9984 | standard deviation: 0.127251 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 10 612557 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 16 count: 617680 average: 15.9984 | standard deviation: 0.126735 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 10 617558 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 32 max: 4653 count: 612551 average: 1795.7 | standard deviation: 410.66 | 0 1 4 5 4 6 2 4 4 5 2 2 2 5 3 0 0 6 14 17 28 51 113 126 222 341 478 739 943 1172 1767 2399 2690 3474 4236 4975 6483 7278 7353 9544 11638 11194 12606 14095 14781 17182 16959 16021 18801 20784 18178 19118 19510 19480 21166 19191 16928 19138 19616 16277 16268 15657 15140 15502 13442 11313 12308 12228 9547 9169 8703 7770 7869 6263 5198 5485 5264 4033 3801 3587 3147 3163 2478 2078 2041 1979 1479 1363 1116 1041 1026 720 599 673 609 407 374 362 280 234 210 164 195 189 108 117 93 78 70 54 43 54 50 33 34 21 18 15 18 13 13 5 6 5 4 10 3 7 8 5 5 5 4 2 3 3 2 0 0 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 4653 count: 398259 average: 1796.14 | standard deviation: 410.545 | 0 1 4 2 4 4 1 2 2 3 1 0 2 3 2 0 0 4 9 13 19 34 69 77 142 213 312 496 634 789 1112 1557 1708 2226 2742 3251 4192 4713 4761 6194 7550 7329 8214 9166 9655 11143 11019 10418 12237 13560 11738 12340 12645 12602 13722 12490 11061 12504 12769 10620 10543 10215 9778 10113 8796 7377 7953 7936 6168 5941 5772 5011 5117 4169 3341 3601 3439 2674 2487 2285 2012 2017 1631 1369 1349 1275 989 894 721 679 658 468 412 453 398 269 258 217 175 160 142 102 128 123 67 76 57 44 47 33 26 32 31 19 17 11 12 10 11 10 10 3 2 4 3 7 1 3 5 2 4 4 4 1 1 2 1 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 32 max: 4626 count: 214292 average: 1794.89 | standard deviation: 410.873 | 0 0 0 3 0 2 1 2 2 2 1 2 0 2 1 0 0 2 5 4 9 17 44 49 80 128 166 243 309 383 655 842 982 1248 1494 1724 2291 2565 2592 3350 4088 3865 4392 4929 5126 6039 5940 5603 6564 7224 6440 6778 6865 6878 7444 6701 5867 6634 6847 5657 5725 5442 5362 5389 4646 3936 4355 4292 3379 3228 2931 2759 2752 2094 1857 1884 1825 1359 1314 1302 1135 1146 847 709 692 704 490 469 395 362 368 252 187 220 211 138 116 145 105 74 68 62 67 66 41 41 36 34 23 21 17 22 19 14 17 10 6 5 7 3 3 2 4 1 1 3 2 4 3 3 1 1 0 1 2 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 4653 count: 604395 average: 1797.09 | standard deviation: 410.541 | 0 1 4 5 4 6 2 4 4 5 2 2 2 5 3 0 0 5 14 16 27 51 107 121 212 329 459 718 907 1137 1731 2346 2618 3386 4136 4857 6358 7136 7189 9366 11477 10968 12372 13884 14549 16941 16662 15768 18551 20542 17864 18850 19270 19247 20917 18940 16714 18905 19436 16065 16081 15483 14980 15328 13265 11178 12186 12123 9437 9093 8626 7689 7797 6193 5141 5442 5224 3985 3768 3556 3119 3142 2458 2058 2027 1963 1464 1353 1109 1034 1018 712 590 667 604 406 370 361 279 234 209 164 191 188 105 115 92 77 68 54 43 53 50 33 33 21 17 15 18 13 13 5 6 5 4 9 3 7 8 5 5 5 4 2 3 3 2 0 0 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache_wCC: [binsize: 32 max: 4002 count: 8156 average: 1692.69 | standard deviation: 406.323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 6 5 10 12 19 21 36 35 36 53 72 88 100 118 125 142 164 178 161 226 234 211 232 241 297 253 250 242 314 268 240 233 249 251 214 233 180 212 187 174 160 174 177 135 122 105 110 76 77 81 72 70 57 43 40 48 33 31 28 21 20 20 14 16 15 10 7 7 8 8 9 6 5 1 4 1 1 0 1 0 4 1 3 2 1 1 2 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 32 max: 4653 count: 617552 average: 1795.77 | standard deviation: 410.976 | 0 1 4 5 4 6 2 4 4 5 2 2 2 5 3 0 0 6 14 17 28 51 113 127 225 347 480 747 957 1194 1787 2428 2721 3514 4274 5019 6546 7363 7419 9623 11747 11289 12705 14208 14907 17297 17099 16125 18938 20942 18315 19262 19657 19621 21335 19340 17072 19265 19761 16416 16371 15770 15258 15618 13543 11418 12401 12344 9621 9246 8775 7842 7924 6316 5244 5542 5313 4064 3837 3620 3185 3194 2499 2105 2049 2002 1491 1379 1125 1055 1034 725 608 679 620 414 386 364 284 235 215 166 196 192 113 118 96 79 70 55 46 54 51 34 34 21 18 15 18 13 14 5 6 5 4 10 3 7 8 5 5 5 4 2 3 3 2 0 0 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 4653 count: 401489 average: 1796.25 | standard deviation: 410.867 | 0 1 4 2 4 4 1 2 2 3 1 0 2 3 2 0 0 4 9 13 19 34 69 77 144 218 313 500 642 800 1127 1576 1726 2253 2769 3277 4237 4769 4803 6248 7617 7392 8279 9235 9736 11211 11105 10479 12314 13658 11825 12430 12744 12685 13841 12591 11160 12584 12865 10706 10616 10295 9850 10193 8857 7442 8016 8018 6215 5997 5820 5065 5150 4203 3375 3637 3472 2688 2508 2307 2031 2036 1642 1387 1355 1294 997 904 726 689 664 471 420 457 405 273 264 218 178 161 144 103 129 126 69 76 60 45 47 34 28 32 32 20 17 11 12 10 11 10 11 3 2 4 3 7 1 3 5 2 4 4 4 1 1 2 1 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST: [binsize: 32 max: 4626 count: 216063 average: 1794.88 | standard deviation: 411.178 | 0 0 0 3 0 2 1 2 2 2 1 2 0 2 1 0 0 2 5 4 9 17 44 50 81 129 167 247 315 394 660 852 995 1261 1505 1742 2309 2594 2616 3375 4130 3897 4426 4973 5171 6086 5994 5646 6624 7284 6490 6832 6913 6936 7494 6749 5912 6681 6896 5710 5755 5475 5408 5425 4686 3976 4385 4326 3406 3249 2955 2777 2774 2113 1869 1905 1841 1376 1329 1313 1154 1158 857 718 694 708 494 475 399 366 370 254 188 222 215 141 122 146 106 74 71 63 67 66 44 42 36 34 23 21 18 22 19 14 17 10 6 5 7 3 3 2 4 1 1 3 2 4 3 3 1 1 0 1 2 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 4653 count: 609344 average: 1797.16 | standard deviation: 410.863 | 0 1 4 5 4 6 2 4 4 5 2 2 2 5 3 0 0 5 14 16 27 51 107 122 215 335 460 726 921 1159 1751 2375 2649 3425 4174 4900 6420 7218 7254 9445 11586 11062 12469 13995 14673 17054 16802 15870 18686 20699 17999 18994 19413 19387 21085 19089 16858 19030 19579 16202 16183 15595 15096 15443 13366 11282 12279 12238 9510 9168 8697 7761 7851 6244 5187 5499 5272 4016 3804 3589 3157 3172 2479 2085 2035 1986 1476 1369 1118 1048 1026 717 599 673 615 413 382 363 283 235 214 166 192 191 110 116 95 78 68 55 46 53 51 34 33 21 17 15 18 13 14 5 6 5 4 9 3 7 8 5 5 5 4 2 3 3 2 0 0 0 0 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache_wCC: [binsize: 32 max: 4002 count: 8208 average: 1692.83 | standard deviation: 406.296 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 6 5 10 12 20 21 36 35 36 53 72 89 100 119 126 145 165 178 161 227 236 213 234 243 297 255 252 243 316 268 244 234 250 251 214 235 182 214 188 175 162 175 177 136 122 106 111 78 78 81 73 72 57 43 41 48 33 31 28 22 20 20 14 16 15 10 7 7 8 8 9 6 5 1 4 1 1 0 1 0 4 1 3 2 1 1 2 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_wCC_Times: 8156
|
||||
imcomplete_wCC_Times: 8208
|
||||
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average: 0 | standard deviation: 0 | 7 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 175 count: 7 average: 113.714 | standard deviation: 50.5833 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
imcomplete_dir_Times: 604388
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 4653 count: 392936 average: 1797.52 | standard deviation: 410.479 | 0 1 4 2 4 4 1 2 2 3 1 0 2 3 2 0 0 3 9 12 19 34 66 75 136 203 303 482 609 767 1090 1519 1664 2178 2685 3176 4112 4612 4654 6074 7444 7169 8063 9044 9500 10991 10831 10240 12073 13400 11535 12164 12489 12466 13560 12328 10926 12344 12645 10474 10409 10101 9677 9992 8674 7283 7879 7873 6097 5889 5722 4966 5062 4125 3303 3568 3414 2646 2464 2266 1993 2001 1620 1355 1343 1263 982 889 716 673 654 464 405 451 396 269 255 217 174 160 142 102 125 123 65 76 56 43 45 33 26 31 31 19 17 11 11 10 11 10 10 3 2 4 3 6 1 3 5 2 4 4 4 1 1 2 1 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 4002 count: 5323 average: 1694.26 | standard deviation: 402.526 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 3 2 6 10 9 14 25 22 22 38 44 48 57 75 80 101 107 120 106 160 151 122 155 152 188 178 164 160 203 176 156 136 162 162 135 160 124 146 134 114 101 121 122 94 74 63 71 52 50 45 55 44 38 33 25 28 23 19 19 16 11 14 6 12 7 5 5 6 4 4 7 2 2 0 3 0 1 0 0 0 3 0 2 0 1 1 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 4626 count: 211459 average: 1796.3 | standard deviation: 410.657 | 0 0 0 3 0 2 1 2 2 2 1 2 0 2 1 0 0 2 5 4 8 17 41 46 76 126 156 236 298 370 641 827 954 1208 1451 1681 2246 2524 2535 3292 4033 3799 4309 4840 5049 5950 5831 5528 6478 7142 6329 6686 6781 6781 7357 6612 5788 6561 6791 5591 5672 5382 5303 5336 4591 3895 4307 4250 3340 3204 2904 2723 2735 2068 1838 1874 1810 1339 1304 1290 1126 1141 838 703 684 700 482 464 393 361 364 248 185 216 208 137 115 144 105 74 67 62 66 65 40 39 36 34 23 21 17 22 19 14 16 10 6 5 7 3 3 2 4 1 1 3 2 4 3 3 1 1 0 1 2 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 3670 count: 2833 average: 1689.73 | standard deviation: 413.417 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 3 4 2 10 7 11 13 14 15 28 40 43 43 45 41 57 58 55 66 83 89 77 89 109 75 86 82 111 92 84 97 87 89 79 73 56 66 53 60 59 53 55 41 48 42 39 24 27 36 17 26 19 10 15 20 10 12 9 5 9 6 8 4 8 5 2 1 4 4 2 4 3 1 1 1 0 0 1 0 1 1 1 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
imcomplete_dir_Times: 609337
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 4653 count: 396132 average: 1797.62 | standard deviation: 410.802 | 0 1 4 2 4 4 1 2 2 3 1 0 2 3 2 0 0 3 9 12 19 34 66 75 138 208 303 486 617 778 1105 1538 1682 2204 2712 3202 4156 4665 4696 6128 7511 7231 8126 9112 9580 11057 10917 10301 12149 13497 11621 12254 12585 12549 13679 12429 11025 12423 12740 10559 10481 10181 9748 10071 8735 7347 7942 7955 6143 5943 5770 5020 5094 4157 3337 3604 3446 2660 2485 2288 2012 2019 1631 1373 1349 1282 990 899 721 683 660 467 413 455 403 273 261 218 177 161 144 103 126 126 67 76 59 44 45 34 28 31 32 20 17 11 11 10 11 10 11 3 2 4 3 6 1 3 5 2 4 4 4 1 1 2 1 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache_wCC: [binsize: 32 max: 4002 count: 5357 average: 1694.45 | standard deviation: 402.825 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 3 2 6 10 10 14 25 22 22 38 44 49 57 75 81 104 107 120 106 161 153 123 156 154 188 178 165 161 204 176 159 136 162 162 135 161 125 147 135 114 102 122 122 95 74 63 72 54 50 45 56 46 38 33 26 28 23 19 19 17 11 14 6 12 7 5 5 6 4 4 7 2 2 0 3 0 1 0 0 0 3 0 2 0 1 1 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 4626 count: 213212 average: 1796.29 | standard deviation: 410.975 | 0 0 0 3 0 2 1 2 2 2 1 2 0 2 1 0 0 2 5 4 8 17 41 47 77 127 157 240 304 381 646 837 967 1221 1462 1698 2264 2553 2558 3317 4075 3831 4343 4883 5093 5997 5885 5569 6537 7202 6378 6740 6828 6838 7406 6660 5833 6607 6839 5643 5702 5414 5348 5372 4631 3935 4337 4283 3367 3225 2927 2741 2757 2087 1850 1895 1826 1356 1319 1301 1145 1153 848 712 686 704 486 470 397 365 366 250 186 218 212 140 121 145 106 74 70 63 66 65 43 40 36 34 23 21 18 22 19 14 16 10 6 5 7 3 3 2 4 1 1 3 2 4 3 3 1 1 0 1 2 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_ST_L1Cache_wCC: [binsize: 32 max: 3670 count: 2851 average: 1689.78 | standard deviation: 412.794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 3 4 2 10 7 11 13 14 15 28 40 43 44 45 41 58 58 55 66 83 90 78 89 109 77 87 82 112 92 85 98 88 89 79 74 57 67 53 61 60 53 55 41 48 43 39 24 28 36 17 26 19 10 15 20 10 12 9 5 9 6 8 4 8 5 2 1 4 4 2 4 3 1 1 1 0 0 1 0 1 1 1 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
@ -66,11 +66,11 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 22 count: 1227672 average: 0.0072389 | standard deviation: 0.160195 | 1224232 923 774 826 891 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1227672 average: 0.0072389 | standard deviation: 0.160195 | 1224232 923 774 826 891 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 22 count: 1237687 average: 0.00723931 | standard deviation: 0.160084 | 1234218 929 781 837 896 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1237687 average: 0.00723931 | standard deviation: 0.160084 | 1234218 929 781 837 896 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 612551 average: 0.00100726 | standard deviation: 0.0517903 | 612293 37 99 106 16 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 22 count: 615121 average: 0.0134445 | standard deviation: 0.22016 | 611939 886 675 720 875 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 617552 average: 0.00101044 | standard deviation: 0.0517838 | 617290 38 102 106 16 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 22 count: 620135 average: 0.0134422 | standard deviation: 0.219998 | 616928 891 679 731 880 2 1 1 0 0 1 0 1 1 3 0 5 8 2 0 0 0 1 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
@ -82,337 +82,337 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1227672 average: 0.0072389
|
|||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 48
|
||||
user_time: 46
|
||||
system_time: 0
|
||||
page_reclaims: 10401
|
||||
page_faults: 3
|
||||
page_reclaims: 9935
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 480
|
||||
block_outputs: 232
|
||||
block_inputs: 0
|
||||
block_outputs: 200
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
total_msg_count_Control: 1837698 14701584
|
||||
total_msg_count_Data: 1820943 131107896
|
||||
total_msg_count_Response_Data: 1837653 132311016
|
||||
total_msg_count_Writeback_Control: 1845363 14762904
|
||||
total_msgs: 7341657 total_bytes: 292883400
|
||||
total_msg_count_Control: 1852692 14821536
|
||||
total_msg_count_Data: 1835849 132181128
|
||||
total_msg_count_Response_Data: 1852658 133391376
|
||||
total_msg_count_Writeback_Control: 1860405 14883240
|
||||
total_msgs: 7401604 total_bytes: 295277280
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 4.4737
|
||||
links_utilized_percent_switch_0_link_0: 4.46588 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 4.48153 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 4.47467
|
||||
links_utilized_percent_switch_0_link_0: 4.46681 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 4.48253 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 76730 5524560 [ 0 0 0 0 76730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 77065 616520 [ 0 0 0 77065 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 76731 613848 [ 0 0 76731 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 76026 5473872 [ 0 0 76026 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 1040 74880 [ 0 0 0 0 1040 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 77375 5571000 [ 0 0 0 0 77375 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 77713 621704 [ 0 0 0 77713 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 77377 619016 [ 0 0 77377 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 76667 5520024 [ 0 0 76667 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Data: 1048 75456 [ 0 0 0 0 1048 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 4.46364
|
||||
links_utilized_percent_switch_1_link_0: 4.45628 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 4.471 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 4.4635
|
||||
links_utilized_percent_switch_1_link_0: 4.45612 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 4.47087 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 76567 5512824 [ 0 0 0 0 76567 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 76882 615056 [ 0 0 0 76882 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 76569 612552 [ 0 0 76569 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Data: 75853 5461416 [ 0 0 75853 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1030 74160 [ 0 0 0 0 1030 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 77192 5557824 [ 0 0 0 0 77192 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 77508 620064 [ 0 0 0 77508 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 77193 617544 [ 0 0 77193 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Data: 76469 5505768 [ 0 0 76469 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1042 75024 [ 0 0 0 0 1042 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 4.44318
|
||||
links_utilized_percent_switch_2_link_0: 4.43569 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 4.45067 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 4.44221
|
||||
links_utilized_percent_switch_2_link_0: 4.43473 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 4.44968 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 76213 5487336 [ 0 0 0 0 76213 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 76529 612232 [ 0 0 0 76529 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 76216 609728 [ 0 0 76216 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 75497 5435784 [ 0 0 75497 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1037 74664 [ 0 0 0 0 1037 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 76821 5531112 [ 0 0 0 0 76821 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 77139 617112 [ 0 0 0 77139 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 76824 614592 [ 0 0 76824 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 76104 5479488 [ 0 0 76104 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1040 74880 [ 0 0 0 0 1040 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 2
|
||||
switch_3_outlinks: 2
|
||||
links_utilized_percent_switch_3: 4.44459
|
||||
links_utilized_percent_switch_3_link_0: 4.43679 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 4.45238 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3: 4.44269
|
||||
links_utilized_percent_switch_3_link_0: 4.43483 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 4.45054 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 76230 5488560 [ 0 0 0 0 76230 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 76565 612520 [ 0 0 0 76565 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 76231 609848 [ 0 0 76231 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 75505 5436360 [ 0 0 75505 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1060 76320 [ 0 0 0 0 1060 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 76821 5531112 [ 0 0 0 0 76821 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 77157 617256 [ 0 0 0 77157 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 76823 614584 [ 0 0 76823 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 76096 5478912 [ 0 0 76096 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1065 76680 [ 0 0 0 0 1065 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_4_inlinks: 2
|
||||
switch_4_outlinks: 2
|
||||
links_utilized_percent_switch_4: 4.47109
|
||||
links_utilized_percent_switch_4_link_0: 4.46353 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 4.47864 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4: 4.47158
|
||||
links_utilized_percent_switch_4_link_0: 4.46407 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_4_link_1: 4.4791 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 76691 5521752 [ 0 0 0 0 76691 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 77013 616104 [ 0 0 0 77013 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 76694 613552 [ 0 0 76694 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Data: 76026 5473872 [ 0 0 76026 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 989 71208 [ 0 0 0 0 989 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Response_Data: 77329 5567688 [ 0 0 0 0 77329 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_0_Writeback_Control: 77652 621216 [ 0 0 0 77652 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Control: 77331 618648 [ 0 0 77331 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Data: 76659 5519448 [ 0 0 76659 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_4_link_1_Response_Data: 995 71640 [ 0 0 0 0 995 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_5_inlinks: 2
|
||||
switch_5_outlinks: 2
|
||||
links_utilized_percent_switch_5: 4.47561
|
||||
links_utilized_percent_switch_5_link_0: 4.46773 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 4.4835 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5: 4.47536
|
||||
links_utilized_percent_switch_5_link_0: 4.46739 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_5_link_1: 4.48332 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 76762 5526864 [ 0 0 0 0 76762 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 77096 616768 [ 0 0 0 77096 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 76764 614112 [ 0 0 76764 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Data: 76109 5479848 [ 0 0 76109 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 991 71352 [ 0 0 0 0 991 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Response_Data: 77385 5571720 [ 0 0 0 0 77385 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_0_Writeback_Control: 77723 621784 [ 0 0 0 77723 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Control: 77389 619112 [ 0 0 77389 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Data: 76728 5524416 [ 0 0 76728 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_5_link_1_Response_Data: 1001 72072 [ 0 0 0 0 1001 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_6_inlinks: 2
|
||||
switch_6_outlinks: 2
|
||||
links_utilized_percent_switch_6: 4.47463
|
||||
links_utilized_percent_switch_6_link_0: 4.46749 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 4.48176 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6: 4.47242
|
||||
links_utilized_percent_switch_6_link_0: 4.4653 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_6_link_1: 4.47954 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 76761 5526792 [ 0 0 0 0 76761 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 77064 616512 [ 0 0 0 77064 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 76763 614104 [ 0 0 76763 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Data: 76075 5477400 [ 0 0 76075 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 992 71424 [ 0 0 0 0 992 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Response_Data: 77352 5569344 [ 0 0 0 0 77352 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_0_Writeback_Control: 77658 621264 [ 0 0 0 77658 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Control: 77354 618832 [ 0 0 77354 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Data: 76662 5519664 [ 0 0 76662 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_6_link_1_Response_Data: 998 71856 [ 0 0 0 0 998 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_7_inlinks: 2
|
||||
switch_7_outlinks: 2
|
||||
links_utilized_percent_switch_7: 4.46521
|
||||
links_utilized_percent_switch_7_link_0: 4.45799 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 4.47243 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7: 4.46812
|
||||
links_utilized_percent_switch_7_link_0: 4.46098 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_7_link_1: 4.47526 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 76597 5514984 [ 0 0 0 0 76597 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 76907 615256 [ 0 0 0 76907 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 76598 612784 [ 0 0 76598 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Data: 75890 5464080 [ 0 0 75890 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 1017 73224 [ 0 0 0 0 1017 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Response_Data: 77277 5563944 [ 0 0 0 0 77277 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_0_Writeback_Control: 77585 620680 [ 0 0 0 77585 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Control: 77277 618216 [ 0 0 77277 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Data: 76568 5512896 [ 0 0 76568 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_7_link_1_Response_Data: 1019 73368 [ 0 0 0 0 1019 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_8_inlinks: 2
|
||||
switch_8_outlinks: 2
|
||||
links_utilized_percent_switch_8: 35.2846
|
||||
links_utilized_percent_switch_8_link_0: 35.3449 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 35.2243 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8: 35.2841
|
||||
links_utilized_percent_switch_8_link_0: 35.3443 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_8_link_1: 35.224 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_8_link_0_Control: 612566 4900528 [ 0 0 612566 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Data: 606981 43702632 [ 0 0 606981 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 604395 43516440 [ 0 0 0 0 604395 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 615121 4920968 [ 0 0 0 615121 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Control: 617562 4940496 [ 0 0 617562 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_0_Data: 611948 44060256 [ 0 0 611948 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Response_Data: 609345 43872840 [ 0 0 0 0 609345 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_8_link_1_Writeback_Control: 620135 4961080 [ 0 0 0 620135 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_9_inlinks: 9
|
||||
switch_9_outlinks: 9
|
||||
links_utilized_percent_switch_9: 7.88847
|
||||
links_utilized_percent_switch_9_link_0: 4.46588 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 4.45628 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 4.43569 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 4.43679 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 4.46353 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 4.46773 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 4.46749 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 4.45799 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 35.3449 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9: 7.88828
|
||||
links_utilized_percent_switch_9_link_0: 4.46681 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_1: 4.45612 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_2: 4.43473 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_3: 4.43483 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_4: 4.46408 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_5: 4.46739 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_6: 4.4653 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_7: 4.46098 bw: 16000 base_latency: 1
|
||||
links_utilized_percent_switch_9_link_8: 35.3443 bw: 16000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 76730 5524560 [ 0 0 0 0 76730 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 77065 616520 [ 0 0 0 77065 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 76567 5512824 [ 0 0 0 0 76567 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 76882 615056 [ 0 0 0 76882 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 76213 5487336 [ 0 0 0 0 76213 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 76529 612232 [ 0 0 0 76529 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 76230 5488560 [ 0 0 0 0 76230 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 76565 612520 [ 0 0 0 76565 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 76691 5521752 [ 0 0 0 0 76691 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 77013 616104 [ 0 0 0 77013 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 76762 5526864 [ 0 0 0 0 76762 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 77096 616768 [ 0 0 0 77096 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 76761 5526792 [ 0 0 0 0 76761 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 77064 616512 [ 0 0 0 77064 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 76597 5514984 [ 0 0 0 0 76597 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 76907 615256 [ 0 0 0 76907 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 612566 4900528 [ 0 0 612566 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Data: 606981 43702632 [ 0 0 606981 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Response_Data: 77375 5571000 [ 0 0 0 0 77375 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_0_Writeback_Control: 77713 621704 [ 0 0 0 77713 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Response_Data: 77192 5557824 [ 0 0 0 0 77192 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_1_Writeback_Control: 77508 620064 [ 0 0 0 77508 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Response_Data: 76821 5531112 [ 0 0 0 0 76821 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_2_Writeback_Control: 77139 617112 [ 0 0 0 77139 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Response_Data: 76821 5531112 [ 0 0 0 0 76821 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_3_Writeback_Control: 77157 617256 [ 0 0 0 77157 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Response_Data: 77330 5567760 [ 0 0 0 0 77330 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_4_Writeback_Control: 77652 621216 [ 0 0 0 77652 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Response_Data: 77385 5571720 [ 0 0 0 0 77385 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_5_Writeback_Control: 77723 621784 [ 0 0 0 77723 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Response_Data: 77352 5569344 [ 0 0 0 0 77352 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_6_Writeback_Control: 77658 621264 [ 0 0 0 77658 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Response_Data: 77277 5563944 [ 0 0 0 0 77277 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_7_Writeback_Control: 77585 620680 [ 0 0 0 77585 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Control: 617562 4940496 [ 0 0 617562 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_9_link_8_Data: 611948 44060256 [ 0 0 611948 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.l1_cntrl0.cacheMemory
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 76731
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 76731
|
||||
system.l1_cntrl0.cacheMemory_total_misses: 77377
|
||||
system.l1_cntrl0.cacheMemory_total_demand_misses: 77377
|
||||
system.l1_cntrl0.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 65.0962%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 34.9038%
|
||||
system.l1_cntrl0.cacheMemory_request_type_LD: 65.0969%
|
||||
system.l1_cntrl0.cacheMemory_request_type_ST: 34.9031%
|
||||
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 76731 100%
|
||||
system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 77377 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load [49593 49882 49908 50150 49949 49848 49638 49304 ] 398272
|
||||
Load [50004 50305 50279 50578 50370 50258 50037 49672 ] 401503
|
||||
Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
Store [27101 26882 26855 26448 26782 26721 26578 26927 ] 214294
|
||||
Data [76691 76762 76761 76597 76730 76567 76213 76230 ] 612551
|
||||
Fwd_GETX [989 991 992 1017 1040 1030 1037 1060 ] 8156
|
||||
Store [27327 27084 27075 26703 27007 26935 26787 27153 ] 216071
|
||||
Data [77329 77385 77352 77277 77375 77192 76821 76821 ] 617552
|
||||
Fwd_GETX [995 1001 998 1019 1048 1042 1040 1065 ] 8208
|
||||
Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
Replacement [76690 76760 76759 76594 76727 76565 76212 76227 ] 612534
|
||||
Writeback_Ack [75699 75765 75764 75577 75686 75534 75170 75167 ] 604362
|
||||
Writeback_Nack [325 340 308 313 339 318 322 338 ] 2603
|
||||
Replacement [77327 77385 77350 77277 77373 77189 76820 76821 ] 617542
|
||||
Writeback_Ack [76330 76378 76350 76253 76323 76144 75775 75751 ] 609304
|
||||
Writeback_Nack [327 344 310 313 342 322 324 341 ] 2623
|
||||
|
||||
- Transitions -
|
||||
I Load [49593 49882 49908 50150 49949 49848 49638 49304 ] 398272
|
||||
I Load [50004 50305 50279 50578 50370 50258 50037 49672 ] 401503
|
||||
I Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
I Store [27101 26882 26855 26448 26782 26721 26578 26927 ] 214294
|
||||
I Store [27327 27084 27075 26703 27007 26935 26787 27153 ] 216071
|
||||
I Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
I Replacement [664 651 684 704 701 712 715 722 ] 5553
|
||||
I Replacement [668 657 688 706 706 720 716 724 ] 5585
|
||||
|
||||
II Writeback_Nack [325 340 308 313 339 318 322 338 ] 2603
|
||||
II Writeback_Nack [327 344 310 313 342 322 324 341 ] 2623
|
||||
|
||||
M Load [0 0 0 0 0 0 0 0 ] 0
|
||||
M Ifetch [0 0 0 0 0 0 0 0 ] 0
|
||||
M Store [0 0 0 0 0 0 0 0 ] 0
|
||||
M Fwd_GETX [664 651 684 704 701 712 715 722 ] 5553
|
||||
M Fwd_GETX [668 657 688 706 706 720 716 724 ] 5585
|
||||
M Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
M Replacement [76026 76109 76075 75890 76026 75853 75497 75505 ] 606981
|
||||
M Replacement [76659 76728 76662 76571 76667 76469 76104 76097 ] 611957
|
||||
|
||||
MI Fwd_GETX [325 340 308 313 339 318 322 338 ] 2603
|
||||
MI Fwd_GETX [327 344 310 313 342 322 324 341 ] 2623
|
||||
MI Inv [0 0 0 0 0 0 0 0 ] 0
|
||||
MI Writeback_Ack [75699 75765 75764 75577 75686 75534 75170 75167 ] 604362
|
||||
MI Writeback_Ack [76330 76378 76350 76253 76323 76144 75775 75751 ] 609304
|
||||
MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
|
||||
|
||||
IS Data [49590 49880 49906 50150 49949 49846 49635 49303 ] 398259
|
||||
IS Data [50002 50301 50278 50576 50370 50258 50035 49669 ] 401489
|
||||
|
||||
IM Data [27101 26882 26855 26447 26781 26721 26578 26927 ] 214292
|
||||
IM Data [27327 27084 27074 26701 27005 26934 26786 27152 ] 216063
|
||||
|
||||
Cache Stats: system.l1_cntrl1.cacheMemory
|
||||
system.l1_cntrl1.cacheMemory_total_misses: 76569
|
||||
system.l1_cntrl1.cacheMemory_total_demand_misses: 76569
|
||||
system.l1_cntrl1.cacheMemory_total_misses: 77193
|
||||
system.l1_cntrl1.cacheMemory_total_demand_misses: 77193
|
||||
system.l1_cntrl1.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl1.cacheMemory_request_type_LD: 65.1021%
|
||||
system.l1_cntrl1.cacheMemory_request_type_ST: 34.8979%
|
||||
system.l1_cntrl1.cacheMemory_request_type_LD: 65.1069%
|
||||
system.l1_cntrl1.cacheMemory_request_type_ST: 34.8931%
|
||||
|
||||
system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 76569 100%
|
||||
system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 77193 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl2.cacheMemory
|
||||
system.l1_cntrl2.cacheMemory_total_misses: 76216
|
||||
system.l1_cntrl2.cacheMemory_total_demand_misses: 76216
|
||||
system.l1_cntrl2.cacheMemory_total_misses: 76824
|
||||
system.l1_cntrl2.cacheMemory_total_demand_misses: 76824
|
||||
system.l1_cntrl2.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl2.cacheMemory_request_type_LD: 65.1281%
|
||||
system.l1_cntrl2.cacheMemory_request_type_ST: 34.8719%
|
||||
system.l1_cntrl2.cacheMemory_request_type_LD: 65.132%
|
||||
system.l1_cntrl2.cacheMemory_request_type_ST: 34.868%
|
||||
|
||||
system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76216 100%
|
||||
system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 76824 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl3.cacheMemory
|
||||
system.l1_cntrl3.cacheMemory_total_misses: 76231
|
||||
system.l1_cntrl3.cacheMemory_total_demand_misses: 76231
|
||||
system.l1_cntrl3.cacheMemory_total_misses: 76825
|
||||
system.l1_cntrl3.cacheMemory_total_demand_misses: 76825
|
||||
system.l1_cntrl3.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl3.cacheMemory_request_type_LD: 64.6771%
|
||||
system.l1_cntrl3.cacheMemory_request_type_ST: 35.3229%
|
||||
system.l1_cntrl3.cacheMemory_request_type_LD: 64.656%
|
||||
system.l1_cntrl3.cacheMemory_request_type_ST: 35.344%
|
||||
|
||||
system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76231 100%
|
||||
system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 76825 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl4.cacheMemory
|
||||
system.l1_cntrl4.cacheMemory_total_misses: 76694
|
||||
system.l1_cntrl4.cacheMemory_total_demand_misses: 76694
|
||||
system.l1_cntrl4.cacheMemory_total_misses: 77331
|
||||
system.l1_cntrl4.cacheMemory_total_demand_misses: 77331
|
||||
system.l1_cntrl4.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl4.cacheMemory_request_type_LD: 64.6635%
|
||||
system.l1_cntrl4.cacheMemory_request_type_ST: 35.3365%
|
||||
system.l1_cntrl4.cacheMemory_request_type_LD: 64.6623%
|
||||
system.l1_cntrl4.cacheMemory_request_type_ST: 35.3377%
|
||||
|
||||
system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 76694 100%
|
||||
system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor: 77331 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl5.cacheMemory
|
||||
system.l1_cntrl5.cacheMemory_total_misses: 76764
|
||||
system.l1_cntrl5.cacheMemory_total_demand_misses: 76764
|
||||
system.l1_cntrl5.cacheMemory_total_misses: 77389
|
||||
system.l1_cntrl5.cacheMemory_total_demand_misses: 77389
|
||||
system.l1_cntrl5.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl5.cacheMemory_request_type_LD: 64.981%
|
||||
system.l1_cntrl5.cacheMemory_request_type_ST: 35.019%
|
||||
system.l1_cntrl5.cacheMemory_request_type_LD: 65.0028%
|
||||
system.l1_cntrl5.cacheMemory_request_type_ST: 34.9972%
|
||||
|
||||
system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 76764 100%
|
||||
system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor: 77389 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl6.cacheMemory
|
||||
system.l1_cntrl6.cacheMemory_total_misses: 76763
|
||||
system.l1_cntrl6.cacheMemory_total_demand_misses: 76763
|
||||
system.l1_cntrl6.cacheMemory_total_misses: 77354
|
||||
system.l1_cntrl6.cacheMemory_total_demand_misses: 77354
|
||||
system.l1_cntrl6.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl6.cacheMemory_request_type_LD: 65.0157%
|
||||
system.l1_cntrl6.cacheMemory_request_type_ST: 34.9843%
|
||||
system.l1_cntrl6.cacheMemory_request_type_LD: 64.9986%
|
||||
system.l1_cntrl6.cacheMemory_request_type_ST: 35.0014%
|
||||
|
||||
system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 76763 100%
|
||||
system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor: 77354 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl7.cacheMemory
|
||||
system.l1_cntrl7.cacheMemory_total_misses: 76598
|
||||
system.l1_cntrl7.cacheMemory_total_demand_misses: 76598
|
||||
system.l1_cntrl7.cacheMemory_total_misses: 77281
|
||||
system.l1_cntrl7.cacheMemory_total_demand_misses: 77281
|
||||
system.l1_cntrl7.cacheMemory_total_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0
|
||||
system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0
|
||||
|
||||
system.l1_cntrl7.cacheMemory_request_type_LD: 65.4717%
|
||||
system.l1_cntrl7.cacheMemory_request_type_ST: 34.5283%
|
||||
system.l1_cntrl7.cacheMemory_request_type_LD: 65.4469%
|
||||
system.l1_cntrl7.cacheMemory_request_type_ST: 34.5531%
|
||||
|
||||
system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 76598 100%
|
||||
system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor: 77281 100%
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1208787
|
||||
memory_reads: 604397
|
||||
memory_writes: 604365
|
||||
memory_refreshes: 59684
|
||||
memory_total_request_delays: 86764072
|
||||
memory_delays_per_request: 71.7778
|
||||
memory_delays_in_input_queue: 1509968
|
||||
memory_delays_behind_head_of_bank_queue: 39767134
|
||||
memory_delays_stalled_at_head_of_bank_queue: 45486970
|
||||
memory_stalls_for_bank_busy: 7019107
|
||||
memory_total_requests: 1218678
|
||||
memory_reads: 609346
|
||||
memory_writes: 609308
|
||||
memory_refreshes: 60173
|
||||
memory_total_request_delays: 87480258
|
||||
memory_delays_per_request: 71.7829
|
||||
memory_delays_in_input_queue: 1522193
|
||||
memory_delays_behind_head_of_bank_queue: 40100008
|
||||
memory_delays_stalled_at_head_of_bank_queue: 45858057
|
||||
memory_stalls_for_bank_busy: 7076344
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 11191838
|
||||
memory_stalls_for_arbitration: 9120916
|
||||
memory_stalls_for_bus: 12483705
|
||||
memory_stalls_for_anti_starvation: 11282671
|
||||
memory_stalls_for_arbitration: 9195209
|
||||
memory_stalls_for_bus: 12585722
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 4604021
|
||||
memory_stalls_for_read_read_turnaround: 1067383
|
||||
accesses_per_bank: 38081 37280 38059 37993 37808 37669 38264 38058 37708 37676 37829 37380 37422 38256 37284 38186 37917 37744 38412 38248 37780 37359 37760 37766 37532 37908 37452 37826 37364 37732 37412 37622
|
||||
memory_stalls_for_read_write_turnaround: 4642017
|
||||
memory_stalls_for_read_read_turnaround: 1076094
|
||||
accesses_per_bank: 38404 37646 38381 38273 38109 38021 38580 38357 38057 38004 38123 37658 37751 38546 37560 38514 38232 38045 38749 38589 38066 37687 38032 38060 37804 38206 37726 38148 37682 38049 37701 37918
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX [784980 ] 784980
|
||||
GETX [791175 ] 791175
|
||||
GETS [0 ] 0
|
||||
PUTX [604378 ] 604378
|
||||
PUTX_NotOwner [2603 ] 2603
|
||||
PUTX [609324 ] 609324
|
||||
PUTX_NotOwner [2623 ] 2623
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
Memory_Data [604396 ] 604396
|
||||
Memory_Ack [604362 ] 604362
|
||||
Memory_Data [609345 ] 609345
|
||||
Memory_Ack [609304 ] 609304
|
||||
|
||||
- Transitions -
|
||||
I GETX [604409 ] 604409
|
||||
I GETX [609354 ] 609354
|
||||
I PUTX_NotOwner [0 ] 0
|
||||
I DMA_READ [0 ] 0
|
||||
I DMA_WRITE [0 ] 0
|
||||
|
||||
M GETX [8156 ] 8156
|
||||
M PUTX [604378 ] 604378
|
||||
M PUTX_NotOwner [2603 ] 2603
|
||||
M GETX [8208 ] 8208
|
||||
M PUTX [609324 ] 609324
|
||||
M PUTX_NotOwner [2623 ] 2623
|
||||
M DMA_READ [0 ] 0
|
||||
M DMA_WRITE [0 ] 0
|
||||
|
||||
|
@ -428,21 +428,21 @@ M_DWRI Memory_Ack [0 ] 0
|
|||
M_DRDI GETX [0 ] 0
|
||||
M_DRDI Memory_Ack [0 ] 0
|
||||
|
||||
IM GETX [64832 ] 64832
|
||||
IM GETX [65257 ] 65257
|
||||
IM GETS [0 ] 0
|
||||
IM PUTX [0 ] 0
|
||||
IM PUTX_NotOwner [0 ] 0
|
||||
IM DMA_READ [0 ] 0
|
||||
IM DMA_WRITE [0 ] 0
|
||||
IM Memory_Data [604396 ] 604396
|
||||
IM Memory_Data [609345 ] 609345
|
||||
|
||||
MI GETX [107583 ] 107583
|
||||
MI GETX [108356 ] 108356
|
||||
MI GETS [0 ] 0
|
||||
MI PUTX [0 ] 0
|
||||
MI PUTX_NotOwner [0 ] 0
|
||||
MI DMA_READ [0 ] 0
|
||||
MI DMA_WRITE [0 ] 0
|
||||
MI Memory_Ack [604362 ] 604362
|
||||
MI Memory_Ack [609304 ] 609304
|
||||
|
||||
ID GETX [0 ] 0
|
||||
ID GETS [0 ] 0
|
||||
|
|
|
@ -6,77 +6,77 @@ Warning: rounding error > tolerance
|
|||
0.072760 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.072760 rounded to 0
|
||||
system.cpu4: completed 10000 read, 5220 write accesses @847627
|
||||
system.cpu7: completed 10000 read, 5333 write accesses @853307
|
||||
system.cpu1: completed 10000 read, 5223 write accesses @856720
|
||||
system.cpu2: completed 10000 read, 5343 write accesses @856757
|
||||
system.cpu0: completed 10000 read, 5346 write accesses @859240
|
||||
system.cpu3: completed 10000 read, 5325 write accesses @862609
|
||||
system.cpu5: completed 10000 read, 5417 write accesses @867929
|
||||
system.cpu6: completed 10000 read, 5429 write accesses @870556
|
||||
system.cpu7: completed 20000 read, 10546 write accesses @1710362
|
||||
system.cpu3: completed 20000 read, 10676 write accesses @1715625
|
||||
system.cpu2: completed 20000 read, 10865 write accesses @1717913
|
||||
system.cpu1: completed 20000 read, 10472 write accesses @1718245
|
||||
system.cpu4: completed 20000 read, 10710 write accesses @1723388
|
||||
system.cpu0: completed 20000 read, 10695 write accesses @1731500
|
||||
system.cpu6: completed 20000 read, 10923 write accesses @1732721
|
||||
system.cpu5: completed 20000 read, 10714 write accesses @1741949
|
||||
system.cpu3: completed 30000 read, 16111 write accesses @2561534
|
||||
system.cpu7: completed 30000 read, 15801 write accesses @2564909
|
||||
system.cpu0: completed 30000 read, 15963 write accesses @2570530
|
||||
system.cpu2: completed 30000 read, 16167 write accesses @2572444
|
||||
system.cpu4: completed 30000 read, 16049 write accesses @2589273
|
||||
system.cpu6: completed 30000 read, 16204 write accesses @2590810
|
||||
system.cpu5: completed 30000 read, 15952 write accesses @2600828
|
||||
system.cpu1: completed 30000 read, 15999 write accesses @2614055
|
||||
system.cpu7: completed 40000 read, 21145 write accesses @3411914
|
||||
system.cpu0: completed 40000 read, 21350 write accesses @3420253
|
||||
system.cpu2: completed 40000 read, 21529 write accesses @3428587
|
||||
system.cpu3: completed 40000 read, 21460 write accesses @3434840
|
||||
system.cpu6: completed 40000 read, 21523 write accesses @3443024
|
||||
system.cpu4: completed 40000 read, 21533 write accesses @3467265
|
||||
system.cpu5: completed 40000 read, 21305 write accesses @3470138
|
||||
system.cpu1: completed 40000 read, 21461 write accesses @3492145
|
||||
system.cpu7: completed 50000 read, 26466 write accesses @4272276
|
||||
system.cpu2: completed 50000 read, 26738 write accesses @4280117
|
||||
system.cpu0: completed 50000 read, 26773 write accesses @4295924
|
||||
system.cpu6: completed 50000 read, 26837 write accesses @4299550
|
||||
system.cpu3: completed 50000 read, 26845 write accesses @4312607
|
||||
system.cpu5: completed 50000 read, 26698 write accesses @4316933
|
||||
system.cpu4: completed 50000 read, 26954 write accesses @4344468
|
||||
system.cpu1: completed 50000 read, 26769 write accesses @4358867
|
||||
system.cpu7: completed 60000 read, 31755 write accesses @5113250
|
||||
system.cpu0: completed 60000 read, 32149 write accesses @5156117
|
||||
system.cpu2: completed 60000 read, 32096 write accesses @5160599
|
||||
system.cpu6: completed 60000 read, 32168 write accesses @5173313
|
||||
system.cpu3: completed 60000 read, 32243 write accesses @5178563
|
||||
system.cpu5: completed 60000 read, 32247 write accesses @5183771
|
||||
system.cpu4: completed 60000 read, 32381 write accesses @5220290
|
||||
system.cpu1: completed 60000 read, 32294 write accesses @5220865
|
||||
system.cpu7: completed 70000 read, 37125 write accesses @5977718
|
||||
system.cpu0: completed 70000 read, 37636 write accesses @6026353
|
||||
system.cpu6: completed 70000 read, 37517 write accesses @6027404
|
||||
system.cpu2: completed 70000 read, 37549 write accesses @6039275
|
||||
system.cpu3: completed 70000 read, 37632 write accesses @6040322
|
||||
system.cpu5: completed 70000 read, 37704 write accesses @6061913
|
||||
system.cpu1: completed 70000 read, 37680 write accesses @6066326
|
||||
system.cpu4: completed 70000 read, 37794 write accesses @6080683
|
||||
system.cpu7: completed 80000 read, 42401 write accesses @6837718
|
||||
system.cpu0: completed 80000 read, 43037 write accesses @6872986
|
||||
system.cpu6: completed 80000 read, 42861 write accesses @6886837
|
||||
system.cpu3: completed 80000 read, 43022 write accesses @6895964
|
||||
system.cpu2: completed 80000 read, 43017 write accesses @6904754
|
||||
system.cpu5: completed 80000 read, 43129 write accesses @6910157
|
||||
system.cpu1: completed 80000 read, 42955 write accesses @6929917
|
||||
system.cpu4: completed 80000 read, 43333 write accesses @6955798
|
||||
system.cpu7: completed 90000 read, 47777 write accesses @7715699
|
||||
system.cpu0: completed 90000 read, 48512 write accesses @7730512
|
||||
system.cpu6: completed 90000 read, 48227 write accesses @7747760
|
||||
system.cpu1: completed 90000 read, 48224 write accesses @7775090
|
||||
system.cpu2: completed 90000 read, 48474 write accesses @7775105
|
||||
system.cpu3: completed 90000 read, 48528 write accesses @7778761
|
||||
system.cpu5: completed 90000 read, 48627 write accesses @7786116
|
||||
system.cpu4: completed 90000 read, 48988 write accesses @7814863
|
||||
system.cpu7: completed 100000 read, 53297 write accesses @8594451
|
||||
system.cpu4: completed 10000 read, 5267 write accesses @855219
|
||||
system.cpu7: completed 10000 read, 5381 write accesses @861031
|
||||
system.cpu1: completed 10000 read, 5262 write accesses @863126
|
||||
system.cpu2: completed 10000 read, 5381 write accesses @864460
|
||||
system.cpu0: completed 10000 read, 5401 write accesses @867419
|
||||
system.cpu3: completed 10000 read, 5382 write accesses @869141
|
||||
system.cpu5: completed 10000 read, 5455 write accesses @872828
|
||||
system.cpu6: completed 10000 read, 5482 write accesses @879392
|
||||
system.cpu7: completed 20000 read, 10628 write accesses @1724117
|
||||
system.cpu2: completed 20000 read, 10953 write accesses @1730360
|
||||
system.cpu1: completed 20000 read, 10550 write accesses @1730621
|
||||
system.cpu3: completed 20000 read, 10808 write accesses @1733195
|
||||
system.cpu4: completed 20000 read, 10816 write accesses @1737229
|
||||
system.cpu0: completed 20000 read, 10790 write accesses @1746955
|
||||
system.cpu6: completed 20000 read, 11016 write accesses @1749077
|
||||
system.cpu5: completed 20000 read, 10800 write accesses @1759742
|
||||
system.cpu3: completed 30000 read, 16255 write accesses @2586824
|
||||
system.cpu7: completed 30000 read, 15936 write accesses @2587214
|
||||
system.cpu0: completed 30000 read, 16091 write accesses @2589409
|
||||
system.cpu2: completed 30000 read, 16288 write accesses @2595682
|
||||
system.cpu4: completed 30000 read, 16193 write accesses @2610317
|
||||
system.cpu6: completed 30000 read, 16368 write accesses @2614352
|
||||
system.cpu5: completed 30000 read, 16095 write accesses @2624564
|
||||
system.cpu1: completed 30000 read, 16153 write accesses @2637701
|
||||
system.cpu7: completed 40000 read, 21310 write accesses @3438977
|
||||
system.cpu0: completed 40000 read, 21543 write accesses @3451234
|
||||
system.cpu2: completed 40000 read, 21712 write accesses @3460847
|
||||
system.cpu3: completed 40000 read, 21652 write accesses @3468818
|
||||
system.cpu6: completed 40000 read, 21709 write accesses @3479513
|
||||
system.cpu4: completed 40000 read, 21724 write accesses @3497567
|
||||
system.cpu5: completed 40000 read, 21477 write accesses @3498797
|
||||
system.cpu1: completed 40000 read, 21640 write accesses @3521390
|
||||
system.cpu7: completed 50000 read, 26683 write accesses @4309027
|
||||
system.cpu2: completed 50000 read, 27008 write accesses @4319999
|
||||
system.cpu0: completed 50000 read, 26993 write accesses @4330940
|
||||
system.cpu6: completed 50000 read, 27072 write accesses @4336165
|
||||
system.cpu3: completed 50000 read, 27085 write accesses @4352827
|
||||
system.cpu5: completed 50000 read, 26964 write accesses @4357459
|
||||
system.cpu4: completed 50000 read, 27198 write accesses @4384075
|
||||
system.cpu1: completed 50000 read, 27029 write accesses @4398757
|
||||
system.cpu7: completed 60000 read, 32063 write accesses @5160248
|
||||
system.cpu0: completed 60000 read, 32443 write accesses @5203475
|
||||
system.cpu2: completed 60000 read, 32367 write accesses @5205683
|
||||
system.cpu6: completed 60000 read, 32517 write accesses @5225171
|
||||
system.cpu3: completed 60000 read, 32534 write accesses @5227022
|
||||
system.cpu5: completed 60000 read, 32552 write accesses @5229640
|
||||
system.cpu1: completed 60000 read, 32592 write accesses @5258417
|
||||
system.cpu4: completed 60000 read, 32682 write accesses @5263781
|
||||
system.cpu7: completed 70000 read, 37467 write accesses @6033043
|
||||
system.cpu0: completed 70000 read, 37995 write accesses @6081225
|
||||
system.cpu6: completed 70000 read, 37873 write accesses @6089309
|
||||
system.cpu3: completed 70000 read, 38002 write accesses @6091981
|
||||
system.cpu2: completed 70000 read, 37862 write accesses @6093259
|
||||
system.cpu5: completed 70000 read, 38035 write accesses @6114916
|
||||
system.cpu1: completed 70000 read, 38024 write accesses @6119174
|
||||
system.cpu4: completed 70000 read, 38117 write accesses @6129370
|
||||
system.cpu7: completed 80000 read, 42779 write accesses @6903893
|
||||
system.cpu0: completed 80000 read, 43420 write accesses @6927865
|
||||
system.cpu6: completed 80000 read, 43280 write accesses @6952004
|
||||
system.cpu3: completed 80000 read, 43445 write accesses @6966407
|
||||
system.cpu5: completed 80000 read, 43493 write accesses @6966458
|
||||
system.cpu2: completed 80000 read, 43456 write accesses @6967571
|
||||
system.cpu1: completed 80000 read, 43311 write accesses @6981707
|
||||
system.cpu4: completed 80000 read, 43712 write accesses @7010960
|
||||
system.cpu7: completed 90000 read, 48212 write accesses @7781504
|
||||
system.cpu0: completed 90000 read, 49018 write accesses @7809551
|
||||
system.cpu6: completed 90000 read, 48768 write accesses @7821401
|
||||
system.cpu2: completed 90000 read, 48919 write accesses @7841558
|
||||
system.cpu1: completed 90000 read, 48631 write accesses @7843811
|
||||
system.cpu3: completed 90000 read, 49017 write accesses @7850422
|
||||
system.cpu5: completed 90000 read, 49075 write accesses @7851926
|
||||
system.cpu4: completed 90000 read, 49432 write accesses @7874435
|
||||
system.cpu7: completed 100000 read, 53796 write accesses @8664886
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Sep 1 2012 13:41:29
|
||||
gem5 started Sep 1 2012 13:47:40
|
||||
gem5 executing on doudou.cs.wisc.edu
|
||||
gem5 compiled Nov 10 2012 16:31:57
|
||||
gem5 started Nov 10 2012 16:32:41
|
||||
gem5 executing on ribera.cs.wisc.edu
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 8642753 because maximum number of loads reached
|
||||
Exiting @ tick 8664886 because maximum number of loads reached
|
||||
|
|
|
@ -1,12 +1,12 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.008594 # Number of seconds simulated
|
||||
sim_ticks 8594451 # Number of ticks simulated
|
||||
final_tick 8594451 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.008665 # Number of seconds simulated
|
||||
sim_ticks 8664886 # Number of ticks simulated
|
||||
final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 108749 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418376 # Number of bytes of host memory used
|
||||
host_seconds 79.03 # Real time elapsed on the host
|
||||
host_tick_rate 186194 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 418708 # Number of bytes of host memory used
|
||||
host_seconds 46.54 # Real time elapsed on the host
|
||||
system.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads
|
||||
system.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes
|
||||
system.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads
|
||||
|
@ -55,29 +55,29 @@ system.l1_cntrl3.cacheMemory.num_tag_array_reads 0
|
|||
system.l1_cntrl3.cacheMemory.num_tag_array_writes 0 # number of tag array writes
|
||||
system.l1_cntrl3.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
|
||||
system.l1_cntrl3.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
|
||||
system.cpu0.num_reads 99932 # number of read accesses completed
|
||||
system.cpu0.num_writes 53945 # number of write accesses completed
|
||||
system.cpu0.num_reads 99885 # number of read accesses completed
|
||||
system.cpu0.num_writes 54375 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99540 # number of read accesses completed
|
||||
system.cpu1.num_writes 53424 # number of write accesses completed
|
||||
system.cpu1.num_reads 99537 # number of read accesses completed
|
||||
system.cpu1.num_writes 53839 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99404 # number of read accesses completed
|
||||
system.cpu2.num_writes 53533 # number of write accesses completed
|
||||
system.cpu2.num_reads 99297 # number of read accesses completed
|
||||
system.cpu2.num_writes 53929 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99305 # number of read accesses completed
|
||||
system.cpu3.num_writes 53683 # number of write accesses completed
|
||||
system.cpu3.num_reads 99124 # number of read accesses completed
|
||||
system.cpu3.num_writes 54072 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99222 # number of read accesses completed
|
||||
system.cpu4.num_writes 53970 # number of write accesses completed
|
||||
system.cpu4.num_reads 99259 # number of read accesses completed
|
||||
system.cpu4.num_writes 54427 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99453 # number of read accesses completed
|
||||
system.cpu5.num_writes 53665 # number of write accesses completed
|
||||
system.cpu5.num_reads 99389 # number of read accesses completed
|
||||
system.cpu5.num_writes 54074 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99859 # number of read accesses completed
|
||||
system.cpu6.num_writes 53616 # number of write accesses completed
|
||||
system.cpu6.num_reads 99658 # number of read accesses completed
|
||||
system.cpu6.num_writes 54033 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 53297 # number of write accesses completed
|
||||
system.cpu7.num_writes 53796 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
Loading…
Reference in a new issue