config: Use SimpleDRAM in full-system, and with o3 and inorder
This patch favours using SimpleDRAM with the default timing instead of SimpleMemory for all regressions that involve the o3 or inorder CPU, or are full system (in other words, where the actual performance of the memory is important for the overall performance). Moving forward, the solution for FSConfig and the users of fs.py and se.py is probably something similar to what we use to choose the CPU type. I envision a few pre-set configurations SimpleLPDDR2, SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on this part is welcome. This patch changes plenty stats and adds all the DRAM controller related stats. A follow-on patch updates the relevant statistics. The total run-time for the entire regression goes up with ~5% with this patch due to the added complexity of the SimpleDRAM model. This is a concious trade-off to ensure that the model is properly tested.
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5 changed files with 12 additions and 12 deletions
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@ -73,7 +73,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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# base address (including the PCI config space)
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self.bridge = Bridge(delay='50ns',
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ranges = [AddrRange(IO_address_space_base, Addr.max)])
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self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
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self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.physmem.port = self.membus.master
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@ -109,7 +109,7 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
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physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
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self = LinuxAlphaSystem(physmem = physmem)
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if not mdesc:
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# generic system
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@ -178,9 +178,9 @@ def makeSparcSystem(mem_mode, mdesc = None):
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self.t1000 = T1000()
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self.t1000.attachOnChipIO(self.membus)
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self.t1000.attachIO(self.iobus)
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self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'),
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self.physmem = SimpleDRAM(range = AddrRange(Addr('1MB'), size = '64MB'),
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zero = True)
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self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'),
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self.physmem2 = SimpleDRAM(range = AddrRange(Addr('2GB'), size ='256MB'),
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zero = True)
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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@ -271,7 +271,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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if bare_metal:
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# EOT character on UART will end the simulation
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self.realview.uart.end_on_eot = True
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self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())),
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self.physmem = SimpleDRAM(range = AddrRange(Addr(mdesc.mem())),
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zero = True)
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else:
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self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
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@ -285,7 +285,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
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boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
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'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
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self.physmem = SimpleMemory(range =
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self.physmem = SimpleDRAM(range =
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AddrRange(self.realview.mem_start_addr,
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size = mdesc.mem()),
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conf_table_reported = True)
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@ -323,7 +323,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
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self.iobus = NoncoherentBus()
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self.membus = MemBus()
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self.bridge = Bridge(delay='50ns')
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self.physmem = SimpleMemory(range = AddrRange('1GB'))
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self.physmem = SimpleDRAM(range = AddrRange('1GB'))
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.physmem.port = self.membus.master
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@ -428,7 +428,7 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False
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self.mem_mode = mem_mode
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# Physical memory
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self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
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self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
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# Platform
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self.pc = Pc()
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@ -50,7 +50,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleMemory(),
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physmem = SimpleDRAM(),
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membus = CoherentBus())
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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@ -63,7 +63,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleMemory(),
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physmem = SimpleDRAM(),
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membus = CoherentBus())
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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@ -35,7 +35,7 @@ nb_cores = 4
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cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
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# system simulated
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system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
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system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
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# l2cache & bus
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system.toL2Bus = CoherentBus(clock = '2GHz')
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@ -52,7 +52,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
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cpu.clock = '2GHz'
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system = System(cpu = cpu,
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physmem = SimpleMemory(),
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physmem = SimpleDRAM(),
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membus = CoherentBus())
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system.system_port = system.membus.slave
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system.physmem.port = system.membus.master
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