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config: Fix the cache class naming in regression scripts

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This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
This commit is contained in:
Andreas Hansson 2012-10-26 06:42:42 -04:00
parent b387d8e213
commit 651de2d9af
19 changed files with 56 additions and 57 deletions
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5
configs/common/Caches.py
View file

@ -46,7 +46,7 @@ from m5.objects import *
# starting point, and specific parameters can be overridden in the
# specific instantiations.
class L1(BaseCache):
class L1Cache(BaseCache):
assoc = 2
hit_latency = 2
response_latency = 2
@ -55,7 +55,7 @@ class L1(BaseCache):
tgts_per_mshr = 20
is_top_level = True
class L2(BaseCache):
class L2Cache(BaseCache):
assoc = 8
block_size = 64
hit_latency = 20
@ -84,4 +84,3 @@ class PageTableWalkerCache(BaseCache):
size = '1kB'
tgts_per_mshr = 12
is_top_level = True

6
tests/configs/o3-timing-mp.py
View file

@ -39,7 +39,7 @@ system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')
system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
@ -47,8 +47,8 @@ system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache

6
tests/configs/pc-o3-timing.py
View file

@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8),
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller

6
tests/configs/pc-simple-atomic.py
View file

@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8),
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller

6
tests/configs/pc-simple-timing.py
View file

@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8),
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller

6
tests/configs/realview-o3-checker.py
View file

@ -56,9 +56,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system

6
tests/configs/realview-o3-dual.py
View file

@ -46,14 +46,14 @@ system.cpu = cpus
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache

6
tests/configs/realview-o3.py
View file

@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system

6
tests/configs/realview-simple-atomic-dual.py
View file

@ -46,14 +46,14 @@ system.cpu = cpus
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache

6
tests/configs/realview-simple-atomic.py
View file

@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system

6
tests/configs/realview-simple-timing-dual.py
View file

@ -46,14 +46,14 @@ system.cpu = cpus
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache

6
tests/configs/realview-simple-timing.py
View file

@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system

6
tests/configs/tsunami-inorder.py
View file

@ -48,9 +48,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system

6
tests/configs/tsunami-o3-dual.py
View file

@ -46,14 +46,14 @@ system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache

6
tests/configs/tsunami-o3.py
View file

@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system

6
tests/configs/tsunami-simple-atomic-dual.py
View file

@ -45,14 +45,14 @@ system.cpu = cpus
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache

6
tests/configs/tsunami-simple-atomic.py
View file

@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system

6
tests/configs/tsunami-simple-timing-dual.py
View file

@ -45,14 +45,14 @@ system.cpu = cpus
system.toL2Bus = CoherentBus(clock = '2GHz')
#connect up the l2 cache
system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache

6
tests/configs/tsunami-simple-timing.py
View file

@ -45,9 +45,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4),
L2(size = '4MB', assoc = 8))
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system