Commit graph

508 commits

Author SHA1 Message Date
Ali Saidi
ae0d8d1681 Allow ASI_LDTX_REAL
--HG--
extra : convert_revision : ba1af012ab8ac61a25058977cb7ec511eb2cf3cb
2007-01-17 18:36:12 -05:00
Ali Saidi
c8a2d602b1 do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many
fix for lookup table to keep it consistant with tlb on a replace of a specific entry

--HG--
extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32
2007-01-17 17:59:22 -05:00
Ali Saidi
8173a05eaf Implement reading writing of sync fault status register and address register
--HG--
extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad
2007-01-17 13:09:26 -05:00
Ali Saidi
0584d5bd6c In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks
--HG--
extra : convert_revision : e7b21c56eadf4603ab03364741b00c9689492423
2007-01-16 19:06:33 -05:00
Ali Saidi
ecfd628ecd Modify ISA and staticInst to support a IsFirstMicroOp flag
Increment instruction count on first micro-op instead of last

src/arch/sparc/isa/decoder.isa:
    Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
    set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
    Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
    Add IsFirstMicroop flag to static insts

--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
2007-01-16 19:06:05 -05:00
Lisa Hsu
5c9cbdbb45 Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge between ali and me.

--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
2007-01-11 09:48:15 -05:00
Lisa Hsu
42535f5f53 ua2005.cc:
formatting/indentation for case statements

src/arch/sparc/ua2005.cc:
    formatting/indentation for case statements

--HG--
extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
2007-01-11 09:41:34 -05:00
Lisa Hsu
9f75c1c58f ua2005.cc:
i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

src/arch/sparc/ua2005.cc:
    i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

--HG--
extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
2007-01-11 09:29:03 -05:00
Lisa Hsu
d939060ec6 Add Trap Level Zero to interrupts, remove some unreachable code that I forgot to remove last time.
--HG--
extra : convert_revision : 74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
2007-01-11 09:18:31 -05:00
Ali Saidi
9d04510869 bug fixes to get us to 145m instructions
src/arch/sparc/intregfile.cc:
    some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
    fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
    legion always returns du and dl set, so we need to emulate that for now at least

--HG--
extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
2007-01-10 22:19:13 -05:00
Ali Saidi
28a83c6d1c quiet/remove some warnings
fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis

src/arch/sparc/miscregfile.cc:
    get rid of some warnings
    fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
    implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
    make warning less verbose

--HG--
extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
2007-01-09 22:20:38 -05:00
Lisa Hsu
0d7282d7ab pagetable.hh:
small fix so ALPHA_FS will build on macs
interrupts.hh:
small fix for alpha compile

src/arch/alpha/interrupts.hh:
    small fix for alpha compile
src/arch/alpha/pagetable.hh:
    small fix so ALPHA_FS will build on macs

--HG--
extra : convert_revision : 5fdbc68caa706d652b51807ac8f6bf58bcf72bdc
2007-01-08 20:50:45 -05:00
Lisa Hsu
032ea9b2db the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh:
    fill in how we do interrupts on sparc a little bit.

    1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
    2) fill in getInterrupts() a little bit.

    also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
    1) update formatting
    2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
    overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.

--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2007-01-08 18:18:28 -05:00
Lisa Hsu
b45219e7ae some formatting changes, and update how I do bitfields for HPSTATE and PSTATE to avoid name confusion.
src/arch/sparc/faults.cc:
    1) s/Resumeable/Resumable/gc
    2) s/if(/if (/gc
    3) keep variables lowercase
    4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv).
src/arch/sparc/faults.hh:
    s/Resumeable/Resumable/
src/arch/sparc/isa_traits.hh:
    This is unused and unnecessary.
src/arch/sparc/miscregfile.hh:
    add bitfield masks for some important ASRs (HPSTATE, PSTATE).

--HG--
extra : convert_revision : f0ffaf48de298758685266dfb90f43aff42e0a2c
2007-01-08 18:07:17 -05:00
Ali Saidi
2f4239a685 fix softint and partially implement hstick interrupts need to figure out how to do the acutal interrupting still
src/arch/sparc/miscregfile.cc:
    fix softint and fprs in miscregfile

--HG--
extra : convert_revision : cf98bd9c172e20f328f18e07dd05f63f37f14c87
2007-01-08 17:09:48 -05:00
Ali Saidi
4a8078192d set the softint appropriately on an timer compare interrupt
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly

src/arch/sparc/faults.cc:
    there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
    correct protection defines
src/arch/sparc/ua2005.cc:
    set the softint appropriately on an timer compare interrupt

--HG--
extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
2007-01-05 15:04:17 -05:00
Ali Saidi
b46aa88435 Fix stick compare to work correctly and set checkInterrupts to true at the appropriate time
turn warnings into dprintfs

src/arch/sparc/miscregfile.cc:
    turn dprintfn into dprintfs

--HG--
extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
2007-01-04 20:22:45 -05:00
Gabe Black
8840ebcb00 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
2007-01-03 00:52:30 -05:00
Gabe Black
b642ad00eb Implement a stub nnpc for alpha that is read only as npc+4.
--HG--
extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
2006-12-28 14:27:45 -05:00
Gabe Black
9ca6efdb60 Fixed NumMiscArchRegs. This is still a magic number, and it should be set automatically by the miscreg enum. I need to figure out how to do that without including the whole miscregfile.hh and making header spaghetti.
--HG--
extra : convert_revision : eb640c9ef10a188b96f6a079f91abc8f67b9d38c
2006-12-28 14:23:30 -05:00
Ali Saidi
ba14d6d0e1 Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48

src/arch/sparc/tlb.cc:
    Bug fixes in the TLB
    Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
    Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
    itb should be 64 entries too

--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-27 14:38:07 -05:00
Gabe Black
876c59fe8d Stub for SE mode gdb support for MIPS.
--HG--
extra : convert_revision : 2166b511c3615f7a2355f058a624e9ffe8259e65
2006-12-21 20:42:40 -05:00
Gabe Black
327f451eb7 Fixes to get ALPHA_FS and ALPHA_SE to compile again.
--HG--
extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
2006-12-20 20:44:06 -05:00
Gabe Black
f13155393d Initial work to make remote gdb available in SE mode. This is completely untested.
--HG--
extra : convert_revision : 3ad9a3368961d5e9e71f702da84ffe293fe8adc8
2006-12-20 18:39:40 -05:00
Gabe Black
841d76d37b Make sure the "stack_min" variable is page aligned.
--HG--
extra : convert_revision : e78c53778de83bdb2eca13d98d418b17b386ab29
2006-12-20 15:44:37 -05:00
Ali Saidi
5e9d8795f2 fix twinx loads a little bit
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle

src/arch/sparc/isa/formats/mem/blockmem.isa:
    twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
    fix the fault check for twinx
src/arch/sparc/tlb.cc:
    tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
    don't halt on a couple more instruction (ldx, stx) when things differ
    beacuse of the way tlb faults are handled in legion.

--HG--
extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71
2006-12-19 02:11:33 -05:00
Gabe Black
af1e8d2d40 Fixing the extended twin format to go with the new isa parser interface.
--HG--
extra : convert_revision : f41183cfa011b21e7ab8cbcdef0ac1d464692362
2006-12-18 18:17:30 -05:00
Gabe Black
9e7dc34383 Merge zizzer.eecs.umich.edu:/.automount/zower/eecshome/m5/newmem
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/sparco3

--HG--
extra : convert_revision : f17800685609d8353ec14676f45fbb123fc4e6c3
2006-12-18 12:19:30 -05:00
Ali Saidi
6841f863c5 move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD

src/arch/sparc/isa/decoder.isa:
    move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
    Make QUAD_LDD asi ok to execute

--HG--
extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
2006-12-18 03:37:52 -05:00
Steve Reinhardt
d19d7aa8a5 Minor cleanup of new snippet/subst code.
--HG--
extra : convert_revision : d81e0d1356f3433e8467e407d66d4afb95614748
2006-12-17 23:09:36 -08:00
Steve Reinhardt
968048f56a Convert Alpha (and finish converting MIPS) to new
InstObjParam interface.

src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/fp.isa:
src/arch/alpha/isa/int.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/isa/mem.isa:
src/arch/alpha/isa/pal.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/util.isa:
    Get rid of CodeBlock calls to adapt to new InstObjParam interface.
src/arch/isa_parser.py:
    Check template code for operands (in addition to snippets).
src/cpu/o3/alpha/dyn_inst.hh:
    Add (read|write)MiscRegOperand calls to Alpha DynInst.

--HG--
extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-17 19:27:50 -08:00
Gabe Black
c3ec52346b Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/operands.isa:
    Hand Merge

--HG--
extra : convert_revision : 4c54544e5c7a61f055ea9b00ccf5f8510df0e6c2
2006-12-17 11:55:24 -05:00
Gabe Black
81996f855a Compilation fixes.
--HG--
extra : convert_revision : 4932ab507580e0c9f7012398e71921ce58fc3c4e
2006-12-17 11:16:04 -05:00
Gabe Black
729dbb60e9 Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
    Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.

--HG--
extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
2006-12-17 11:15:37 -05:00
Gabe Black
c299c2562b Started removing "CodeBlock" objects from the mips isa description.
--HG--
extra : convert_revision : 2e174ecfce8c86732e1addfc23e961429b86a570
2006-12-17 10:54:17 -05:00
Gabe Black
220e99a29b Compilation fix after messy merge.
--HG--
extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472
2006-12-17 10:53:10 -05:00
Gabe Black
c9f18981f9 Merge zizzer:/bk/sparcfs/
into  zower.eecs.umich.edu:/eecshome/m5/sparcfs

--HG--
extra : convert_revision : 2764b356ef01d1fcb6ed272e4ef96179cd651d4e
2006-12-16 12:55:15 -05:00
Gabe Black
b9d069167c Support for twin loads.
src/arch/sparc/isa/decoder.isa:
    Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
    Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
    Comment explaining twin load operands.

--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
2006-12-16 12:54:28 -05:00
Gabe Black
fe73760388 Compiler error fix.
--HG--
extra : convert_revision : 39e2638a10bf3e821e8f3d4d8c664008c98fc921
2006-12-16 12:53:01 -05:00
Gabe Black
9d0ca61b7e Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
    Hand Merge

--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
2006-12-16 11:35:40 -05:00
Gabe Black
181f4f32f6 Made changes to CWP be non speculative.
--HG--
extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
2006-12-16 07:10:58 -05:00
Gabe Black
6aa06a26b7 Changes to the isa_parser and affected files to fix an indexing problem with split execute instructions and miscregs aliasing with integer registers.
src/arch/isa_parser.py:
    Rearranged things so that classes with more than one execute function treat operands properly.
    1. Eliminated the CodeBlock class
    2. Created a SubOperandList
    3. Redefined how InstObjParams is constructed

    To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.

    Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
    Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
    Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
    Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.

--HG--
extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-16 07:10:04 -05:00
Lisa Hsu
991146218d Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
2006-12-15 13:27:53 -05:00
Lisa Hsu
b93b32ec33 Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
2006-12-15 13:06:37 -05:00
Lisa Hsu
573d59441e some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode

src/arch/sparc/miscregfile.cc:
    fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
    fix for build
src/cpu/exetrace.cc:
    wrap this variable between FULL_SYSTEM #ifs

--HG--
extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
2006-12-15 13:05:46 -05:00
Lisa Hsu
9a4370ec3b tlb.cc:
fix namespace indentations

src/arch/alpha/tlb.cc:
    fix namespace indentations

--HG--
extra : convert_revision : 327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
2006-12-15 12:58:02 -05:00
Ali Saidi
5e70511bff Optimized the TLB translations with some caching
--HG--
extra : convert_revision : f79f863393f918ff9363b2c261f8c0dfec64312e
2006-12-15 01:48:09 -05:00
Ali Saidi
fa4293af33 flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff

src/arch/sparc/asi.cc:
    flesh out twinx asis
src/arch/sparc/miscregfile.cc:
    fix TICK register reads
src/arch/sparc/tlb.cc:
    reduce the number of readmiscreg accesses,
    implement tsb pointer stuff

--HG--
extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
2006-12-14 19:01:21 -05:00
Lisa Hsu
a10eff03a5 Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 8cf3e824e4892249b12ed0fd92bb310748b18fa2
2006-12-13 17:52:24 -05:00
Lisa Hsu
98bb1c62b3 fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
--HG--
extra : convert_revision : 4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
2006-12-13 17:51:28 -05:00
Lisa Hsu
a983c4968c Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : c6d174716641f0b8286b8478bcb9053b3eec54e3
2006-12-13 14:33:32 -05:00
Lisa Hsu
5d42fd836b Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

--HG--
extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
2006-12-12 21:19:51 -05:00
Gabe Black
90907f6b3c Merge zizzer:/bk/newmem/
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
2006-12-12 18:10:00 -05:00
Ali Saidi
139519ef87 Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts

src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
    initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
    fix bug in tlb map code
src/base/range_map.hh:
    fix bug in rangemap code and add range_multimap
    (these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
    fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
    make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
    fix up the rangemap unit test to catch the missing case

--HG--
extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
2006-12-12 17:55:27 -05:00
Steve Reinhardt
6c8c86f2f9 Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
--HG--
extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
2006-12-12 09:58:40 -08:00
Ali Saidi
4947bf276e fix lisa's hand merge
--HG--
extra : convert_revision : d25604156ae0b2cf29d92fb960b8f5d77427985b
2006-12-09 18:27:54 -05:00
Ali Saidi
2eef266c45 Merge zizzer:/bk/sparcfs
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c51fd95f7acd7cffb3ea705d7216772f0a801844
2006-12-09 18:00:49 -05:00
Ali Saidi
81a00fdcfe Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data

src/arch/sparc/faults.cc:
    Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
    allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
    fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
    cleanup/fix page table code
src/arch/sparc/tlb.cc:
    implement more mmaped iprs, fix numbered insertion  code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
    add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
    dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.

--HG--
extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
2006-12-09 18:00:40 -05:00
Lisa Hsu
369e10d95a Merge zizzer:/bk/sparcfs
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge

--HG--
extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
2006-12-08 15:07:26 -05:00
Lisa Hsu
da6c1f5b09 mostly implemented SOFTINT relevant interrupt stuff.
src/arch/sparc/interrupts.hh:
    add in thread_context.hh to get access to tc.
    get rid of stubs that don't make sense right now.
    implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
    softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
    add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
    implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.

--HG--
extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
2006-12-08 14:37:31 -05:00
Ali Saidi
ed22eb781d get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    add sparc error asi
src/arch/sparc/faults.cc:
    put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
    Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
    warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
    add sparc error register code that just does nothing
    fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
    fix implementation of HPSTATE  write
src/cpu/exetrace.cc:
    let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
    add l2 error status register fake devices

--HG--
extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-07 18:50:33 -05:00
Gabe Black
41051f35ac Make branches handle the lack of a symbol table or the lack of a symbol gracefully.
--HG--
extra : convert_revision : 7bb16405999b86f9fa082a6d44da43d346edc182
2006-12-07 18:45:30 -05:00
Gabe Black
015873fa86 Change how Page Faults work in SPARC. It now prints the faulting address, and panics instead of fatals. This isn't technically what it should do, but it makes gdb stop at the panic rather than letting m5 exit.
--HG--
extra : convert_revision : 3b14c99edaf649e0809977c9579afb2b7b0d72e9
2006-12-07 18:43:55 -05:00
Ali Saidi
03be92f23b Handle access to ASI_QUEUE
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file

src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
    add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
    Handle access to ASI_QUEUE

--HG--
extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
2006-12-06 19:25:53 -05:00
Ali Saidi
ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.

configs/common/FSConfig.py:
    Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
    we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
    Fix AsiIsNucleus spelling with respect to header file
    Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
    Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
    switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
    Flesh out priviledgedString with hypervisor checks
    Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
    insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
    Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
    flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
    add an IPR traceflag
src/mem/request.hh:
    Fix a bad assert() in request

--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-06 14:29:10 -05:00
Gabe Black
0ed6c52c1e Made the alpha setSyscallReturn take a ThreadContext pointer instead of a RegFile *.
--HG--
extra : convert_revision : 021a1fe6760df1daf6299d46060371a5310f008a
2006-12-06 11:33:37 -05:00
Gabe Black
b3cfa6ec42 Added a flattenIntIndex function for Alpha.
--HG--
extra : convert_revision : 5ed79ed18e443118a28d6890327c55a6a3fcd325
2006-12-06 11:30:41 -05:00
Gabe Black
dc105934f3 Change to use -return_value.value like other implementations.
--HG--
extra : convert_revision : 513422c1c8c24f3662e6a423d13ee033424aa44b
2006-12-06 05:47:19 -05:00
Gabe Black
bf5f6c6430 Some changes for misc regs which were changed into unofficial integer registers, and moved the flattenIndex function into the register file.
--HG--
extra : convert_revision : 6b797c793a6c12c61a23f0f78a1ea1c88609553e
2006-12-06 05:46:44 -05:00
Gabe Black
5ad1731a12 Reorganize the includes and add an include for misc.hh.
--HG--
extra : convert_revision : 484b2d07a1e8b3879c35d80bf16b73fd0cc9be1f
2006-12-06 05:45:18 -05:00
Gabe Black
643cb6dd81 Added some debug output, and made sure not to accidentally ask for the result of a store conditional.
--HG--
extra : convert_revision : d36ff9e2343fdf78a3bc16a1348975fdba5c55e2
2006-12-06 05:44:31 -05:00
Gabe Black
a36a59e8d7 Some basic fix ups, and CWP is no longer set explicitly.
--HG--
extra : convert_revision : 1dde5594a2bcfd9fb5ad974360b3dc035f1624e5
2006-12-06 05:43:25 -05:00
Gabe Black
c541be3a48 Changed the integer register file to work with flattened indices.
--HG--
extra : convert_revision : c5153c3c712e5d18b5233e1fd205806adcb30654
2006-12-06 05:42:09 -05:00
Gabe Black
4d8a0541dd Change MIPS's setSyscallReturn to use a thread context.
--HG--
extra : convert_revision : 618f8404ec5380615e28170d761b2fcdf9c07d96
2006-12-06 05:41:08 -05:00
Gabe Black
a3f351ab59 Added basic flatten function for mips.
--HG--
extra : convert_revision : 2c32851584001734d139f36c4d58c5e61067fcfc
2006-12-06 05:40:11 -05:00
Gabe Black
12c5bd2305 Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed.
src/arch/alpha/syscallreturn.hh:
src/arch/mips/syscallreturn.hh:
src/sim/syscallreturn.hh:
    Move the SyscallReturn class into sim/syscallreturn.hh
src/arch/sparc/faults.cc:
src/arch/sparc/isa/operands.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/arch/sparc/process.cc:
src/arch/sparc/sparc_traits.hh:
    Move some miscregs into the integer register file so they get renamed.

--HG--
extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
2006-12-05 01:55:02 -05:00
Ali Saidi
4d57cab49a forgot to commit miscreg file
--HG--
extra : convert_revision : c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
2006-12-04 20:29:55 -05:00
Gabe Black
8b1bcc3f52 Merge zizzer:/bk/sparcfs
into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

--HG--
extra : convert_revision : 45d9599dd883e10c283812c1c241c20323f44cec
2006-12-04 19:56:04 -05:00
Gabe Black
251f4e1134 Add in code to pass the ASI to translation.
--HG--
extra : convert_revision : 4a985635cda7680abcddaf0bc9579fa03d5bc7c6
2006-12-04 19:55:52 -05:00
Ali Saidi
8e75b6e2a5 reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes)
Protect other pieces of code so that sparc compiles SE again

src/arch/sparc/SConscript:
    Add ua2005.cc back into SConscript
src/arch/sparc/miscregfile.hh:
    add functions that deal with priv registers so we don't have to have a bunch of if defs and other ugliness
src/arch/sparc/mmaped_ipr.hh:
    wrap handleIpr* with if full_system so it compiles under se
src/arch/sparc/ua2005.cc:
    reorganize edit fs only miscreg functions
src/cpu/exetrace.cc:
    protect legion code so it doesn't try to compile under se

--HG--
extra : convert_revision : 6b3c9f6f95b4da8544525f4f82e92861383ede76
2006-12-04 19:39:57 -05:00
Ali Saidi
92c5a5c8cb More changes to get SPARC fs closer. Now at 1.2M cycles before difference
configs/common/FSConfig.py:
    seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
    change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
    For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
    Use instruction count from cpu rather than cycles because that is what legion does
    we can change it back after were done with legion
src/base/bitfield.hh:
    add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
    add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
    compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
    change asserts of packet success to if panics wrapped with NDEBUG defines
    so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
    expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
    convert some tabs to spaces
src/python/m5/objects/T1000.py:
    add more fake devices for each l1 bank and each memory controller

--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
2006-12-04 00:54:40 -05:00
Ali Saidi
8c4f7a0404 Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it

configs/common/FSConfig.py:
    We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
    Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
    Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
    Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
    fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
    Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
    Let kernel be none
src/sim/system.cc:
    Let the system kernel be none, but warn about it

--HG--
extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
2006-11-30 15:51:54 -05:00
Ali Saidi
7b9ef9716b Add TLB Dprintfs
fix addr alignment problem

--HG--
extra : convert_revision : c691611d4d32bc95d0ae30243b30cd6634e7772b
2006-11-29 20:32:43 -05:00
Gabe Black
36c03001bb Fixes to get compilation.
--HG--
extra : convert_revision : cd6b496c4e4b32ce2a639eb9a2b6fbd62dfff2d1
2006-11-29 17:59:42 -05:00
Gabe Black
5bdf4400b2 Merge zizzer:/bk/sparcfs
into  zower.eecs.umich.edu:/eecshome/m5/newmemmid

src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.hh:
    hand merge

--HG--
extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
2006-11-29 17:34:20 -05:00
Ali Saidi
544f4b4d81 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : c358d5e3211756bbf905eef2a62b65a2e56a86f3
2006-11-29 17:11:20 -05:00
Ali Saidi
b2eecd643c Add support for mmapped iprs to atomic cpu
src/arch/SConscript:
    add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
    make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
    miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
    add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
    allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits

--HG--
extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
2006-11-29 17:11:10 -05:00
Gabe Black
f2daf210f1 Initial changes to get O3 working with SPARC
src/arch/sparc/process.cc:
    MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
    Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
    Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
    Sparc version of this file.

--HG--
extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-24 22:06:33 -05:00
Gabe Black
5f446e36b6 Merge zower:/eecshome/m5/newmem
into  ewok.(none):/home/gblack/m5/newmemo3

--HG--
extra : convert_revision : e8d6ce19a83fe526112c1dd61c48196eb8c0951f
2006-11-24 14:08:44 -05:00
Gabe Black
d0f4a4c441 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 7dbd30ce5579dd62d5f54bb5d75cf12346bc5d1d
2006-11-24 14:08:43 -05:00
Gabe Black
c6ddab95df Rename this function.
--HG--
extra : convert_revision : 57ea1e1d3b75e35abb3310d392ec70086fff699a
2006-11-24 14:01:18 -05:00
Gabe Black
7708217167 Fix weird type modifier.
--HG--
extra : convert_revision : 7372b7a92b3c9d05388acb43ba58ada18464fa24
2006-11-24 14:00:45 -05:00
Gabe Black
96a6af98e2 Fix an include problem.
--HG--
extra : convert_revision : 89be55bd3f4f9b452a680a98b69ce42b80546769
2006-11-24 14:00:00 -05:00
Steve Reinhardt
28f8318252 Add no-op versions of ivlb and ivle back in for backwards compatibility.
--HG--
extra : convert_revision : 383b72c130b20f3d7cde4e08fa36a481f3c0bf7c
2006-11-24 12:32:33 -05:00
Ali Saidi
6e9cf9411f Merge zizzer:/bk/sparcfs
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : f540987901994fe9dc023587fd555efb2dbf24bf
2006-11-23 01:44:49 -05:00
Ali Saidi
271b9a5435 first cut at a sparc tlb
src/arch/sparc/SConscript:
    Add code to serialize/unserialze tlb entries
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
    update asi names for how they're listed in the supplement
    add asis
    add more asi functions
src/arch/sparc/isa_traits.hh:
    move the interrupt stuff and some basic address space stuff into isa traits
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add mmu registers to tlb
    get rid of implicit asi stuff... the tlb will handle it
src/arch/sparc/regfile.hh:
    make isnt/dataAsid return ints not asis
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    first cut at sparc tlb
src/arch/sparc/vtophys.hh:
    pagatable nedes to be included here
src/mem/request.hh:
    add asi and if the request is a memory mapped register to the requset object
src/sim/host.hh:
    fix incorrect definition of LL

--HG--
extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3
2006-11-23 01:42:57 -05:00
Gabe Black
de445b5e96 Fixes to the isa description.
src/arch/sparc/isa/base.isa:
    Fix a constant.
src/arch/sparc/isa/decoder.isa:
    Made carry calculation more consistent.
src/arch/sparc/isa/operands.isa:
    Use the right constant.

--HG--
extra : convert_revision : 25b3a09ff20d4b8e1a95ee8a983d14ef3cfe73bb
2006-11-23 00:36:42 -05:00
Gabe Black
758c780651 Moved some constants from isa_traits.hh to the reg file headers.
--HG--
extra : convert_revision : 378b2d9791e6282539900a2261ad2275d726b4be
2006-11-22 23:49:44 -05:00
Gabe Black
0a99750ebf Merge zizzer:/bk/sparcfs
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
2006-11-22 15:45:32 -05:00
Gabe Black
b4a31cb8b5 Make sure only real bits of pstate can be set.
--HG--
extra : convert_revision : 8707bbed2aeb80613f86503e92b63853767adaa9
2006-11-20 18:08:50 -05:00
Gabe Black
a0287c1e2d Set the pstate.priv bit to 1 in hyperpriveleged mode. The description in the manual of what happens during a trap says it should be 0, and other places say it doesn't matter.
--HG--
extra : convert_revision : 9ecb6af06657e936a208cbeb8e4a18305869b949
2006-11-20 18:07:58 -05:00
Gabe Black
cd2727694d Add in rom/rams for the nvram, hypervisor description, and partition description.
--HG--
extra : convert_revision : a49de5fcfbea307c971964b8a68b95eb5d9a2bf4
2006-11-20 17:59:35 -05:00
Kevin Lim
719416b60f Fix typo.
--HG--
extra : convert_revision : 2dd830c6b3b5df894608b7596250b0181a3dfdf0
2006-11-20 11:44:27 -05:00
Nathan Binkert
31d829d388 Implement current working directory for LiveProcesses
--HG--
extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
2006-11-16 12:43:11 -08:00
Gabe Black
74654ddd1f Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
2006-11-16 14:42:44 -05:00
Gabe Black
cd5b33b9ff Fixes for SPARC_FS
configs/common/FSConfig.py:
    Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
    Create a T1000 platform
src/arch/sparc/miscregfile.cc:
    Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
    Truncate an ExtMachInst to a MachInst before comparing with Legion.

--HG--
extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
2006-11-16 12:34:10 -05:00
Gabe Black
ac2c7967f6 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
2006-11-14 15:23:23 -05:00
Lisa Hsu
ee777f35c2 interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build

src/arch/sparc/interrupts.hh:
    make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build

--HG--
extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
2006-11-14 12:59:57 -05:00
Gabe Black
7632198a6e Merge 141.212.106.238:/home/gblack/m5/newmemmemops
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem

--HG--
extra : convert_revision : cda58e6e63f2f909b85a510fb76d35d49d8042b9
2006-11-14 01:31:37 -05:00
Gabe Black
20730b790c Set hpstate to be what I'm assuming Legion is.
--HG--
extra : convert_revision : 0be66513cb0cff07c0c2b50c97c1ea74d52b0dc9
2006-11-14 01:30:34 -05:00
Gabe Black
c2ceaa887e Make sure a POR doesn't clobber the value of the hpstate.
--HG--
extra : convert_revision : 4504f08fd94792819bd4419bbd2e0ebd1d7f29e9
2006-11-14 01:29:11 -05:00
Gabe Black
6b95f24145 Fix up the disassembly a little.
--HG--
extra : convert_revision : 7bdf68f445b79b1b5dbcdfa5fa1005c68d03724c
2006-11-14 01:28:11 -05:00
Gabe Black
8d234a4bc5 Merge 141.212.106.238:/home/gblack/m5/newmemmemops
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem

--HG--
extra : convert_revision : 753831a9f6f79d07e6ee122ab894e24161d2e722
2006-11-14 01:23:59 -05:00
Steve Reinhardt
51d8c59ef8 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : faab7569deefde94c20133b2f70a8567bcaa2960
2006-11-12 22:04:00 -08:00
Steve Reinhardt
0f633c5fee Make setRegWithEffect do something in SE mode.
--HG--
extra : convert_revision : 88fdaa403fe6d083f8c8fc064cb0d0d6a8b8daf8
2006-11-12 22:03:42 -08:00
Kevin Lim
3052632b68 Merge ktlim@zamp:./local/clean/tmp/test-regress
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
2006-11-12 21:57:58 -05:00
Kevin Lim
12e26c68c3 Updates to support new interrupt processing and removal of PcPAL.
src/arch/alpha/interrupts.hh:
    No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
    Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
    Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
    Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
    Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
    Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
    Fix broken if statement from PcPAL updates, and properly populate the request fields.

    Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
    Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
    Populate request fields properly.
src/cpu/simple/base.cc:
    Update for interrupt stuff.

--HG--
extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
2006-11-12 20:15:30 -05:00
Gabe Black
fd35f02efe Fix for CAS so that it knows about all the possible code in the constructor.
--HG--
extra : convert_revision : 863d395f8e7c8ee2aec708ffcef842317ec9a89b
2006-11-11 07:23:13 -05:00
Gabe Black
239a89e713 Certain header files should only be used in FS.
src/arch/alpha/faults.hh:
    Only use pagetable.hh in FS
src/arch/alpha/pagetable.hh:
    pagetable.hh should only be included in FS, so protecting it internally should be unnecessary.
src/cpu/exetrace.cc:
    Only use tlb.hh in FS

--HG--
extra : convert_revision : 91ea61f2e7970e7146b6d407ee250fcb20cd4d48
2006-11-11 07:15:16 -05:00
Ali Saidi
aa19b2e7bc fix endian issues with condition codes
use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?

src/arch/sparc/faults.cc:
    set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
    fix endian issues with condition codes
src/arch/sparc/tlb.hh:
    add implemented physical addres constants
src/arch/sparc/utility.hh:
    add tlb.hh to utilities
src/base/loader/raw_object.cc:
    add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
    use memcpy instead of bcopy
src/cpu/exetrace.cc:
    clean up printing a bit more
src/cpu/m5legion_interface.h:
    add tons to the shared interface
src/dev/ethertap.cc:
    s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
    fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
    hack to make sure htole() works...

--HG--
extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
2006-11-10 20:17:42 -05:00
Gabe Black
6d54a77518 Elaborated on the tlb stubs so that they just set the physical address to the virtual address.
--HG--
extra : convert_revision : 41478abc4d21d504420f6842338675c0767f7cf9
2006-11-10 15:32:15 -05:00
Gabe Black
e3d8831857 Fixed up DepTags a little. I think NumMicroIntRegs shouldn't be added to Ctrl_Base_DepTag.
--HG--
extra : convert_revision : 2ebb3eb781441ba936c8d8bb1f42e4c0840aff2e
2006-11-10 15:30:59 -05:00
Gabe Black
d30e3b30af Added StrandStsReg operand.
--HG--
extra : convert_revision : 51be41716ed9fe0e99e53f2341ad5651a525055a
2006-11-10 15:29:32 -05:00
Gabe Black
13a8752c11 Put in provisions for rd, rdpr, rdhpr, wr, wrpr, and wrhpr to disassemble properly.
--HG--
extra : convert_revision : f2cad8a5879999438ba9b05f15a91320e7a4cc4a
2006-11-10 15:28:58 -05:00
Gabe Black
7bf1c8981d Made the annul of unconditional conditional branches behave properly, added code to read and write the strand_sts_reg, and made restored a Priv instruction.
--HG--
extra : convert_revision : 386512215f7243d230717c369217f8d2f9ada935
2006-11-10 15:27:06 -05:00
Gabe Black
27b43b62b7 Fixed up the code that prints out registers to take into account microregisters.
--HG--
extra : convert_revision : 6809de467e4500ce34447c0544caf0ba04af81e7
2006-11-10 15:25:52 -05:00
Gabe Black
8390e46311 Tweaked debug output.
--HG--
extra : convert_revision : cd33b7c1ebdbefd42f18c1435b2519d06d9914a6
2006-11-10 15:25:03 -05:00
Gabe Black
cee4d1c113 Touched up faults, and made POR actually do something.
--HG--
extra : convert_revision : 38951352edbfc423fb6767a9aac49a703578c0ac
2006-11-10 15:24:10 -05:00
Gabe Black
9ef51f2dba Actually finished moving the register file stuff around.
--HG--
extra : convert_revision : 786735ecea8ff480db6b3754ac5daa562938d988
2006-11-10 05:49:16 -05:00
Gabe Black
9731fb3fd7 Moved the Alpha float regfile into it's own regfile and got rid of constants.hh and isa_traits.cc
--HG--
extra : convert_revision : 55afd7d21c276906520da375b3bbb563be420880
2006-11-10 05:29:05 -05:00
Gabe Black
b4dfbf3aab Split out alpha integer register file into it's own files.
--HG--
extra : convert_revision : 164bdcec2860c5dca3f0f11d189781b88dd717cb
2006-11-10 04:54:25 -05:00
Gabe Black
71dc49c785 The reset function of the MiscRegFile really resets it now. This function is called from the class's constructor.
--HG--
extra : convert_revision : 4e7a40ffe0a9a71fd1b2b171d9c0dcac50e1a1fe
2006-11-10 04:33:41 -05:00
Gabe Black
dc6af9fbf7 Set the ASI register to be something explicitly so that simulation is deterministic.
--HG--
extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
2006-11-10 04:14:25 -05:00
Gabe Black
4aea5deccb Fix up instructions to read and write control registers, and got rid of the control register fields which won't work on a big endian host.
--HG--
extra : convert_revision : 1b518873b6e1a073b58cbe27642537d5ae3a604d
2006-11-10 04:02:39 -05:00
Gabe Black
232c3f1b27 Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants.
--HG--
extra : convert_revision : e4af5e2fb2a6953f8837ad9bda309b7d6fa7abfb
2006-11-09 21:30:48 -05:00
Gabe Black
50462c15aa Fix a couple uninitialized variables.
--HG--
extra : convert_revision : d17d28a9520524e5f56bd79beb9b2be6ce76a22f
2006-11-09 19:24:35 -05:00
Ali Saidi
cb172d0332 Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.

SConstruct:
    Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
    add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
    add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
    add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
    add option to try raw when nothing works
src/cpu/exetrace.cc:
    cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
    change the instruction to be 32 bits because it is
src/mem/physical.cc:
    fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
    Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
    Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
    add the ability to add Addr() together

--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-09 18:22:46 -05:00
Gabe Black
5b90922ad5 Put the MIPS stacktrace into the MipsISA namespace to fit with Alpha and SPARC.
--HG--
extra : convert_revision : 86f5585fe9ceb2ee30836d35384ebcddc1357c2a
2006-11-08 16:15:20 -05:00
Gabe Black
42c73c6a92 Make a function to say how big gdbregs is in bytes vs. regs.
--HG--
extra : convert_revision : 10c50c2d45a8e510d71cccde520059363116da8a
2006-11-08 15:31:52 -05:00
Gabe Black
63bbc8929d First cut at full blown SPARC faults. There are a few details that are missing.
--HG--
extra : convert_revision : 8023db1479cb9bf99fc9edfeb521c4e5b581f895
2006-11-08 13:58:00 -05:00
Gabe Black
67b9a2ebd8 Move the check to see if you're in user mode into the isa directory.
--HG--
extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
2006-11-08 13:55:48 -05:00
Gabe Black
770b575c30 Sorted faults by the trap type constant, expanded their names, added in new faults for ua2005, and commented out ones which are apparently dropped.
--HG--
extra : convert_revision : 32bd0c3a75d7c036ad4a3cb0bc1c32e0b6cb3d87
2006-11-08 10:27:38 -05:00
Gabe Black
9375caa3f1 Fix for slightly mangled merge.
--HG--
extra : convert_revision : 1dea04ca222dd423c3d462114bc1c65afa52825d
2006-11-08 08:25:37 -05:00
Gabe Black
b82fa633bb Merge zeep.eecs.umich.edu:/home/gblack/m5/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/arch/sparc/faults.hh:
    Hand merged.

--HG--
extra : convert_revision : 1bcefe47fa98e878a0dfbcfa5869b5b171927911
2006-11-08 08:19:52 -05:00
Gabe Black
635df9ba17 Major clean up of the fault code.
--HG--
extra : convert_revision : eb7e016a127417cbb0e1e2c733b17f82469c2f24
2006-11-08 08:12:19 -05:00
Gabe Black
f0c4d36649 The new global level is computed with min, not max.
--HG--
extra : convert_revision : 6339c82d3655694445c3eb43e467b9aa6b4c8224
2006-11-08 04:18:15 -05:00
Gabe Black
8cb7ac0900 Changed the getReg and setReg functions so that they work like netbsd. Apparently, gdb expects to do single stepping on its own, so those functions panic for SPARC. acc still needs to be implemented.
--HG--
extra : convert_revision : c6e98e37b8ab3d6f8d6b3cd2c961faa65b08a179
2006-11-08 02:13:47 -05:00
Gabe Black
f1a55570d3 Put the ProcessInfo and StackTrace objects into the ISA namespaces.
--HG--
extra : convert_revision : 1626703583f02a1c9823874290462c1b6bdb6c3c
2006-11-08 00:52:04 -05:00
Gabe Black
16a012e80d Stubs for SPARC's tlbs
--HG--
extra : convert_revision : ba08da78693cc6f59f7358134f121f471910dbf6
2006-11-08 00:32:40 -05:00
Gabe Black
746ceb93fd Replaced getArg with a SPARC implementation.
--HG--
extra : convert_revision : ba31171a81b6c46de2997de2701d35fcf8c614b7
2006-11-08 00:32:04 -05:00
Gabe Black
1a5d5d0b56 Force remote gdb code to use signal numbers and not ISA specific trap numbers.
--HG--
extra : convert_revision : 4f45a4b48e3993ac6991db2afffbce2e666eab6c
2006-11-07 23:40:54 -05:00
Gabe Black
c693c6ba9f Put kernel_stats back into arch.
--HG--
rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc
rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh
rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc
rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh
rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh
rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc
rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh
extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
2006-11-07 22:34:34 -05:00
Gabe Black
48415ad298 A dummy implementation of stacktrace.cc to clear up linker errors.
--HG--
extra : convert_revision : ea1e54a529ad7ae4a6564dd6fb47c31fb0573adf
2006-11-07 05:44:22 -05:00
Gabe Black
7e422980e9 Arguments class for SPARC. This is basically just a copy of Alpha's
--HG--
extra : convert_revision : 9df68973c63d5ff256d6de485e8d918c454c8ff1
2006-11-07 05:43:33 -05:00
Gabe Black
74112dec52 Added a stub implementation of fixFuncEventAddr to get past linker errors.
--HG--
extra : convert_revision : 24ab1789496c5fae6c0992db2d521ea02354ee90
2006-11-07 05:41:23 -05:00
Gabe Black
0c9bcf209a The normal spill and fill faults only need to behave specially in SE.
--HG--
extra : convert_revision : 4d4b866699e3450b88418822fc198411ee3d831a
2006-11-07 05:40:48 -05:00
Gabe Black
bcd5099aac Added in alot of missing source files.
--HG--
extra : convert_revision : 335b458d195a00dac3d04e92fe9df915e660538f
2006-11-07 05:40:06 -05:00
Gabe Black
54e22bfe95 Broke remote_gdb into a base class and architecture specific derived classes.
--HG--
extra : convert_revision : 8c528fab56a95b8245ad0f2572d62bb556ce0dde
2006-11-07 05:39:40 -05:00
Gabe Black
da24915181 Moved the idle event out of system_events.hh. The skipFuncEvent can be made ISA independent by making it use the #define for branch delay slots (and NNPC)
--HG--
extra : convert_revision : b2631b1163397ecc99f2f315e2b88537e2002731
2006-11-07 05:38:33 -05:00
Gabe Black
4bfb8547bb Moved the switched version of kernel_stats.hh back to kern, and moved the base kernel_stats to base_kernel_stats
--HG--
extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017
2006-11-07 05:36:54 -05:00
Gabe Black
eb4ef3ad76 Made kern a switching header file directory.
SConstruct:
    Put the code to make a switching header directory into a function so they are easy to make.
src/arch/SConscript:
    Replace switching header code with the new function call.
src/kern/SConscript:
    Created a new switching header directory in kern, and moved the declaration of some source files here.

--HG--
rename : src/kern/kernel_stats.cc => src/kern/base_kernel_stats.cc
rename : src/kern/kernel_stats.hh => src/kern/base_kernel_stats.hh
extra : convert_revision : 98f5320a5ade567c3e4f67fef123dfb0c5122545
2006-11-07 05:33:21 -05:00
Gabe Black
02abca6b9e Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/SConscript:
    SCCS merged

--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
2006-11-06 19:52:32 -05:00
Gabe Black
b04a2653f9 Got rid of obsolete ivlb and ivle psuedo instructions.
--HG--
extra : convert_revision : c3c2dd5a6e7181ad94194146d7fa2b33b21074fb
2006-11-06 19:09:23 -05:00
Gabe Black
ef1a92eb9b Stub for SPARC interrupt handling object.
--HG--
extra : convert_revision : 7257e3387c01e84e5a1018a9cdcc09a79edfa934
2006-11-06 18:30:28 -05:00
Gabe Black
85a6079db7 Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not.
--HG--
extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
2006-11-06 18:29:58 -05:00
Gabe Black
e39de58d21 Took the Alpha prefix off of AlphaArguments, and made sure it was being used from TheISA:: rather than AlphaISA::
--HG--
extra : convert_revision : 17c143d3cbc2f58a7a9d01366a8f649810ff7f33
2006-11-06 18:28:10 -05:00
Gabe Black
1ffff78ca9 Created seperate SConscript for the dev directory. Made subdirectories for Alpha and SPARC and put SConscripts in them.
--HG--
rename : src/base/kgdb.h => src/arch/alpha/kgdb.h
rename : src/dev/alpha_access.h => src/dev/alpha/access.h
rename : src/dev/alpha_console.cc => src/dev/alpha/console.cc
rename : src/dev/alpha_console.hh => src/dev/alpha/console.hh
extra : convert_revision : a7dd466308cb83edc40528689aacb72413089cdf
2006-11-06 18:26:11 -05:00
Ali Saidi
de90ae4825 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : d7133e32cfca9f15869ee9ab7a93e3470e7d9038
2006-11-04 21:41:10 -05:00
Ali Saidi
21cf4a46b9 fixes so that M5 will compile under solaris
SConstruct:
    Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
    use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
    If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
    solaris doesn't have random(), so use rint with the correct rounding mode
    if we're compiling on solaris
src/base/stats/flags.hh:
    u_int32_t??
src/base/time.hh:
    grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
    we don't need to include stdint here
src/sim/byteswap.hh:
    the method to detect endianness on Solaris is a little more complex...

--HG--
extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
2006-11-04 21:41:01 -05:00
Gabe Black
601822c6b5 Make things compile in SE again.
--HG--
extra : convert_revision : cf7faf5001b31d61c61ddce2386d61c919075800
2006-11-03 14:42:12 -05:00
Gabe Black
8778d85b2d Use a PowerOnReset to initialize the cpu.
--HG--
extra : convert_revision : 9e65af095c37c7c67db377424d2d4363fa8065f9
2006-11-03 14:41:27 -05:00
Gabe Black
6ad386f1a8 Calling syscalls from within the trap instruction's invoke method won't work because apparently you need an xc for that and not a tc. Cleaned up the TrapInstruction fault in light of this.
--HG--
extra : convert_revision : 1805c9244cfd62d0ee7862d8fd7c9983e00c5747
2006-11-03 14:40:35 -05:00
Gabe Black
29a79acb7c Gutted out the old Alpha stuff.
--HG--
extra : convert_revision : 6767dc1305a58e3e7eb0ee909d54768e51744927
2006-11-03 11:05:13 -05:00
Gabe Black
3f4b098985 Added a stub initCPU function. This would be a good place to force in a PowerOnReset fault to kick start the CPU.
--HG--
extra : convert_revision : 79e1fa2ef40e326682069639e260db255fd29d93
2006-11-03 11:04:10 -05:00
Gabe Black
6b701a6d25 Compilation fixes.
--HG--
extra : convert_revision : 44d67a3bb95f875f17586499aa4a04268aa2fd46
2006-11-03 11:03:03 -05:00
Gabe Black
ab651344dd Add the syscall number as the second parameter for the trap fault. This could be improved and syscalls could be called from the trap's invoke method.
--HG--
extra : convert_revision : 127a3673a076110fb3605c0fbc93e8d7e9fec84b
2006-11-03 10:56:47 -05:00
Gabe Black
e6fed44625 Add an invoke function for PowerOnReset
--HG--
extra : convert_revision : a1cdd35c74f6e85f42a04061b466ec7617da8ac2
2006-11-03 10:55:29 -05:00
Gabe Black
694323b7c4 Move around misc reg code
src/arch/sparc/faults.cc:
    Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
    Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
    readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.

--HG--
extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb
2006-11-03 10:54:34 -05:00
Gabe Black
7c5a859243 removed ua2005.cc since it's been obsorbed into the miscregfile, and added system.cc
--HG--
extra : convert_revision : 2a124adcefe0d15860632a05e8788d3fd34008c2
2006-11-03 10:52:08 -05:00
Gabe Black
118b9dc1f9 Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however.
--HG--
extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
2006-11-03 04:25:33 -05:00
Gabe Black
c8fc116c76 Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the
--HG--
extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
2006-11-03 02:25:39 -05:00
Gabe Black
fa91832900 Fixed a comment
--HG--
extra : convert_revision : bebc701508e1d38ee74a07377c634d5e46e89abe
2006-11-03 01:15:31 -05:00
Kevin Lim
e71ccde663 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
2006-11-02 15:20:47 -05:00
Kevin Lim
ccaf80cc46 Use ISA specific makeExtMI.
src/arch/alpha/utility.hh:
    For now makeExtMI will be specific to the ISA.

--HG--
extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
2006-11-02 13:11:38 -05:00
Gabe Black
6f78d49410 Fix a range check on the ipr_index.
--HG--
extra : convert_revision : 84e25abd4bb2de0c877c883804d39feb019c7030
2006-11-01 18:46:18 -05:00
Gabe Black
2b11b47357 Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults
--HG--
extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-11-01 16:44:45 -05:00
Gabe Black
f3ba6d20f6 Arg!
--HG--
extra : convert_revision : 8328d002780c0291e7eb264076a62084de88b7a5
2006-10-31 18:59:50 -05:00
Gabe Black
1543c3d0a1 More typos! I need to get nfs to work.
--HG--
extra : convert_revision : f5693e96d376254f777fb0cce7b5be3d36efbea9
2006-10-31 18:51:26 -05:00
Gabe Black
1dd903e856 Fix another typo
--HG--
extra : convert_revision : ad7058babf2a13bfe543e05f2662dc49a18a8b8b
2006-10-31 18:39:17 -05:00
Gabe Black
39de635fbf Check for out of range IPR values as well.
--HG--
extra : convert_revision : 9ca241bb71d8a1d022e54485383a88d2abece663
2006-10-31 18:19:45 -05:00
Gabe Black
45368c0300 Fix stupid typo
--HG--
extra : convert_revision : fbfc82974e89b2c726b689674c9f5d957682b280
2006-10-31 18:01:31 -05:00
Gabe Black
fb5ba85abb Make two simple utility functions to determine if a MiscReg index corresponding to an IPR is readable or writable.
--HG--
extra : convert_revision : 89eebba5eec01e629213997d24c734a6acad0ecb
2006-10-31 17:50:57 -05:00
Gabe Black
ad201172c9 We don't include ipr.cc in SE builds, so don't call it.
--HG--
extra : convert_revision : 45e52d7afbf74e0ddde11f58aeb084186389fc06
2006-10-31 16:59:41 -05:00
Gabe Black
ace4f0c188 Made the old name refer to the miscreg index to prevent having to change code all over the place.
--HG--
extra : convert_revision : e890a3ce420336acdb220396dcbf66d4b9974c76
2006-10-31 16:36:45 -05:00
Gabe Black
44f2c05118 Forgot to change the index.
--HG--
extra : convert_revision : 5a444e635d20bcca445a10e43592b6c10d25e879
2006-10-31 16:18:54 -05:00
Gabe Black
ece796ab8a Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR.
--HG--
extra : convert_revision : dd235261e7086d6667b1b2bdc4a81b2573e21d53
2006-10-31 16:02:28 -05:00
Gabe Black
eab445e1bc Get rid of old, commented out code.
--HG--
extra : convert_revision : 46e9f26917efab642b80ea9e4303ec95d43d935e
2006-10-31 03:44:39 -05:00
Gabe Black
038217049a Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
2006-10-31 03:37:01 -05:00
Gabe Black
4862879a94 Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names.
--HG--
extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4
2006-10-31 02:08:44 -05:00
Gabe Black
349c7aff9b Move the mem classes into util.isa so that multiple inheritance can be used in the future for micro insts.
--HG--
extra : convert_revision : c71faa5e43b56ed15d00ed5fd57c020d1c845445
2006-10-29 03:40:52 -05:00