Fix stick compare to work correctly and set checkInterrupts to true at the appropriate time
turn warnings into dprintfs src/arch/sparc/miscregfile.cc: turn dprintfn into dprintfs --HG-- extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
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@ -321,9 +321,9 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
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// I'm not sure why legion ignores the lowest two bits, but we'll go
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// with it
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// change from curCycle() to instCount() until we're done with legion
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DPRINTFN("Instruction Count when TICK read: %#X stick=%#X\n",
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DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
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tc->getCpuPtr()->instCount(), stick);
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return mbits(tc->getCpuPtr()->instCount() + (int32_t)stick,62,2) |
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return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
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mbits(tick,63,63);
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case MISCREG_FPRS:
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warn("FPRS register read and FPU stuff not really implemented\n");
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@ -615,7 +615,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
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// use stick for offset and tick for holding intrrupt bit
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stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
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tick = mbits(val,63,63);
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DPRINTFN("Writing TICK=%#X\n", val);
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DPRINTF(Timer, "Writing TICK=%#X\n", val);
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break;
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case MISCREG_FPRS:
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//Configure the fpu based on the fprs
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@ -64,19 +64,20 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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time = (tick_cmpr & mask(63)) - (tick & mask(63));
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if (!(tick_cmpr & ~mask(63)) && time > 0)
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tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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warn ("writing to TICK compare register %#X\n", val);
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panic("writing to TICK compare register %#X\n", val);
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break;
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case MISCREG_STICK_CMPR:
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if (sTickCompare == NULL)
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sTickCompare = new STickCompareEvent(this, tc);
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setReg(miscReg, val);
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if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
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if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
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sTickCompare->deschedule();
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time = (stick_cmpr & mask(63)) - (stick & mask(63));
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time = ((int64_t)(stick_cmpr & mask(63)) + (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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if (!(stick_cmpr & ~mask(63)) && time > 0)
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sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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warn ("writing to sTICK compare register value %#X\n", val);
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sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
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DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
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break;
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case MISCREG_PSTATE:
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@ -116,11 +117,12 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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if (hSTickCompare == NULL)
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hSTickCompare = new HSTickCompareEvent(this, tc);
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setReg(miscReg, val);
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if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
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if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
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hSTickCompare->deschedule();
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time = (hstick_cmpr & mask(63)) - (stick & mask(63));
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time = ((int64_t)(hstick_cmpr & mask(63)) + (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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if (!(hstick_cmpr & ~mask(63)) && time > 0)
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hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
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warn ("writing to hsTICK compare register value %#X\n", val);
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break;
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@ -191,12 +193,25 @@ MiscRegFile::processTickCompare(ThreadContext *tc)
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void
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MiscRegFile::processSTickCompare(ThreadContext *tc)
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{
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panic("tick compare not implemented\n");
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// since our microcode instructions take two cycles we need to check if
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// we're actually at the correct cycle or we need to wait a little while
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// more
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int ticks;
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ticks = (stick_cmpr & mask(63)) - tc->getCpuPtr()->instCount();
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assert(ticks >= 0 && "stick compare missed interrupt cycle");
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if (ticks == 0) {
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DPRINTF(Timer, "STick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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tc->getCpuPtr()->checkInterrupts = true;
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} else
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sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
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}
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void
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MiscRegFile::processHSTickCompare(ThreadContext *tc)
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{
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panic("tick compare not implemented\n");
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panic("hstick compare not implemented\n");
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}
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