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fix softint and partially implement hstick interrupts need to figure out how to do the acutal interrupting still

Browse source 
src/arch/sparc/miscregfile.cc:
    fix softint and fprs in miscregfile

--HG--
extra : convert_revision : cf98bd9c172e20f328f18e07dd05f63f37f14c87
This commit is contained in:
Ali Saidi 2007-01-08 17:09:48 -05:00
parent 4a8078192d
commit 2f4239a685
2 changed files with 27 additions and 7 deletions
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10
src/arch/sparc/miscregfile.cc
View file

@ -327,7 +327,11 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
mbits(tick,63,63);
case MISCREG_FPRS:
warn("FPRS register read and FPU stuff not really implemented\n");
return fprs;
// in legion if fp is enabled du and dl are set
if (fprs & 0x4)
return 0x7;
else
return 0;
case MISCREG_PCR:
case MISCREG_PIC:
panic("Performance Instrumentation not impl\n");
@ -399,7 +403,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
gsr = val;
break;
case MISCREG_SOFTINT:
softint |= val;
softint = val;
break;
case MISCREG_TICK_CMPR:
tick_cmpr = val;
@ -637,6 +641,8 @@ void MiscRegFile::setRegWithEffect(int miscReg,
break;
case MISCREG_PIL:
case MISCREG_SOFTINT:
case MISCREG_SOFTINT_SET:
case MISCREG_SOFTINT_CLR:
case MISCREG_TICK_CMPR:
case MISCREG_STICK_CMPR:
case MISCREG_HINTP:

24
src/arch/sparc/ua2005.cc
View file

@ -51,9 +51,9 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
break;
case MISCREG_SOFTINT_CLR:
return setRegWithEffect(miscReg, ~val & softint, tc);
return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
case MISCREG_SOFTINT_SET:
return setRegWithEffect(miscReg, val | softint, tc);
return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
case MISCREG_TICK_CMPR:
if (tickCompare == NULL)
@ -119,11 +119,11 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
setReg(miscReg, val);
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
hSTickCompare->deschedule();
time = ((int64_t)(hstick_cmpr & mask(63)) + (int64_t)stick) -
time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
tc->getCpuPtr()->instCount();
if (!(hstick_cmpr & ~mask(63)) && time > 0)
hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
warn ("writing to hsTICK compare register value %#X\n", val);
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
break;
case MISCREG_HPSTATE:
@ -213,6 +213,20 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
void
MiscRegFile::processHSTickCompare(ThreadContext *tc)
{
panic("hstick compare not implemented\n");
// since our microcode instructions take two cycles we need to check if
// we're actually at the correct cycle or we need to wait a little while
// more
int ticks;
ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
tc->getCpuPtr()->instCount();
assert(ticks >= 0 && "hstick compare missed interrupt cycle");
if (ticks == 0) {
DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
(stick_cmpr & mask(63)));
tc->getCpuPtr()->checkInterrupts = true;
// Need to do something to cause interrupt to happen here !!! @todo
} else
sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
}