Support for twin loads.
src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
--HG--
extra : convert_revision : ad42821a97dcda17744875b1e5dc00a9642e59b7
This commit is contained in:
Gabe Black
parent
fe73760388
commit
b9d069167c
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@ -1030,7 +1030,7 @@ decode OP default Unknown::unknown()
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0x00: lduw({{Rd = Mem.uw;}});
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0x01: ldub({{Rd = Mem.ub;}});
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0x02: lduh({{Rd = Mem.uhw;}});
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0x03: ldd({{
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0x03: ldtw({{
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uint64_t val = Mem.udw;
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RdLow = val<31:0>;
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RdHigh = val<63:32>;
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@ -1040,7 +1040,7 @@ decode OP default Unknown::unknown()
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0x04: stw({{Mem.uw = Rd.sw;}});
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0x05: stb({{Mem.ub = Rd.sb;}});
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0x06: sth({{Mem.uhw = Rd.shw;}});
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0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
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0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
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}
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format Load {
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0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
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@ -1060,7 +1060,7 @@ decode OP default Unknown::unknown()
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0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
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0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
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0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
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0x13: ldda({{
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0x13: ldtwa({{
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uint64_t val = Mem.udw;
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RdLow = val<31:0>;
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RdHigh = val<63:32>;
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@ -1070,7 +1070,7 @@ decode OP default Unknown::unknown()
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0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
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0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
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0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
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0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
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0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
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}
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format LoadAlt {
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0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
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@ -91,6 +91,65 @@ output header {{
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};
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}};
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output header {{
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class TwinMem : public SparcMacroInst
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{
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protected:
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// Constructor
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// We make the assumption that all block memory operations
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// Will take 8 instructions to execute
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TwinMem(const char *mnem, ExtMachInst _machInst) :
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SparcMacroInst(mnem, _machInst, No_OpClass, 8)
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{}
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};
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class TwinMemImm : public BlockMem
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{
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protected:
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// Constructor
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TwinMemImm(const char *mnem, ExtMachInst _machInst) :
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BlockMem(mnem, _machInst)
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{}
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};
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class TwinMemMicro : public SparcMicroInst
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{
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protected:
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// Constructor
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TwinMemMicro(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, int8_t _offset) :
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SparcMicroInst(mnem, _machInst, __opClass),
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offset(_offset)
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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const int8_t offset;
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};
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class TwinMemImmMicro : public BlockMemMicro
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{
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protected:
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// Constructor
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TwinMemImmMicro(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, int8_t _offset) :
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BlockMemMicro(mnem, _machInst, __opClass, _offset),
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imm(sext<13>(SIMM13))
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{}
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std::string generateDisassembly(Addr pc,
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const SymbolTable *symtab) const;
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const int32_t imm;
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};
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}};
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output decoder {{
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std::string BlockMemMicro::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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@ -242,6 +301,39 @@ def template BlockMemDeclare {{
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};
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}};
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def template TwinMemDeclare {{
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/**
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* Static instruction class for a block memory operation
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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//Constructor
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%(class_name)s(ExtMachInst machInst);
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protected:
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class %(class_name)s_0 : public %(base_class)sMicro
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{
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public:
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//Constructor
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%(class_name)s_0(ExtMachInst machInst);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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class %(class_name)s_1 : public %(base_class)sMicro
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{
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public:
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//Constructor
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%(class_name)s_1(ExtMachInst machInst);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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};
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}};
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// Basic instruction class constructor template.
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def template BlockMemConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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@ -259,6 +351,17 @@ def template BlockMemConstructor {{
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}
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}};
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// Basic instruction class constructor template.
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def template TwinMemConstructor {{
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst)
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{
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%(constructor)s;
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microOps[0] = new %(class_name)s_0(machInst);
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microOps[1] = new %(class_name)s_1(machInst);
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}
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}};
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def template BlockMemMicroConstructor {{
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inline %(class_name)s::
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%(class_name)s_%(micro_pc)s::
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@ -312,6 +415,47 @@ let {{
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asi, opt_flags);
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faultCode = ''
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return (header_output, decoder_output, exec_output, decode_block)
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def doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags):
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addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
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addrCalcImm = 'EA = Rs1 + imm + offset;'
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iop = InstObjParams(name, Name, 'TwinMem', code, opt_flags)
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iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', code, opt_flags)
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header_output = TwinMemDeclare.subst(iop) + TwinMemDeclare.subst(iop_imm)
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decoder_output = TwinMemConstructor.subst(iop) + TwinMemConstructor.subst(iop_imm)
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decode_block = ROrImmDecode.subst(iop)
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matcher = re.compile(r'RdTwin')
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exec_output = ''
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for microPc in range(2):
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flag_code = ''
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pcedCode = ''
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if (microPc == 1):
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flag_code = "flags[IsLastMicroOp] = true;"
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pcedCode = matcher.sub("RdHigh", code)
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else:
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flag_code = "flags[IsDelayedCommit] = true;"
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pcedCode = matcher.sub("RdLow", code)
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iop = InstObjParams(name, Name, 'TwinMem', pcedCode,
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opt_flags, {"ea_code": addrCalcReg,
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"fault_check": faultCode, "micro_pc": microPc,
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"set_flags": flag_code})
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iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', pcedCode,
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opt_flags, {"ea_code": addrCalcImm,
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"fault_check": faultCode, "micro_pc": microPc,
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"set_flags": flag_code})
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decoder_output += BlockMemMicroConstructor.subst(iop)
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decoder_output += BlockMemMicroConstructor.subst(iop_imm)
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exec_output += doDualSplitExecute(
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pcedCode, addrCalcReg, addrCalcImm, execute, faultCode,
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makeMicroName(name, microPc),
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makeMicroName(name + "Imm", microPc),
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makeMicroName(Name, microPc),
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makeMicroName(Name + "Imm", microPc),
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asi, opt_flags);
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faultCode = ''
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return (header_output, decoder_output, exec_output, decode_block)
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}};
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def format BlockLoad(code, asi, *opt_flags) {{
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@ -337,3 +481,11 @@ def format BlockStore(code, asi, *opt_flags) {{
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decode_block) = doBlockMemFormat(code, faultCode,
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StoreExecute, name, Name, asi, opt_flags)
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}};
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def format TwinLoad(code, asi, *opt_flags) {{
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faultCode = AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck
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(header_output,
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decoder_output,
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exec_output,
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decode_block) = doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags)
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}};
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@ -284,6 +284,12 @@ let {{
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else if(EA & 0x3f)
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fault = new MemAddressNotAligned;
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'''
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TwinAlignmentFaultCheck = '''
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if(RD & 0xe)
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fault = new IllegalInstruction;
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else if(EA & 0x1f)
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fault = new MemAddressNotAligned;
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'''
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# XXX Need to take care of pstate.hpriv as well. The lower ASIs
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# are split into ones that are available in priv and hpriv, and
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# those that are only available in hpriv
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@ -57,6 +57,9 @@ def operands {{
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# For clarity, descriptions that depend on unsigned behavior should
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# explicitly specify '.uq'.
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'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
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# For microcoded twin load instructions, RdTwin appears in the "code"
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# for the instruction and is replaced by RdLow or RdHigh by the format
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# before it's processed by the iop.
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'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
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'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
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'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
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