fix twinx loads a little bit
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle
src/arch/sparc/isa/formats/mem/blockmem.isa:
twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
fix the fault check for twinx
src/arch/sparc/tlb.cc:
tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
don't halt on a couple more instruction (ldx, stx) when things differ
beacuse of the way tlb faults are handled in legion.
--HG--
extra : convert_revision : 1e156dead6ebd58b257213625ed63c3793ef4b71
This commit is contained in:
Ali Saidi
parent
6841f863c5
commit
5e9d8795f2
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@ -101,7 +101,7 @@ output header {{
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// We make the assumption that all block memory operations
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// Will take 8 instructions to execute
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TwinMem(const char *mnem, ExtMachInst _machInst) :
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SparcMacroInst(mnem, _machInst, No_OpClass, 8)
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SparcMacroInst(mnem, _machInst, No_OpClass, 2)
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{}
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};
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@ -285,9 +285,9 @@ let {{
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fault = new MemAddressNotAligned;
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'''
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TwinAlignmentFaultCheck = '''
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if(RD & 0xe)
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if(RD & 0x1)
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fault = new IllegalInstruction;
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else if(EA & 0x1f)
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else if(EA & 0xf)
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fault = new MemAddressNotAligned;
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'''
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# XXX Need to take care of pstate.hpriv as well. The lower ASIs
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@ -124,7 +124,8 @@ TLB::insert(Addr va, int partition_id, int context_id, bool real,
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lookupTable.erase(i);
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}
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lookupTable.insert(new_entry->range, new_entry);;
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i = lookupTable.insert(new_entry->range, new_entry);
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assert(i != lookupTable.end());
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// If all entries have there used bit set, clear it on them all, but the
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// one we just inserted
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@ -148,7 +149,7 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id)
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va, partition_id, context_id, real);
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// Assemble full address structure
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tr.va = va;
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tr.size = va + MachineBytes;
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tr.size = MachineBytes;
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tr.contextId = context_id;
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tr.partitionId = partition_id;
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tr.real = real;
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@ -180,6 +181,7 @@ TLB::lookup(Addr va, int partition_id, bool real, int context_id)
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void
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TLB::dumpAll()
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{
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MapIter i;
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for (int x = 0; x < size; x++) {
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if (tlb[x].valid) {
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DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
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@ -196,11 +198,14 @@ TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
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TlbRange tr;
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MapIter i;
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DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
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va, partition_id, context_id, real);
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cacheValid = false;
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// Assemble full address structure
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tr.va = va;
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tr.size = va + MachineBytes;
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tr.size = MachineBytes;
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tr.contextId = context_id;
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tr.partitionId = partition_id;
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tr.real = real;
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@ -208,6 +213,7 @@ TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
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// Demap any entry that conflicts
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i = lookupTable.find(tr);
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if (i != lookupTable.end()) {
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DPRINTF(IPR, "TLB: Demapped page\n");
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i->second->valid = false;
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if (i->second->used) {
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i->second->used = false;
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@ -221,6 +227,8 @@ void
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TLB::demapContext(int partition_id, int context_id)
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{
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int x;
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DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
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partition_id, context_id);
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cacheValid = false;
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for (x = 0; x < size; x++) {
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if (tlb[x].range.contextId == context_id &&
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@ -239,6 +247,7 @@ void
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TLB::demapAll(int partition_id)
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{
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int x;
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DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
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cacheValid = false;
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for (x = 0; x < size; x++) {
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if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
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@ -884,6 +893,9 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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int part_insert;
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int entry_insert = -1;
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bool real_insert;
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bool ignore;
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int part_id;
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int ctx_id;
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PageTableEntry pte;
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DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
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@ -1003,6 +1015,41 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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PageTableEntry::sun4u);
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insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
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break;
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case ASI_IMMU_DEMAP:
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ignore = false;
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ctx_id = -1;
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part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
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switch (bits(va,5,4)) {
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case 0:
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ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
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break;
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case 1:
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ignore = true;
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break;
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case 3:
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ctx_id = 0;
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break;
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default:
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ignore = true;
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}
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switch(bits(va,7,6)) {
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case 0: // demap page
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if (!ignore)
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tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
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bits(va,9,9), ctx_id);
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break;
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case 1: //demap context
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if (!ignore)
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tc->getITBPtr()->demapContext(part_id, ctx_id);
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break;
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case 2:
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tc->getITBPtr()->demapAll(part_id);
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break;
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default:
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panic("Invalid type for IMMU demap\n");
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}
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break;
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case ASI_DMMU:
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switch (va) {
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case 0x30:
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@ -1015,6 +1062,40 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
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goto doMmuWriteError;
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}
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break;
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case ASI_DMMU_DEMAP:
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ignore = false;
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ctx_id = -1;
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part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
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switch (bits(va,5,4)) {
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case 0:
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ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
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break;
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case 1:
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ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
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break;
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case 3:
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ctx_id = 0;
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break;
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default:
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ignore = true;
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}
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switch(bits(va,7,6)) {
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case 0: // demap page
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if (!ignore)
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demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
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break;
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case 1: //demap context
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if (!ignore)
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demapContext(part_id, ctx_id);
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break;
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case 2:
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demapAll(part_id);
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break;
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default:
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panic("Invalid type for IMMU demap\n");
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}
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break;
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default:
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doMmuWriteError:
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panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
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@ -401,7 +401,11 @@ Trace::InstRecord::dump(ostream &outs)
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diffCcr || diffTl || diffGl || diffAsi || diffPil ||
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diffCwp || diffCansave || diffCanrestore ||
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diffOtherwin || diffCleanwin)
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&& !((staticInst->machInst & 0xC1F80000) == 0x81D00000)) {
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&& !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
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&& !((staticInst->machInst & 0xC1F80000) == 0xC0580000)
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&& !((staticInst->machInst & 0xC1F80000) == 0xC0000000)
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&& !((staticInst->machInst & 0xC1F80000) == 0xC0700000)) {
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outs << "Differences found between M5 and Legion:";
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if (diffPC)
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outs << " [PC]";
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