2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
2016-10-14 00:21:40 +02:00
sim_seconds 2.905298 # Number of seconds simulated
sim_ticks 2905297782500 # Number of ticks simulated
final_tick 2905297782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-10-19 12:20:04 +02:00
host_inst_rate 1078702 # Simulator instruction rate (inst/s)
host_op_rate 1300576 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27866902585 # Simulator tick rate (ticks/s)
host_mem_usage 582552 # Number of bytes of host memory used
host_seconds 104.26 # Real time elapsed on the host
2016-10-14 00:21:40 +02:00
sim_insts 112461365 # Number of instructions simulated
sim_ops 135593151 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::cpu.inst 1184612 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8933156 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_read::total 10119304 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1184612 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1184612 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7531136 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_written::total 7548660 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_reads::cpu.inst 26963 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 140100 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_reads::total 167087 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117674 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_writes::total 122055 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_read::cpu.inst 407742 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3074782 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3483052 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 407742 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 407742 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2592208 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2598240 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2592208 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_total::cpu.inst 407742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3080813 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6081292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 167087 # Number of read requests accepted
system.physmem.writeReqs 122055 # Number of write requests accepted
system.physmem.readBursts 167087 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 122055 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10685312 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue
system.physmem.bytesWritten 7561344 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10119304 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7548660 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::0 9954 # Per bank write bursts
system.physmem.perBankRdBursts::1 9813 # Per bank write bursts
system.physmem.perBankRdBursts::2 10094 # Per bank write bursts
system.physmem.perBankRdBursts::3 9518 # Per bank write bursts
system.physmem.perBankRdBursts::4 18811 # Per bank write bursts
system.physmem.perBankRdBursts::5 10188 # Per bank write bursts
system.physmem.perBankRdBursts::6 10467 # Per bank write bursts
system.physmem.perBankRdBursts::7 10858 # Per bank write bursts
system.physmem.perBankRdBursts::8 9262 # Per bank write bursts
system.physmem.perBankRdBursts::9 10094 # Per bank write bursts
system.physmem.perBankRdBursts::10 9505 # Per bank write bursts
system.physmem.perBankRdBursts::11 9184 # Per bank write bursts
system.physmem.perBankRdBursts::12 9983 # Per bank write bursts
system.physmem.perBankRdBursts::13 9847 # Per bank write bursts
system.physmem.perBankRdBursts::14 9958 # Per bank write bursts
system.physmem.perBankRdBursts::15 9422 # Per bank write bursts
system.physmem.perBankWrBursts::0 7103 # Per bank write bursts
system.physmem.perBankWrBursts::1 7218 # Per bank write bursts
system.physmem.perBankWrBursts::2 7869 # Per bank write bursts
system.physmem.perBankWrBursts::3 7374 # Per bank write bursts
system.physmem.perBankWrBursts::4 7424 # Per bank write bursts
system.physmem.perBankWrBursts::5 7558 # Per bank write bursts
system.physmem.perBankWrBursts::6 7579 # Per bank write bursts
system.physmem.perBankWrBursts::7 7921 # Per bank write bursts
system.physmem.perBankWrBursts::8 6916 # Per bank write bursts
system.physmem.perBankWrBursts::9 7516 # Per bank write bursts
system.physmem.perBankWrBursts::10 7047 # Per bank write bursts
system.physmem.perBankWrBursts::11 7122 # Per bank write bursts
system.physmem.perBankWrBursts::12 7779 # Per bank write bursts
system.physmem.perBankWrBursts::13 7383 # Per bank write bursts
system.physmem.perBankWrBursts::14 7451 # Per bank write bursts
system.physmem.perBankWrBursts::15 6886 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-10-14 00:21:40 +02:00
system.physmem.numWrRetry 65 # Number of times write queue was full causing retry
system.physmem.totGap 2905297420500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.readPktSize::6 157515 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.writePktSize::6 117674 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 166128 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 554 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::15 1886 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2786 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5910 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5767 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6250 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6643 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8271 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8725 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7065 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6628 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 401 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 376 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 293 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 204 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 193 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 57323 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 318.311882 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 186.988870 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 336.470779 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 20402 35.59% 35.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14531 25.35% 60.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5716 9.97% 70.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3104 5.41% 76.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2370 4.13% 80.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1421 2.48% 82.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1241 2.16% 85.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 946 1.65% 86.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7592 13.24% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 57323 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5761 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.979865 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 590.542998 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 5760 99.98% 99.98% # Reads before turning the bus around for writes
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
2016-10-14 00:21:40 +02:00
system.physmem.rdPerTurnAround::total 5761 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5761 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.507898 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.546505 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 15.055833 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5040 87.48% 87.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 23 0.40% 87.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 68 1.18% 89.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 38 0.66% 89.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 294 5.10% 94.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 33 0.57% 95.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 2 0.03% 95.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 7 0.12% 95.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 6 0.10% 95.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 3 0.05% 95.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 2 0.03% 95.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 5 0.09% 95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 158 2.74% 98.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 4 0.07% 98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 6 0.10% 98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 3 0.05% 98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 10 0.17% 98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.03% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.03% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 11 0.19% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.03% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 3 0.05% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 8 0.14% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 7 0.12% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 4 0.07% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 4 0.07% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads
2016-08-12 15:12:59 +02:00
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads
2016-10-14 00:21:40 +02:00
system.physmem.wrPerTurnAround::156-159 2 0.03% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 3 0.05% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 2 0.03% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5761 # Writes before turning the bus around for reads
system.physmem.totQLat 4504540500 # Total ticks spent queuing
system.physmem.totMemAccLat 7635003000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 834790000 # Total ticks spent in databus transfers
system.physmem.avgQLat 26980.08 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-10-14 00:21:40 +02:00
system.physmem.avgMemAccLat 45730.08 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.68 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.48 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-03-02 11:04:20 +01:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2014-10-30 05:18:29 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2016-10-14 00:21:40 +02:00
system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing
system.physmem.readRowHits 138094 # Number of row buffer hits during reads
system.physmem.writeRowHits 89686 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes
system.physmem.avgGap 10047995.17 # Average gap between requests
system.physmem.pageHitRate 79.89 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 210115920 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 111679260 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 640479420 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 313440120 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 6609223920.000002 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 4735061820 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 414343200 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 13903412640 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 9310120320 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 682719565725 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 718969243965 # Total energy per rank (pJ)
system.physmem_0.averagePower 247.468348 # Core power per rank (mW)
system.physmem_0.totalIdleTime 2893307612500 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 778413000 # Time in different power states
system.physmem_0.memoryStateTime::REF 2810438000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 2839095824500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 24245244750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 7877734000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 30490128250 # Time in different power states
system.physmem_1.actEnergy 199177440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 105861525 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 551600700 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 303282000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 6621516720.000002 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 4536550200 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 409678080 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 13514783790 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 9490661760 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 682993594335 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 718728215280 # Total energy per rank (pJ)
system.physmem_1.averagePower 247.385386 # Core power per rank (mW)
system.physmem_1.totalIdleTime 2894278953000 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 777246000 # Time in different power states
system.physmem_1.memoryStateTime::REF 2816412000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 2839926040500 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 24715420500 # Time in different power states
system.physmem_1.memoryStateTime::ACT 7425105000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 29637558500 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2014-11-03 17:14:42 +01:00
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 9547 # Table walker walks requested
system.cpu.dtb.walker.walksShort 9547 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1253 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8294 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples 9547 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0 9547 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 9547 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 7383 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 9942.435324 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 8397.692517 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 6587.109188 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-16383 6605 89.46% 89.46% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::16384-32767 773 10.47% 99.93% # Table walker service (enqueue to completion) latency
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.walkCompletionTime::total 7383 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6177 83.67% 83.67% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1206 16.33% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7383 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9547 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9547 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7383 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7383 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 16930 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.read_hits 24520121 # DTB read hits
system.cpu.dtb.read_misses 8133 # DTB read misses
system.cpu.dtb.write_hits 19605715 # DTB write hits
system.cpu.dtb.write_misses 1414 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-10-14 00:21:40 +02:00
system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-10-14 00:21:40 +02:00
system.cpu.dtb.prefetch_faults 1628 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2014-10-30 05:18:29 +01:00
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
2016-10-14 00:21:40 +02:00
system.cpu.dtb.read_accesses 24528254 # DTB read accesses
system.cpu.dtb.write_accesses 19607129 # DTB write accesses
2011-02-08 04:23:11 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.hits 44125836 # DTB hits
system.cpu.dtb.misses 9547 # DTB misses
system.cpu.dtb.accesses 44135383 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 4763 # Table walker walks requested
system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 10156.853282 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 8221.468352 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7284.204444 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::8192-16383 769 24.74% 83.33% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-24575 516 16.60% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 1002711000 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 1002711000 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 115559307 # ITB inst hits
system.cpu.itb.inst_misses 4763 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2016-06-21 17:42:04 +02:00
system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-10-14 00:21:40 +02:00
system.cpu.itb.inst_accesses 115564070 # ITB inst accesses
system.cpu.itb.hits 115559307 # DTB hits
system.cpu.itb.misses 4763 # DTB misses
system.cpu.itb.accesses 115564070 # DTB accesses
system.cpu.numPwrStateTransitions 6066 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean 887205638.526871 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 17463817933.974155 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu.pwrStateClkGateDist::max_value 499962880972 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON 214403080848 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 2690894701652 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5810595565 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
system.cpu.committedInsts 112461365 # Number of instructions committed
system.cpu.committedOps 135593151 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 119897812 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11226 # Number of float alu accesses
system.cpu.num_func_calls 9894928 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15231225 # number of instructions that are conditional controls
system.cpu.num_int_insts 119897812 # number of integer instructions
system.cpu.num_fp_insts 11226 # number of float instructions
system.cpu.num_int_register_reads 218061607 # number of times the integer registers were read
system.cpu.num_int_register_writes 82648736 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8514 # number of times the floating registers were read
2014-10-30 05:18:29 +01:00
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
2016-10-14 00:21:40 +02:00
system.cpu.num_cc_register_reads 489758493 # number of times the CC registers were read
system.cpu.num_cc_register_writes 51897030 # number of times the CC registers were written
system.cpu.num_mem_refs 45406070 # number of memory refs
system.cpu.num_load_insts 24842315 # Number of load instructions
system.cpu.num_store_insts 20563755 # Number of store instructions
system.cpu.num_idle_cycles 5381789403.302147 # Number of idle cycles
system.cpu.num_busy_cycles 428806161.697852 # Number of busy cycles
system.cpu.not_idle_fraction 0.073797 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.926203 # Percentage of idle cycles
system.cpu.Branches 25920117 # Number of branches fetched
2014-10-30 05:18:29 +01:00
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::IntAlu 93182494 67.18% 67.18% # Class of executed instruction
system.cpu.op_class::IntMult 114558 0.08% 67.26% # Class of executed instruction
2014-10-30 05:18:29 +01:00
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::FloatMultAcc 0 0.00% 67.26% # Class of executed instruction
2014-10-30 05:18:29 +01:00
system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::FloatMisc 0 0.00% 67.26% # Class of executed instruction
2014-10-30 05:18:29 +01:00
system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::SimdFloatMisc 8431 0.01% 67.27% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::MemRead 24839607 17.91% 85.17% # Class of executed instruction
system.cpu.op_class::MemWrite 20555241 14.82% 99.99% # Class of executed instruction
system.cpu.op_class::FloatMemRead 2708 0.00% 99.99% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 8514 0.01% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::total 138713890 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 821351 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.816254 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 43232645 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 821863 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 52.603226 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.816254 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.tag_accesses 177108261 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 177108261 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 23111024 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23111024 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18823159 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18823159 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 392414 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 392414 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443071 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 443071 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460161 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460161 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 41934183 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41934183 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42326597 # number of overall hits
system.cpu.dcache.overall_hits::total 42326597 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 401452 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 401452 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 298737 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 298737 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 118712 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 118712 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22861 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22861 # number of LoadLockedReq misses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_misses::cpu.data 700189 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 700189 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 818901 # number of overall misses
system.cpu.dcache.overall_misses::total 818901 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6440957000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6440957000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 14361709000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 14361709000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 300793500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 300793500 # number of LoadLockedReq miss cycles
2016-08-12 15:12:59 +02:00
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 20802666000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 20802666000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 20802666000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 20802666000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23512476 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23512476 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19121896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19121896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511126 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511126 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465932 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 465932 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460163 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460163 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42634372 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42634372 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43145498 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43145498 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017074 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.017074 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015623 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015623 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232256 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.232256 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.049065 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.049065 # miss rate for LoadLockedReq accesses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.016423 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016423 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018980 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018980 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16044.152227 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16044.152227 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48074.758065 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48074.758065 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13157.495298 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13157.495298 # average LoadLockedReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29710.072566 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29710.072566 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25403.151297 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25403.151297 # average overall miss latency
2016-08-12 15:12:59 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.dcache.writebacks::writebacks 685561 # number of writebacks
system.cpu.dcache.writebacks::total 685561 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 705 # number of ReadReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14335 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14335 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 705 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 705 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 705 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 705 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400747 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 400747 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298737 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 298737 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116693 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 116693 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8526 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 699484 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 699484 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 816177 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 816177 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015919500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015919500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14062972000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 14062972000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1582474000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1582474000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 120274000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 120274000 # number of LoadLockedReq MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20078891500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 20078891500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21661365500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 21661365500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284842500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284842500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284842500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284842500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017044 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017044 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228306 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228306 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018299 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018299 # mshr miss rate for LoadLockedReq accesses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016407 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016407 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018917 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15011.764280 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15011.764280 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47074.758065 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47074.758065 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13561.001945 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13561.001945 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14106.732348 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14106.732348 # average LoadLockedReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28705.290614 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28705.290614 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26540.034208 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26540.034208 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201838.348642 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201838.348642 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.938938 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.938938 # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 1700003 # number of replacements
system.cpu.icache.tags.tagsinuse 510.693079 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 113858786 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1700515 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 66.955473 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 26307743500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.693079 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997447 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.tag_accesses 117259828 # Number of tag accesses
system.cpu.icache.tags.data_accesses 117259828 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 113858786 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 113858786 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 113858786 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 113858786 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 113858786 # number of overall hits
system.cpu.icache.overall_hits::total 113858786 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1700521 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1700521 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1700521 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1700521 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1700521 # number of overall misses
system.cpu.icache.overall_misses::total 1700521 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24021238000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24021238000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24021238000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24021238000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24021238000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24021238000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 115559307 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 115559307 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 115559307 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 115559307 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 115559307 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 115559307 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14125.810854 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14125.810854 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14125.810854 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14125.810854 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.icache.writebacks::writebacks 1700003 # number of writebacks
system.cpu.icache.writebacks::total 1700003 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700521 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1700521 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1700521 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1700521 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1700521 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1700521 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22320717000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22320717000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22320717000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22320717000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22320717000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22320717000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014716 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.014716 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.014716 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13125.810854 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13125.810854 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13125.810854 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13125.810854 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 88035 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65011.446283 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4854285 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 153426 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 31.639259 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 146352515000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050747 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041160 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9651.725117 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 55356.629260 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 # Average percentage of cache occupancy
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147274 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.844675 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.991996 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4355 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60952 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 40277345 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40277345 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 4991 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2669 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 7660 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 685561 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 685561 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1667726 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1667726 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2795 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 2795 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 168131 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 168131 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682557 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1682557 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513829 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 513829 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 4991 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2669 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1682557 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 681960 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2372177 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 4991 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2669 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1682557 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 681960 # number of overall hits
system.cpu.l2cache.overall_hits::total 2372177 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 19 # number of UpgradeReq misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 127792 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 127792 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17948 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 17948 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12137 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 12137 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 17948 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 139929 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 157886 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 17948 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 139929 # number of overall misses
system.cpu.l2cache.overall_misses::total 157886 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1334500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 555500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 555500 # number of UpgradeReq miss cycles
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11816022500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 11816022500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2043061500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2043061500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1517166500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1517166500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2043061500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 13333189000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 15377585000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2043061500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 13333189000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 15377585000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 4998 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2671 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7669 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 685561 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 685561 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1667726 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1667726 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2814 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2814 # number of UpgradeReq accesses(hits+misses)
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 295923 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 295923 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700505 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1700505 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525966 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 525966 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 4998 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2671 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1700505 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 821889 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2530063 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 4998 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2671 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1700505 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 821889 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2530063 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001401 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000749 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001174 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006752 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006752 # miss rate for UpgradeReq accesses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.431842 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.431842 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010555 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010555 # miss rate for ReadCleanReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023076 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023076 # miss rate for ReadSharedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001401 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000749 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010555 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.170253 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.062404 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001401 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000749 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010555 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.170253 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.062404 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164928.571429 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 148277.777778 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29236.842105 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29236.842105 # average UpgradeReq miss latency
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92462.928039 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92462.928039 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 113832.265433 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 113832.265433 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125003.419296 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125003.419296 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 97396.760954 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164928.571429 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 113832.265433 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95285.387589 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 97396.760954 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.writebacks::writebacks 81484 # number of writebacks
system.cpu.l2cache.writebacks::total 81484 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 127792 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 127792 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17948 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17948 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12137 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12137 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 17948 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 139929 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 157886 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 17948 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 139929 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 157886 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 365500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 365500 # number of UpgradeReq MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10538102500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10538102500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1863581500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1863581500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1395796500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1395796500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1863581500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11933899000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 13798725000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1863581500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11933899000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 13798725000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895497500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527925500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895497500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527925500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001174 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006752 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006752 # mshr miss rate for UpgradeReq accesses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.431842 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.431842 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010555 # mshr miss rate for ReadCleanReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.062404 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.062404 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138277.777778 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19236.842105 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19236.842105 # average UpgradeReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82462.928039 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82462.928039 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 103832.265433 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 103832.265433 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115003.419296 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115003.419296 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.494829 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.945717 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100388.194527 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.566119 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 5065968 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543576 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 219 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 219 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 67217 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2293895 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 767045 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1700003 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 142341 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2814 # Transaction distribution
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 295923 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 295923 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700521 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 526163 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119073 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2588406 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11887 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22839 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7742205 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217668600 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96672157 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10684 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 19992 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 314371433 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 112178 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 5305776 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 2712615 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.021718 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.145761 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::0 2653703 97.83% 97.83% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 58912 2.17% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::total 2712615 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4970051500 # Layer occupancy (ticks)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 347876 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 2559803500 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 1279174000 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 17841000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 30159 # Transaction distribution
system.iobus.trans_dist::ReadResp 30159 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72868 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178346 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer23.occupancy 6292000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer25.occupancy 187581870 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 36400 # number of replacements
system.iocache.tags.tagsinuse 1.079755 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.iocache.tags.warmup_cycle 310620847000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.079755 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.067485 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.067485 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.iocache.tags.tag_accesses 327906 # Number of tag accesses
system.iocache.tags.data_accesses 327906 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses
system.iocache.ReadReq_misses::total 210 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2016-10-14 00:21:40 +02:00
system.iocache.demand_misses::realview.ide 36434 # number of demand (read+write) misses
system.iocache.demand_misses::total 36434 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 36434 # number of overall misses
system.iocache.overall_misses::total 36434 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4367688494 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4367688494 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 4401754870 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 4401754870 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 4401754870 # number of overall miss cycles
system.iocache.overall_miss_latency::total 4401754870 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.iocache.demand_accesses::realview.ide 36434 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 36434 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 36434 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 36434 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120574.439432 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120574.439432 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 120814.482901 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 120814.482901 # average overall miss latency
2016-02-10 10:08:27 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-02-10 10:08:27 +01:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 210 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2016-10-14 00:21:40 +02:00
system.iocache.demand_mshr_misses::realview.ide 36434 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2554457612 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2554457612 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 2578023988 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 2578023988 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 2578023988 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 2578023988 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70518.374890 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70518.374890 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency
system.membus.snoop_filter.tot_requests 318841 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 128997 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::ReadResp 70464 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
system.membus.trans_dist::WriteResp 27589 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::WritebackDirty 117674 # Transaction distribution
system.membus.trans_dist::CleanEvict 6761 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::UpgradeReq 128 # Transaction distribution
2014-11-12 15:05:25 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::ReadExReq 127683 # Transaction distribution
system.membus.trans_dist::ReadExResp 127683 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 30304 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431348 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 538940 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 611789 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15350844 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15514197 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_size::total 17831317 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 474 # Total snoops (count)
system.membus.snoopTraffic 30208 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 262090 # Request fanout histogram
system.membus.snoop_fanout::mean 0.018417 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.134455 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::0 257263 98.16% 98.16% # Request fanout histogram
system.membus.snoop_fanout::1 4827 1.84% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::total 262090 # Request fanout histogram
system.membus.reqLayer0.occupancy 90471500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.reqLayer2.occupancy 1726500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.reqLayer5.occupancy 819732726 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.respLayer2.occupancy 945419750 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.respLayer3.occupancy 1085624 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-10-14 00:21:40 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
