2011-02-08 04:23:11 +01:00
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---------- Begin Simulation Statistics ----------
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2014-09-20 23:18:53 +02:00
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sim_seconds 2.614572 # Number of seconds simulated
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sim_ticks 2614571564500 # Number of ticks simulated
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final_tick 2614571564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2011-02-08 04:23:11 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2014-10-09 23:52:13 +02:00
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host_inst_rate 393660 # Simulator instruction rate (inst/s)
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host_op_rate 470163 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 17100811132 # Simulator tick rate (ticks/s)
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host_mem_usage 408168 # Number of bytes of host memory used
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host_seconds 152.89 # Real time elapsed on the host
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2014-09-20 23:18:53 +02:00
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sim_insts 60187274 # Number of instructions simulated
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sim_ops 71883961 # Number of ops (including micro ops) simulated
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2014-01-24 22:29:33 +01:00
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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2012-10-25 19:14:42 +02:00
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system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
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2012-10-15 14:09:54 +02:00
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system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
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2013-05-30 18:54:18 +02:00
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system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_read::cpu.inst 704648 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9109336 # Number of bytes read from this memory
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system.physmem.bytes_read::total 132497824 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 704648 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 704648 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3720832 # Number of bytes written to this memory
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2012-10-15 14:09:54 +02:00
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.bytes_written::total 6736904 # Number of bytes written to this memory
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2012-10-25 19:14:42 +02:00
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system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
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2012-10-15 14:09:54 +02:00
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system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
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2013-05-30 18:54:18 +02:00
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system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.num_reads::cpu.inst 17222 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 142359 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15495012 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 58138 # Number of write requests responded to by this memory
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2012-10-15 14:09:54 +02:00
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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2014-09-20 23:18:53 +02:00
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system.physmem.num_writes::total 812156 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 46922943 # Total read bandwidth from this memory (bytes/s)
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2013-05-30 18:54:18 +02:00
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system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
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2014-09-20 23:18:53 +02:00
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system.physmem.bw_read::cpu.inst 269508 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3484065 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 50676687 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 269508 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 269508 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1423113 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1153563 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2576676 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1423113 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 46922943 # Total bandwidth to/from this memory (bytes/s)
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2013-05-30 18:54:18 +02:00
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system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
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2014-09-20 23:18:53 +02:00
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system.physmem.bw_total::cpu.inst 269508 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4637627 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53253363 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15495012 # Number of read requests accepted
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system.physmem.writeReqs 812156 # Number of write requests accepted
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system.physmem.readBursts 15495012 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 812156 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 991563904 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 116864 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6748800 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 132497824 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6736904 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 1826 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 706685 # Number of DRAM write bursts merged with an existing one
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2014-09-03 13:42:59 +02:00
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system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankRdBursts::0 968097 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankRdBursts::1 967810 # Per bank write bursts
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system.physmem.perBankRdBursts::2 967673 # Per bank write bursts
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system.physmem.perBankRdBursts::3 967915 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankRdBursts::4 974446 # Per bank write bursts
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system.physmem.perBankRdBursts::5 968066 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankRdBursts::6 967653 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankRdBursts::7 967482 # Per bank write bursts
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system.physmem.perBankRdBursts::8 968460 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankRdBursts::9 968209 # Per bank write bursts
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system.physmem.perBankRdBursts::10 967967 # Per bank write bursts
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system.physmem.perBankRdBursts::11 967960 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankRdBursts::12 967930 # Per bank write bursts
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system.physmem.perBankRdBursts::13 967880 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankRdBursts::14 967953 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankRdBursts::15 967685 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6670 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6386 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6320 # Per bank write bursts
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system.physmem.perBankWrBursts::3 6360 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6634 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6864 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6659 # Per bank write bursts
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system.physmem.perBankWrBursts::7 6574 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7028 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankWrBursts::9 6769 # Per bank write bursts
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system.physmem.perBankWrBursts::10 6571 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankWrBursts::11 6645 # Per bank write bursts
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2014-09-03 13:42:59 +02:00
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system.physmem.perBankWrBursts::12 6565 # Per bank write bursts
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2014-09-20 23:18:53 +02:00
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system.physmem.perBankWrBursts::13 6383 # Per bank write bursts
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system.physmem.perBankWrBursts::14 6560 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6462 # Per bank write bursts
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2013-11-01 16:56:34 +01:00
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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2014-09-20 23:18:53 +02:00
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system.physmem.totGap 2614567301000 # Total gap between requests
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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2014-09-03 13:42:59 +02:00
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system.physmem.readPktSize::2 6644 # Read request sizes (log2)
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system.physmem.readPktSize::3 15335434 # Read request sizes (log2)
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2013-11-01 16:56:34 +01:00
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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2014-09-20 23:18:53 +02:00
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system.physmem.readPktSize::6 152934 # Read request sizes (log2)
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2013-11-01 16:56:34 +01:00
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 754018 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
2014-09-20 23:18:53 +02:00
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system.physmem.writePktSize::6 58138 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1126447 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 970731 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 976234 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1093523 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 987097 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1054685 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2721121 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 2624601 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 3412795 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 139881 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 116829 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 107818 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 104436 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 19578 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 18770 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 18545 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see
|
2012-10-25 19:14:42 +02:00
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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2014-03-23 16:12:19 +01:00
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
2014-09-20 23:18:53 +02:00
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|
|
system.physmem.wrQLenPdf::15 3703 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::16 3729 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 6107 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::20 6133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 6136 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::22 6126 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::23 6125 # What write queue length does an incoming req see
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|
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|
system.physmem.wrQLenPdf::24 6125 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::25 6125 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 6130 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 6132 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6127 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 6126 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6125 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6124 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6124 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see
|
2014-05-10 00:58:50 +02:00
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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|
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
2014-03-23 16:12:19 +01:00
|
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
|
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.bytesPerActivate::samples 1027284 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::mean 971.798163 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::gmean 905.747967 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::stdev 203.998959 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::0-127 22800 2.22% 2.22% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::128-255 22532 2.19% 4.41% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::256-383 8422 0.82% 5.23% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::384-511 2556 0.25% 5.48% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::512-639 2545 0.25% 5.73% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::640-767 1785 0.17% 5.90% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::768-895 8607 0.84% 6.74% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::896-1023 981 0.10% 6.84% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::1024-1151 957056 93.16% 100.00% # Bytes accessed per row activation
|
|
|
|
|
system.physmem.bytesPerActivate::total 1027284 # Bytes accessed per row activation
|
|
|
|
|
system.physmem.rdPerTurnAround::samples 6124 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::mean 2529.911822 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::stdev 116281.505657 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::0-524287 6119 99.92% 99.92% # Reads before turning the bus around for writes
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.rdPerTurnAround::total 6124 # Reads before turning the bus around for writes
|
|
|
|
|
system.physmem.wrPerTurnAround::samples 6124 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::mean 17.219138 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::gmean 17.190607 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::stdev 0.983110 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::16 2397 39.14% 39.14% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::17 24 0.39% 39.53% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::18 3669 59.91% 99.44% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::19 32 0.52% 99.97% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.wrPerTurnAround::total 6124 # Writes before turning the bus around for reads
|
|
|
|
|
system.physmem.totQLat 400730693500 # Total ticks spent queuing
|
|
|
|
|
system.physmem.totMemAccLat 691227931000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
|
|
|
system.physmem.totBusLat 77465930000 # Total ticks spent in databus transfers
|
|
|
|
|
system.physmem.avgQLat 25864.96 # Average queueing delay per DRAM burst
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgMemAccLat 44614.96 # Average memory access latency per DRAM burst
|
|
|
|
|
system.physmem.avgRdBW 379.25 # Average DRAM read bandwidth in MiByte/s
|
2014-09-03 13:42:59 +02:00
|
|
|
system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s
|
|
|
|
|
system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s
|
2013-11-01 16:56:34 +01:00
|
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
|
|
|
system.physmem.busUtil 2.98 # Data bus utilization in percentage
|
|
|
|
|
system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads
|
|
|
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing
|
|
|
|
|
system.physmem.avgWrQLen 28.13 # Average write queue length when enqueuing
|
|
|
|
|
system.physmem.readRowHits 14482679 # Number of row buffer hits during reads
|
|
|
|
|
system.physmem.writeRowHits 88673 # Number of row buffer hits during writes
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.writeRowHitRate 84.07 # Row buffer hit rate for writes
|
|
|
|
|
system.physmem.avgGap 160332.39 # Average gap between requests
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.memoryStateTime::IDLE 2239359524750 # Time in different power states
|
|
|
|
|
system.physmem.memoryStateTime::REF 87306180000 # Time in different power states
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
2014-09-20 23:18:53 +02:00
|
|
|
system.physmem.memoryStateTime::ACT 287902801500 # Time in different power states
|
2014-05-10 00:58:50 +02:00
|
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
2014-10-09 23:52:13 +02:00
|
|
|
system.physmem.actEnergy::0 3884796720 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem.actEnergy::1 3881470320 # Energy for activate commands per rank (pJ)
|
|
|
|
|
system.physmem.preEnergy::0 2119680750 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem.preEnergy::1 2117865750 # Energy for precharge commands per rank (pJ)
|
|
|
|
|
system.physmem.readEnergy::0 60443307600 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem.readEnergy::1 60403543200 # Energy for read commands per rank (pJ)
|
|
|
|
|
system.physmem.writeEnergy::0 339986160 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem.writeEnergy::1 343329840 # Energy for write commands per rank (pJ)
|
|
|
|
|
system.physmem.refreshEnergy::0 170770888080 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem.refreshEnergy::1 170770888080 # Energy for refresh commands per rank (pJ)
|
|
|
|
|
system.physmem.actBackEnergy::0 155970246555 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem.actBackEnergy::1 156681731385 # Energy for active background per rank (pJ)
|
|
|
|
|
system.physmem.preBackEnergy::0 1431925089750 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem.preBackEnergy::1 1431300980250 # Energy for precharge background per rank (pJ)
|
|
|
|
|
system.physmem.totalEnergy::0 1825453995615 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem.totalEnergy::1 1825499808825 # Total energy per rank (pJ)
|
|
|
|
|
system.physmem.averagePower::0 698.185571 # Core power per rank (mW)
|
|
|
|
|
system.physmem.averagePower::1 698.203093 # Core power per rank (mW)
|
|
|
|
|
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
|
|
|
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
|
|
|
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
|
|
|
|
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::ReadReq 16546657 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadResp 16546657 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.trans_dist::WriteReq 763381 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::WriteResp 763381 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::Writeback 58138 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.trans_dist::ReadExReq 132459 # Transaction distribution
|
|
|
|
|
system.membus.trans_dist::ReadExResp 132459 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894372 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281306 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.pkt_count::total 34952154 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551336 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18949570 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.pkt_size::total 141632962 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
|
|
|
system.membus.snoop_fanout::samples 215583 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::1 215583 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
|
|
|
system.membus.snoop_fanout::total 215583 # Request fanout histogram
|
|
|
|
|
system.membus.reqLayer0.occupancy 1204828500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
|
|
|
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.reqLayer2.occupancy 3334000 # Layer occupancy (ticks)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
|
|
|
|
|
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.reqLayer6.occupancy 17917176000 # Layer occupancy (ticks)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.respLayer1.occupancy 4952454428 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.membus.respLayer2.occupancy 37912905250 # Layer occupancy (ticks)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
|
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
|
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
|
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
|
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteReq 8182 # Transaction distribution
|
|
|
|
|
system.iobus.trans_dist::WriteResp 8182 # Transaction distribution
|
2014-02-19 13:59:46 +01:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 532 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1040 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.pkt_count_system.bridge.master::total 2383082 # Packet count per connected master and slave (bytes)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.iobus.pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes)
|
2014-02-19 13:59:46 +01:00
|
|
|
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.reqLayer2.occupancy 532000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.reqLayer3.occupancy 526000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
|
|
|
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks)
|
|
|
|
|
system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iobus.respLayer1.occupancy 38695381750 # Layer occupancy (ticks)
|
2014-03-23 16:12:19 +01:00
|
|
|
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.read_hits 13160242 # DTB read hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.read_misses 7329 # DTB read misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.write_hits 11228050 # DTB write hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.write_misses 2212 # DTB write misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.read_accesses 13167571 # DTB read accesses
|
|
|
|
|
system.cpu.dtb.write_accesses 11230262 # DTB write accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.hits 24388292 # DTB hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dtb.misses 9541 # DTB misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dtb.accesses 24397833 # DTB accesses
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
|
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.itb.inst_hits 61481095 # ITB inst hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
2014-01-24 22:29:34 +01:00
|
|
|
system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.itb.inst_accesses 61485566 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.hits 61481095 # DTB hits
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.itb.misses 4471 # DTB misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.itb.accesses 61485566 # DTB accesses
|
|
|
|
|
system.cpu.numCycles 5229143129 # number of cpu cycles simulated
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.committedInsts 60187274 # Number of instructions committed
|
|
|
|
|
system.cpu.committedOps 71883961 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.num_int_alu_accesses 64248492 # Number of integer alu accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.num_func_calls 2139801 # number of times a function call or return occured
|
|
|
|
|
system.cpu.num_conditional_control_insts 7549047 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu.num_int_insts 64248492 # number of integer instructions
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.num_fp_insts 10269 # number of float instructions
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.num_int_register_reads 116110622 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 42863098 # number of times the integer registers were written
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.num_cc_register_reads 257769006 # number of times the CC registers were read
|
|
|
|
|
system.cpu.num_cc_register_writes 28995258 # number of times the CC registers were written
|
|
|
|
|
system.cpu.num_mem_refs 25244235 # number of memory refs
|
|
|
|
|
system.cpu.num_load_insts 13512788 # Number of load instructions
|
|
|
|
|
system.cpu.num_store_insts 11731447 # Number of store instructions
|
|
|
|
|
system.cpu.num_idle_cycles 4584209782.584247 # Number of idle cycles
|
|
|
|
|
system.cpu.num_busy_cycles 644933346.415753 # Number of busy cycles
|
|
|
|
|
system.cpu.not_idle_fraction 0.123334 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0.876666 # Percentage of idle cycles
|
|
|
|
|
system.cpu.Branches 10306630 # Number of branches fetched
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.op_class::IntAlu 47577014 65.23% 65.27% # Class of executed instruction
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.op_class::MemRead 13512788 18.53% 83.92% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::MemWrite 11731447 16.08% 100.00% # Class of executed instruction
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
|
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.op_class::total 72939427 # Class of executed instruction
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.kern.inst.quiesce 83004 # number of quiesce instructions executed
|
|
|
|
|
system.cpu.icache.tags.replacements 855897 # number of replacements
|
|
|
|
|
system.cpu.icache.tags.tagsinuse 510.877214 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.tags.total_refs 60624686 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.sampled_refs 856409 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.avg_refs 70.789408 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.tags.warmup_cycle 19623933250 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.877214 # Average occupied blocks per requestor
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997807 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.tags.occ_percent::total 0.997807 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id
|
|
|
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.tags.tag_accesses 62337504 # Number of tag accesses
|
|
|
|
|
system.cpu.icache.tags.data_accesses 62337504 # Number of data accesses
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 60624686 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 60624686 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 60624686 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 60624686 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 60624686 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 60624686 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 856409 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 856409 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 856409 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 856409 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 856409 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 856409 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766778500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 11766778500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11766778500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 11766778500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11766778500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 11766778500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 61481095 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 61481095 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 61481095 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 61481095 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 61481095 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 61481095 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013930 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.013930 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.013930 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13739.671699 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13739.671699 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 13739.671699 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 13739.671699 # average overall miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856409 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 856409 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 856409 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 856409 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 856409 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 856409 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049953500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 10049953500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049953500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 10049953500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049953500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 10049953500 # number of overall MSHR miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 440846250 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 440846250 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013930 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11734.992860 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11734.992860 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11734.992860 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11734.992860 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11734.992860 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11734.992860 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.replacements 62827 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tags.tagsinuse 50749.017881 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.tags.total_refs 1679035 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.sampled_refs 128209 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.avg_refs 13.096077 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.tags.warmup_cycle 2564785024500 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 37681.898715 # Average occupied blocks per requestor
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884636 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000702 # Average occupied blocks per requestor
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6996.424673 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6066.809153 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.574980 # Average percentage of cache occupancy
|
2013-06-27 11:49:51 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106757 # Average percentage of cache occupancy
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092572 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.tags.occ_percent::total 0.774369 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7027 # Occupied blocks per task id
|
|
|
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56159 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id
|
|
|
|
|
system.cpu.l2cache.tags.tag_accesses 17118836 # Number of tag accesses
|
|
|
|
|
system.cpu.l2cache.tags.data_accesses 17118836 # Number of data accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7538 # number of ReadReq hits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3114 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 844199 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 368983 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 1223834 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 595027 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 595027 # number of Writeback hits
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 113476 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 113476 # number of ReadExReq hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7538 # number of demand (read+write) hits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3114 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 844199 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 482459 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 1337310 # number of demand (read+write) hits
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7538 # number of overall hits
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3114 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 844199 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 482459 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 1337310 # number of overall hits
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 9872 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 20475 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2895 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2895 # number of UpgradeReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 134075 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 134075 # number of ReadExReq misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 143947 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 154550 # number of demand (read+write) misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 10596 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 143947 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 154550 # number of overall misses
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 305250 # number of ReadReq miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 150000 # number of ReadReq miss cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 749772500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 732753250 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1482981000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 346985 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 346985 # number of UpgradeReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9334508634 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 9334508634 # number of ReadExReq miss cycles
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 305250 # number of demand (read+write) miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 150000 # number of demand (read+write) miss cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 749772500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10067261884 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 10817489634 # number of demand (read+write) miss cycles
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 305250 # number of overall miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 150000 # number of overall miss cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 749772500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10067261884 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 10817489634 # number of overall miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7543 # number of ReadReq accesses(hits+misses)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3116 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 854795 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 378855 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 1244309 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 595027 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 595027 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2921 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2921 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247551 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 247551 # number of ReadExReq accesses(hits+misses)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7543 # number of demand (read+write) accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3116 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 854795 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 626406 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 1491860 # number of demand (read+write) accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7543 # number of overall (read+write) accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3116 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 854795 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 626406 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 1491860 # number of overall (read+write) accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000642 # miss rate for ReadReq accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012396 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026057 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.016455 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991099 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991099 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541606 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541606 # miss rate for ReadExReq accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000642 # miss rate for demand accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012396 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229798 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.103596 # miss rate for demand accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000642 # miss rate for overall accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012396 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229798 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.103596 # miss rate for overall accesses
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61050 # average ReadReq miss latency
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 75000 # average ReadReq miss latency
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70759.956587 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74225.410251 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72428.864469 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 119.856649 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 119.856649 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69621.544911 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69621.544911 # average ReadExReq miss latency
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70759.956587 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69937.281666 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 69993.462530 # average overall miss latency
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61050 # average overall miss latency
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 75000 # average overall miss latency
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70759.956587 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69937.281666 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 69993.462530 # average overall miss latency
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 58138 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 58138 # number of writebacks
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9872 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 20475 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2895 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2895 # number of UpgradeReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 134075 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 134075 # number of ReadExReq MSHR misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143947 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 154550 # number of demand (read+write) MSHR misses
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143947 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 154550 # number of overall MSHR misses
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 242750 # number of ReadReq MSHR miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 617083500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 609612750 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1227064000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28955895 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28955895 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7657225866 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7657225866 # number of ReadExReq MSHR miss cycles
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 242750 # number of demand (read+write) MSHR miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 617083500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8266838616 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 8884289866 # number of demand (read+write) MSHR miss cycles
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 242750 # number of overall MSHR miss cycles
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 617083500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8266838616 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 8884289866 # number of overall MSHR miss cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 349507750 # number of ReadReq MSHR uncacheable cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166662160750 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167011668500 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16705919061 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16705919061 # number of WriteReq MSHR uncacheable cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 349507750 # number of overall MSHR uncacheable cycles
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183368079811 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183717587561 # number of overall MSHR uncacheable cycles
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for ReadReq accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012396 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026057 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016455 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991099 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991099 # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541606 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541606 # mshr miss rate for ReadExReq accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for demand accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012396 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229798 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.103596 # mshr miss rate for demand accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000663 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000642 # mshr miss rate for overall accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012396 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229798 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.103596 # mshr miss rate for overall accesses
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average ReadReq mshr miss latency
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58237.400906 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61751.696718 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59929.865690 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.036269 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.036269 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57111.511214 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57111.511214 # average ReadExReq mshr miss latency
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58237.400906 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57429.738834 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57484.890754 # average overall mshr miss latency
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48550 # average overall mshr miss latency
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58237.400906 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57429.738834 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57484.890754 # average overall mshr miss latency
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.replacements 625894 # number of replacements
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.tags.tagsinuse 511.875658 # Cycle average of tags in use
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.total_refs 21786154 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.sampled_refs 626406 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.tags.avg_refs 34.779606 # Average number of references to valid blocks.
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.875658 # Average occupied blocks per requestor
|
2014-05-10 00:58:50 +02:00
|
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id
|
|
|
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id
|
2014-01-24 22:29:33 +01:00
|
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.tags.tag_accesses 90404594 # Number of tag accesses
|
|
|
|
|
system.cpu.dcache.tags.data_accesses 90404594 # Number of data accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 11249411 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 11249411 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 9965441 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 9965441 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 84252 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.SoftPFReq_hits::total 84252 # number of SoftPFReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236461 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_hits::total 236461 # number of LoadLockedReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247668 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.StoreCondReq_hits::total 247668 # number of StoreCondReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 21214852 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 21214852 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 21299104 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 21299104 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 294699 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 294699 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 255299 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 255299 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 100108 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_misses::total 100108 # number of SoftPFReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11208 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_misses::total 11208 # number of LoadLockedReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 549998 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 549998 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 650106 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 650106 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4039018749 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4039018749 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11552022511 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11552022511 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154983250 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 154983250 # number of LoadLockedReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 15591041260 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 15591041260 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 15591041260 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 15591041260 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 11544110 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 11544110 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10220740 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 10220740 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 184360 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SoftPFReq_accesses::total 184360 # number of SoftPFReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247669 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 247669 # number of LoadLockedReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247668 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247668 # number of StoreCondReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 21764850 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 21764850 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 21949210 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 21949210 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025528 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.025528 # miss rate for ReadReq accesses
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024979 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.024979 # miss rate for WriteReq accesses
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.543003 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.543003 # miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045254 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045254 # miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.025270 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.025270 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.029619 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.029619 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13705.573310 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13705.573310 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45248.992401 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 45248.992401 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13827.913098 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13827.913098 # average LoadLockedReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28347.450827 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 28347.450827 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23982.306362 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 23982.306362 # average overall miss latency
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.dcache.writebacks::writebacks 595027 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 595027 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 533 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 533 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4827 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 4827 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 5360 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 5360 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 5360 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 5360 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294166 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 294166 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250472 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 250472 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 73481 # number of SoftPFReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 73481 # number of SoftPFReq MSHR misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11208 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11208 # number of LoadLockedReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 544638 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 544638 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 618119 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 618119 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3444363000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3444363000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10784804239 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10784804239 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1224587250 # number of SoftPFReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1224587250 # number of SoftPFReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132510750 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132510750 # number of LoadLockedReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14229167239 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 14229167239 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15453754489 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 15453754489 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182056011250 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182056011250 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242438939 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242438939 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208298450189 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 208298450189 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025482 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025482 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398573 # mshr miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398573 # mshr miss rate for SoftPFReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045254 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045254 # mshr miss rate for LoadLockedReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025024 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025024 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028161 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.028161 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11708.909255 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11708.909255 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43057.923596 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43057.923596 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16665.359072 # average SoftPFReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16665.359072 # average SoftPFReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11822.872056 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.872056 # average LoadLockedReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26125.917103 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26125.917103 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25001.261066 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25001.261066 # average overall mshr miss latency
|
2013-01-07 19:05:54 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2453657 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2453657 # Transaction distribution
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.trans_dist::Writeback 595027 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2921 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 247551 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 247551 # Transaction distribution
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724466 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748697 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12042 # Packet count per connected master and slave (bytes)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.pkt_count::total 7511457 # Packet count per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54733404 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83586150 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12464 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.pkt_size::total 138362190 # Cumulative packet size per connected master and slave (bytes)
|
|
|
|
|
system.cpu.toL2Bus.snoops 18590 # Total snoops (count)
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::samples 2108398 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::5 2108398 100.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.snoop_fanout::total 2108398 # Request fanout histogram
|
|
|
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3007986500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1294797750 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
2014-09-20 23:18:53 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2533255572 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
2013-11-01 16:56:34 +01:00
|
|
|
system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
2014-09-03 13:42:59 +02:00
|
|
|
system.cpu.toL2Bus.respLayer3.occupancy 18709500 # Layer occupancy (ticks)
|
2013-05-30 18:54:18 +02:00
|
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
2013-08-19 09:52:36 +02:00
|
|
|
system.iocache.tags.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
|
|
|
|
|
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2014-01-24 22:29:33 +01:00
|
|
|
system.iocache.tags.tag_accesses 0 # Number of tag accesses
|
|
|
|
|
system.iocache.tags.data_accesses 0 # Number of data accesses
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
2014-09-20 23:18:53 +02:00
|
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1760318460750 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1760318460750 # number of overall MSHR uncacheable cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
2011-08-19 22:08:09 +02:00
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-08 04:23:11 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
