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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

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Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
sim_seconds 2.624627 # Number of seconds simulated
sim_ticks 2624627401000 # Number of ticks simulated
final_tick 2624627401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
host_inst_rate 463403 # Simulator instruction rate (inst/s)
host_op_rate 589674 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 20203281292 # Simulator tick rate (ticks/s)
host_mem_usage 381220 # Number of bytes of host memory used
host_seconds 129.91 # Real time elapsed on the host
sim_insts 60201162 # Number of instructions simulated
sim_ops 76605148 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 123834568 # Number of bytes read from this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 705824 # Number of bytes read from this memory
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.physmem.bytes_read::cpu.data 9049808 # Number of bytes read from this memory
system.physmem.bytes_read::total 133590712 # Number of bytes read from this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bytes_inst_read::cpu.inst 705824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 705824 # Number of instructions bytes read from this memory
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.physmem.bytes_written::writebacks 3677120 # Number of bytes written to this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.physmem.bytes_written::total 6693192 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15479321 # Number of read requests responded to by this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17231 # Number of read requests responded to by this memory
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.physmem.num_reads::cpu.data 141437 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15637997 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57455 # Number of write requests responded to by this memory
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.physmem.num_writes::total 811473 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47181771 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 73 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.physmem.bw_read::cpu.inst 268924 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3448035 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50898925 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 268924 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 268924 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1401006 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1149143 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2550149 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1401006 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47181771 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.physmem.bw_total::cpu.inst 268924 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4597178 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53449074 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dtb.read_hits 14996727 # DTB read hits
system.cpu.dtb.read_misses 7361 # DTB read misses
system.cpu.dtb.write_hits 11231610 # DTB write hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dtb.write_misses 2211 # DTB write misses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dtb.prefetch_faults 186 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dtb.read_accesses 15004088 # DTB read accesses
system.cpu.dtb.write_accesses 11233821 # DTB write accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dtb.hits 26228337 # DTB hits
system.cpu.dtb.misses 9572 # DTB misses
system.cpu.dtb.accesses 26237909 # DTB accesses
system.cpu.itb.inst_hits 61495131 # ITB inst hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.itb.inst_accesses 61499602 # ITB inst accesses
system.cpu.itb.hits 61495131 # DTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.itb.misses 4471 # DTB misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.itb.accesses 61499602 # DTB accesses
system.cpu.numCycles 5249254802 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.committedInsts 60201162 # Number of instructions committed
system.cpu.committedOps 76605148 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68872531 # Number of integer alu accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.num_func_calls 2139915 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7948068 # number of instructions that are conditional controls
system.cpu.num_int_insts 68872531 # number of integer instructions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_insts 10269 # number of float instructions
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.num_int_register_reads 394780405 # number of times the integer registers were read
system.cpu.num_int_register_writes 74180740 # number of times the integer registers were written
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.num_mem_refs 27395680 # number of memory refs
system.cpu.num_load_insts 15660706 # Number of load instructions
system.cpu.num_store_insts 11734974 # Number of store instructions
system.cpu.num_idle_cycles 4573851223.612257 # Number of idle cycles
system.cpu.num_busy_cycles 675403578.387743 # Number of busy cycles
system.cpu.not_idle_fraction 0.128667 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.871333 # Percentage of idle cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.icache.replacements 855895 # number of replacements
system.cpu.icache.tagsinuse 510.920698 # Cycle average of tags in use
system.cpu.icache.total_refs 60638724 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 856407 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70.805965 # Average number of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.warmup_cycle 19300651000 # Cycle when the warmup percentage was hit.
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.icache.occ_blocks::cpu.inst 510.920698 # Average occupied blocks per requestor
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.occ_percent::cpu.inst 0.997892 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.997892 # Average percentage of cache occupancy
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.icache.ReadReq_hits::cpu.inst 60638724 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60638724 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60638724 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60638724 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60638724 # number of overall hits
system.cpu.icache.overall_hits::total 60638724 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 856407 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 856407 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 856407 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 856407 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 856407 # number of overall misses
system.cpu.icache.overall_misses::total 856407 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11564476500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11564476500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11564476500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11564476500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11564476500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11564476500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61495131 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61495131 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61495131 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61495131 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61495131 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61495131 # number of overall (read+write) accesses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013926 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013926 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013926 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013926 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013926 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013926 # miss rate for overall accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.481989 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13503.481989 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13503.481989 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.481989 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13503.481989 # average overall miss latency
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856407 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 856407 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 856407 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 856407 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 856407 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 856407 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851662500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9851662500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851662500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9851662500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851662500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9851662500 # number of overall MSHR miss cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 353004500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 353004500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 353004500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 353004500 # number of overall MSHR uncacheable cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013926 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.481989 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.481989 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.481989 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.481989 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dcache.replacements 627232 # number of replacements
system.cpu.dcache.tagsinuse 511.878513 # Cycle average of tags in use
system.cpu.dcache.total_refs 23656893 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627744 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.685574 # Average number of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.warmup_cycle 653137000 # Cycle when the warmup percentage was hit.
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dcache.occ_blocks::cpu.data 511.878513 # Average occupied blocks per requestor
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.occ_percent::cpu.data 0.999763 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999763 # Average percentage of cache occupancy
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dcache.ReadReq_hits::cpu.data 13196266 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13196266 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9973744 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9973744 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236294 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236294 # number of LoadLockedReq hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 247690 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247690 # number of StoreCondReq hits
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dcache.demand_hits::cpu.data 23170010 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23170010 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23170010 # number of overall hits
system.cpu.dcache.overall_hits::total 23170010 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368699 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368699 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250547 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250547 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11397 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11397 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 619246 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 619246 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 619246 # number of overall misses
system.cpu.dcache.overall_misses::total 619246 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5200667500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5200667500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8968842000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8968842000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154755000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 154755000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14169509500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14169509500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14169509500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14169509500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13564965 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13564965 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10224291 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10224291 # number of WriteReq accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247691 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247691 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247690 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247690 # number of StoreCondReq accesses(hits+misses)
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dcache.demand_accesses::cpu.data 23789256 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23789256 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23789256 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23789256 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027180 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.027180 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024505 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024505 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046013 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046013 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.026030 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.026030 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026030 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026030 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14105.455941 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14105.455941 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35797.044068 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35797.044068 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13578.573309 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13578.573309 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22881.874893 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22881.874893 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22881.874893 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.dcache.writebacks::writebacks 595999 # number of writebacks
system.cpu.dcache.writebacks::total 595999 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368699 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 368699 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250547 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 250547 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11397 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11397 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 619246 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 619246 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 619246 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 619246 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4463269500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4463269500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8467748000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8467748000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131961000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 131961000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12931017500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12931017500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12931017500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12931017500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182084322500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182084322500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41323476000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41323476000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223407798500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 223407798500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027180 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027180 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046013 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046013 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026030 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026030 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026030 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12105.455941 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12105.455941 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33797.044068 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33797.044068 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11578.573309 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11578.573309 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20881.874893 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20881.874893 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.replacements 61916 # number of replacements
system.cpu.l2cache.tagsinuse 50867.720143 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1683066 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 127296 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 13.221672 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2574019400000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 37864.952088 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885583 # Average occupied blocks per requestor
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001416 # Average occupied blocks per requestor
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.occ_blocks::cpu.inst 6985.681192 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6013.199864 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.577773 # Average percentage of cache occupancy
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.106593 # Average percentage of cache occupancy
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.occ_percent::cpu.data 0.091754 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.776180 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8772 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3549 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 844153 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 370237 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1226711 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 595999 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 595999 # number of Writeback hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 114469 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 114469 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8772 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3549 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 844153 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 484706 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1341180 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8772 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3549 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 844153 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 484706 # number of overall hits
system.cpu.l2cache.overall_hits::total 1341180 # number of overall hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10615 # number of ReadReq misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 20482 # number of ReadReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2873 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2873 # number of UpgradeReq misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 133179 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133179 # number of ReadExReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 10615 # number of demand (read+write) misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_misses::cpu.data 143038 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153661 # number of demand (read+write) misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 10615 # number of overall misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_misses::cpu.data 143038 # number of overall misses
system.cpu.l2cache.overall_misses::total 153661 # number of overall misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 261500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 156000 # number of ReadReq miss cycles
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 552086500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 512764500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1065268500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1041000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1041000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6925666500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6925666500 # number of ReadExReq miss cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 261500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 156000 # number of demand (read+write) miss cycles
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 552086500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7438431000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 7990935000 # number of demand (read+write) miss cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 261500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 156000 # number of overall miss cycles
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 552086500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7438431000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 7990935000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8777 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3552 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 854768 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 380096 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1247193 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 595999 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 595999 # number of Writeback accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2899 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2899 # number of UpgradeReq accesses(hits+misses)
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247648 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247648 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8777 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3552 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 854768 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 627744 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1494841 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8777 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3552 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 854768 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 627744 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1494841 # number of overall (read+write) accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000570 # miss rate for ReadReq accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012419 # miss rate for ReadReq accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025938 # miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 0.016422 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991031 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991031 # miss rate for UpgradeReq accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537775 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.537775 # miss rate for ReadExReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000570 # miss rate for demand accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012419 # miss rate for demand accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.data 0.227860 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.102794 # miss rate for demand accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000570 # miss rate for overall accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012419 # miss rate for overall accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.data 0.227860 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.102794 # miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52300 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52010.032972 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.788011 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52009.984377 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 362.339018 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 362.339018 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52002.691866 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52002.691866 # average ReadExReq miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52003.663910 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52300 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52010.032972 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.180973 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52003.663910 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.writebacks::writebacks 57455 # number of writebacks
system.cpu.l2cache.writebacks::total 57455 # number of writebacks
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10615 # number of ReadReq MSHR misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 20482 # number of ReadReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2873 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2873 # number of UpgradeReq MSHR misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133179 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133179 # number of ReadExReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10615 # number of demand (read+write) MSHR misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 143038 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 153661 # number of demand (read+write) MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10615 # number of overall MSHR misses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 143038 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 153661 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 200000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 120000 # number of ReadReq MSHR miss cycles
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 424634000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 394375000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 819329000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 114934000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 114934000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5327448000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5327448000 # number of ReadExReq MSHR miss cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 200000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 120000 # number of demand (read+write) MSHR miss cycles
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 424634000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5721823000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 6146777000 # number of demand (read+write) MSHR miss cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 200000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 120000 # number of overall MSHR miss cycles
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 424634000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5721823000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 6146777000 # number of overall MSHR miss cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166685236000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166950076000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 31792706500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 31792706500 # number of WriteReq MSHR uncacheable cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198477942500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198742782500 # number of overall MSHR uncacheable cycles
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for ReadReq accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for ReadReq accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025938 # mshr miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016422 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991031 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991031 # mshr miss rate for UpgradeReq accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537775 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537775 # mshr miss rate for ReadExReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for demand accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for demand accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.102794 # mshr miss rate for demand accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000570 # mshr miss rate for overall accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012419 # mshr miss rate for overall accesses
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227860 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102794 # mshr miss rate for overall accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40003.203015 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40001.521452 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40002.392344 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40004.872955 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40004.872955 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40002.162503 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40002.162503 # average ReadExReq mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.203015 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40002.118318 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.193139 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_refs nan # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for DMA port send This patch updates the stats after removing the zero-time send used in the DMA port.
2012-10-23 10:49:48 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1246144703911 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1246144703911 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1246144703911 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink