tests: Update stats no match.
Bootloader I had on my sytem was an older version with a couple of instruction differences.
This commit is contained in:
Ali Saidi
parent
2c2c3a4ce9
commit
ae82551496
42 changed files with 12788 additions and 12780 deletions
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@ -37,13 +37,13 @@ load_offset=2147483648
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machine_type=VExpress_EMM
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mem_mode=timing
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mem_ranges=2147483648:2415919103
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memories=system.realview.vram system.physmem system.realview.nvmem
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memories=system.realview.nvmem system.physmem system.realview.vram
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multi_proc=true
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num_work_ids=16
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panic_on_oops=true
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panic_on_panic=true
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phys_addr_range_64=40
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readfile=/work/gem5.latest/tests/halt.sh
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readfile=/work/gem5.ext/tests/halt.sh
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reset_addr_64=0
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symbolfile=
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work_begin_ckpt_count=0
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@ -1,14 +1,14 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 29 2014 09:18:22
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gem5 started Oct 29 2014 10:01:45
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gem5 compiled Oct 31 2014 10:01:44
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gem5 started Oct 31 2014 11:28:00
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gem5 executing on u200540-lin
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
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0: system.cpu0.isa: ISA system set to: 0x40cab00 0x40cab00
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0: system.cpu1.isa: ISA system set to: 0x40cab00 0x40cab00
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0: system.cpu0.isa: ISA system set to: 0x5a2b680 0x5a2b680
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0: system.cpu1.isa: ISA system set to: 0x5a2b680 0x5a2b680
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info: Using bootloader at address 0x10
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info: Using kernel entry physical address at 0x80008000
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info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
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@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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Exiting @ tick 2843718094000 because m5_exit instruction encountered
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Exiting @ tick 2843665155500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -43,7 +43,7 @@ num_work_ids=16
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panic_on_oops=true
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panic_on_panic=true
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phys_addr_range_64=40
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readfile=/work/gem5.latest/tests/halt.sh
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readfile=/work/gem5.ext/tests/halt.sh
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reset_addr_64=0
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symbolfile=
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work_begin_ckpt_count=0
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@ -1,13 +1,13 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 29 2014 09:18:22
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gem5 started Oct 29 2014 10:01:02
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gem5 compiled Oct 31 2014 10:01:44
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gem5 started Oct 31 2014 11:27:21
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gem5 executing on u200540-lin
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
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0: system.cpu.isa: ISA system set to: 0x4defb00 0x4defb00
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0: system.cpu.isa: ISA system set to: 0x5580680 0x5580680
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info: Using bootloader at address 0x10
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info: Using kernel entry physical address at 0x80008000
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info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
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@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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Exiting @ tick 2852200332000 because m5_exit instruction encountered
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Exiting @ tick 2852222670000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -43,7 +43,7 @@ num_work_ids=16
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panic_on_oops=true
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panic_on_panic=true
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phys_addr_range_64=40
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readfile=/work/gem5.latest/tests/halt.sh
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readfile=/work/gem5.ext/tests/halt.sh
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reset_addr_64=0
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symbolfile=
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work_begin_ckpt_count=0
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@ -32,7 +32,7 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
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warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
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warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
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warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
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warn: 81667444500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
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warn: 81667038500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
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warn: Returning zero for read from miscreg pmcr
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warn: Returning zero for read from miscreg pmcr
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warn: Ignoring write to miscreg pmcntenclr
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@ -1,14 +1,14 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 29 2014 09:18:22
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gem5 started Oct 29 2014 10:12:13
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gem5 compiled Oct 31 2014 10:01:44
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gem5 started Oct 31 2014 11:29:21
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gem5 executing on u200540-lin
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
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0: system.cpu.checker.isa: ISA system set to: 0x59c2b00 0x59c2b00
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0: system.cpu.isa: ISA system set to: 0x59c2b00 0x59c2b00
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0: system.cpu.checker.isa: ISA system set to: 0x4985680 0x4985680
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0: system.cpu.isa: ISA system set to: 0x4985680 0x4985680
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info: Using bootloader at address 0x10
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info: Using kernel entry physical address at 0x80008000
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info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
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@ -44,4 +44,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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Exiting @ tick 2826845674500 because m5_exit instruction encountered
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Exiting @ tick 2826844351500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -37,13 +37,13 @@ load_offset=2147483648
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machine_type=VExpress_EMM
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mem_mode=timing
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mem_ranges=2147483648:2415919103
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memories=system.realview.nvmem system.physmem system.realview.vram
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memories=system.physmem system.realview.vram system.realview.nvmem
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multi_proc=true
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num_work_ids=16
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panic_on_oops=true
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panic_on_panic=true
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phys_addr_range_64=40
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readfile=/work/gem5.latest/tests/halt.sh
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readfile=/work/gem5.ext/tests/halt.sh
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reset_addr_64=0
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symbolfile=
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work_begin_ckpt_count=0
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@ -1,14 +1,14 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 29 2014 09:18:22
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gem5 started Oct 29 2014 10:14:43
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gem5 compiled Oct 31 2014 10:01:44
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gem5 started Oct 31 2014 11:38:41
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gem5 executing on u200540-lin
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
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0: system.cpu0.isa: ISA system set to: 0x5555b00 0x5555b00
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0: system.cpu1.isa: ISA system set to: 0x5555b00 0x5555b00
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0: system.cpu0.isa: ISA system set to: 0x479a680 0x479a680
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0: system.cpu1.isa: ISA system set to: 0x479a680 0x479a680
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info: Using bootloader at address 0x10
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info: Using kernel entry physical address at 0x80008000
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info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
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@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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Exiting @ tick 2824356167500 because m5_exit instruction encountered
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Exiting @ tick 2824340874000 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -43,7 +43,7 @@ num_work_ids=16
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panic_on_oops=true
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panic_on_panic=true
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phys_addr_range_64=40
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readfile=/work/gem5.latest/tests/halt.sh
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readfile=/work/gem5.ext/tests/halt.sh
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reset_addr_64=0
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symbolfile=
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work_begin_ckpt_count=0
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@ -1,13 +1,13 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 29 2014 09:18:22
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gem5 started Oct 29 2014 10:06:55
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gem5 compiled Oct 31 2014 10:01:44
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gem5 started Oct 31 2014 11:28:40
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gem5 executing on u200540-lin
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
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Global frequency set at 1000000000000 ticks per second
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info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
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0: system.cpu.isa: ISA system set to: 0x5387b00 0x5387b00
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0: system.cpu.isa: ISA system set to: 0x443e680 0x443e680
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info: Using bootloader at address 0x10
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info: Using kernel entry physical address at 0x80008000
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info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
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@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
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Exiting @ tick 2826845674500 because m5_exit instruction encountered
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Exiting @ tick 2826844351500 because m5_exit instruction encountered
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File diff suppressed because it is too large
Load diff
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@ -37,13 +37,13 @@ load_offset=2147483648
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machine_type=VExpress_EMM
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mem_mode=atomic
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mem_ranges=2147483648:2415919103
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memories=system.realview.vram system.physmem system.realview.nvmem
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memories=system.physmem system.realview.vram system.realview.nvmem
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multi_proc=true
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num_work_ids=16
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panic_on_oops=true
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panic_on_panic=true
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phys_addr_range_64=40
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readfile=/work/gem5.latest/tests/halt.sh
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readfile=/work/gem5.ext/tests/halt.sh
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reset_addr_64=0
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symbolfile=
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work_begin_ckpt_count=0
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@ -1,11 +1,11 @@
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gem5 Simulator System. http://gem5.org
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gem5 is copyrighted software; use the --copyright option for details.
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gem5 compiled Oct 29 2014 09:18:22
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gem5 started Oct 29 2014 10:14:55
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gem5 compiled Oct 31 2014 10:01:44
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gem5 started Oct 31 2014 11:41:22
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gem5 executing on u200540-lin
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
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command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
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Global frequency set at 1000000000000 ticks per second
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0: system.cpu0.isa: ISA system set to: 0x5395b00 0x5395b00
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0: system.cpu1.isa: ISA system set to: 0x5395b00 0x5395b00
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0: system.cpu2.isa: ISA system set to: 0x5395b00 0x5395b00
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0: system.cpu0.isa: ISA system set to: 0x40eb680 0x40eb680
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0: system.cpu1.isa: ISA system set to: 0x40eb680 0x40eb680
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0: system.cpu2.isa: ISA system set to: 0x40eb680 0x40eb680
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@ -4,13 +4,13 @@ sim_seconds 2.817969 # Nu
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sim_ticks 2817968959500 # Number of ticks simulated
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final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 310224 # Simulator instruction rate (inst/s)
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host_op_rate 376688 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6925358539 # Simulator tick rate (ticks/s)
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host_mem_usage 560716 # Number of bytes of host memory used
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host_seconds 406.91 # Real time elapsed on the host
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sim_insts 126231917 # Number of instructions simulated
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sim_ops 153276568 # Number of ops (including micro ops) simulated
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host_inst_rate 311387 # Simulator instruction rate (inst/s)
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host_op_rate 378101 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 6951332904 # Simulator tick rate (ticks/s)
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host_mem_usage 560824 # Number of bytes of host memory used
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host_seconds 405.39 # Real time elapsed on the host
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sim_insts 126231916 # Number of instructions simulated
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sim_ops 153276567 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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@ -131,7 +131,7 @@ system.physmem.perBankWrBursts::14 3934 # Pe
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system.physmem.perBankWrBursts::15 3898 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
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system.physmem.totGap 2816402816000 # Total gap between requests
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system.physmem.totGap 2816402817000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 1 # Read request sizes (log2)
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@ -298,12 +298,12 @@ system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Wr
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system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads
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system.physmem.totQLat 1185317250 # Total ticks spent queuing
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system.physmem.totMemAccLat 2923442250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totQLat 1185318250 # Total ticks spent queuing
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system.physmem.totMemAccLat 2923443250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 12786.59 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 12786.60 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 31536.59 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 31536.60 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -318,12 +318,12 @@ system.physmem.readRowHits 76736 # Nu
|
|||
system.physmem.writeRowHits 50876 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 17540686.68 # Average gap between requests
|
||||
system.physmem.avgGap 17540686.69 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 2704844342250 # Time in different power states
|
||||
system.physmem.memoryStateTime::IDLE 2704844337250 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 94098160000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 19026363250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 19026368250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ)
|
||||
|
|
@ -335,28 +335,28 @@ system.physmem.writeEnergy::0 224758800 # En
|
|||
system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ)
|
||||
system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem.actBackEnergy::0 70810444215 # Energy for active background per rank (pJ)
|
||||
system.physmem.actBackEnergy::1 69981019830 # Energy for active background per rank (pJ)
|
||||
system.physmem.preBackEnergy::0 1628666804250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.preBackEnergy::1 1629394369500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.totalEnergy::0 1884329287755 # Total energy per rank (pJ)
|
||||
system.physmem.totalEnergy::1 1884181443675 # Total energy per rank (pJ)
|
||||
system.physmem.actBackEnergy::0 70810447635 # Energy for active background per rank (pJ)
|
||||
system.physmem.actBackEnergy::1 69981022395 # Energy for active background per rank (pJ)
|
||||
system.physmem.preBackEnergy::0 1628666801250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.preBackEnergy::1 1629394367250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.totalEnergy::0 1884329288175 # Total energy per rank (pJ)
|
||||
system.physmem.totalEnergy::1 1884181443990 # Total energy per rank (pJ)
|
||||
system.physmem.averagePower::0 668.683537 # Core power per rank (mW)
|
||||
system.physmem.averagePower::1 668.631072 # Core power per rank (mW)
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 74237 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74236 # Transaction distribution
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 74236 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74235 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27571 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27571 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 92896 # Transaction distribution
|
||||
|
|
@ -368,21 +368,21 @@ system.membus.trans_dist::UpgradeResp 4551 # Tr
|
|||
system.membus.trans_dist::ReadExReq 137042 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 137042 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 579193 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 579191 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 652020 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 652018 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 17102703 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 17102699 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 19429167 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 19429163 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 125 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 304844 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
|
|
@ -407,16 +407,16 @@ system.membus.respLayer3.occupancy 23918727 # La
|
|||
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 100821 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65118.790978 # Cycle average of tags in use
|
||||
system.l2c.tags.tagsinuse 65118.790980 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 2895106 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 166061 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 17.433991 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 49797.187016 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::writebacks 49797.187018 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 5291.837037 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 2854.503749 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 2854.503750 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 1121.421966 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 949.242692 # Average occupied blocks per requestor
|
||||
|
|
@ -552,23 +552,23 @@ system.l2c.ReadReq_miss_latency::total 1331208246 # nu
|
|||
system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::cpu2.data 325486 # number of UpgradeReq miss cycles
|
||||
system.l2c.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 994399991 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 994400991 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu2.data 4662408726 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 5656808717 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 5656809717 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 148548750 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 1186690241 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 1186691241 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.dtb.walker 7339250 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.inst 615969000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu2.data 5029395222 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 6988016963 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 6988017963 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 148548750 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 1186690241 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 1186691241 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.dtb.walker 7339250 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.inst 615969000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu2.data 5029395222 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 6988016963 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 6988017963 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4967 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 2546 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 866509 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -675,23 +675,23 @@ system.l2c.ReadReq_avg_miss_latency::total 39244.369152 #
|
|||
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 62.838798 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 305.333959 # average UpgradeReq miss latency
|
||||
system.l2c.UpgradeReq_avg_miss_latency::total 128.260950 # average UpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70464.851970 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70464.922832 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74749.234072 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 40733.682696 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 40733.689897 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.inst 72604.472141 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.data 71114.654581 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.data 71114.714508 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.inst 76309.340932 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu2.data 75122.783343 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 40441.317193 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 40441.322980 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.inst 72604.472141 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.data 71114.654581 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.data 71114.714508 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.inst 76309.340932 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu2.data 75122.783343 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 40441.317193 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 40441.322980 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -752,23 +752,23 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10666566
|
|||
system.l2c.UpgradeReq_mshr_miss_latency::total 14326932 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 813880009 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 813881009 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3892439774 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4706319783 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 4706320783 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.inst 122695750 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 973958759 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 973959759 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.inst 514237000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.data 4200079770 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 5817197029 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 5817198029 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.inst 122695750 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 973958759 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 973959759 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.inst 514237000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.data 4200079770 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 5817197029 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 5817198029 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 943995500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1580248500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 2524244000 # number of ReadReq MSHR uncacheable cycles
|
||||
|
|
@ -819,23 +819,23 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475
|
|||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.903132 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.973994 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.780757 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.793832 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.318631 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 62017.025896 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
|
|
@ -883,8 +883,8 @@ system.cf0.dma_read_txs 1 # Nu
|
|||
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
||||
system.toL2Bus.trans_dist::ReadReq 2443721 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2443718 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadReq 2443720 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2443717 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution
|
||||
|
|
@ -894,16 +894,16 @@ system.toL2Bus.trans_dist::SCUpgradeReq 15 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616609 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616607 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 6218459 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187260 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 6218457 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 213301515 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 213301511 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 51755 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram
|
||||
|
|
@ -1087,7 +1087,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu0.itb.inst_hits 67954631 # ITB inst hits
|
||||
system.cpu0.itb.inst_hits 67954632 # ITB inst hits
|
||||
system.cpu0.itb.inst_misses 2810 # ITB inst misses
|
||||
system.cpu0.itb.read_hits 0 # DTB read hits
|
||||
system.cpu0.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -1104,10 +1104,10 @@ system.cpu0.itb.domain_faults 0 # Nu
|
|||
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu0.itb.inst_accesses 67957441 # ITB inst accesses
|
||||
system.cpu0.itb.hits 67954631 # DTB hits
|
||||
system.cpu0.itb.inst_accesses 67957442 # ITB inst accesses
|
||||
system.cpu0.itb.hits 67954632 # DTB hits
|
||||
system.cpu0.itb.misses 2810 # DTB misses
|
||||
system.cpu0.itb.accesses 67957441 # DTB accesses
|
||||
system.cpu0.itb.accesses 67957442 # DTB accesses
|
||||
system.cpu0.numCycles 82556870 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
|
|
@ -1124,7 +1124,7 @@ system.cpu0.num_int_register_writes 49334420 # nu
|
|||
system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written
|
||||
system.cpu0.num_cc_register_reads 245867738 # number of times the CC registers were read
|
||||
system.cpu0.num_cc_register_writes 29383073 # number of times the CC registers were written
|
||||
system.cpu0.num_cc_register_writes 29383072 # number of times the CC registers were written
|
||||
system.cpu0.num_mem_refs 26220754 # number of memory refs
|
||||
system.cpu0.num_load_insts 14652166 # Number of load instructions
|
||||
system.cpu0.num_store_insts 11568588 # Number of store instructions
|
||||
|
|
@ -1190,16 +1190,16 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 162
|
|||
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 104537930 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 104537930 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 67090157 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 21677955 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 67090158 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu1.inst 21677954 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::cpu2.inst 12120896 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 100889008 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 67090157 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::cpu1.inst 21677955 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 67090158 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::cpu1.inst 21677954 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::cpu2.inst 12120896 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 100889008 # number of demand (read+write) hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 67090157 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::cpu1.inst 21677955 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 67090158 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::cpu1.inst 21677954 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::cpu2.inst 12120896 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 100889008 # number of overall hits
|
||||
system.cpu0.icache.ReadReq_misses::cpu0.inst 866515 # number of ReadReq misses
|
||||
|
|
@ -1223,16 +1223,16 @@ system.cpu0.icache.demand_miss_latency::total 13450125930
|
|||
system.cpu0.icache.overall_miss_latency::cpu1.inst 3389079250 # number of overall miss cycles
|
||||
system.cpu0.icache.overall_miss_latency::cpu2.inst 10061046680 # number of overall miss cycles
|
||||
system.cpu0.icache.overall_miss_latency::total 13450125930 # number of overall miss cycles
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956672 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928102 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956673 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928101 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::cpu2.inst 12853831 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::total 102738605 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.demand_accesses::cpu0.inst 67956672 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::cpu1.inst 21928102 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::cpu0.inst 67956673 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::cpu1.inst 21928101 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::cpu2.inst 12853831 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::total 102738605 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu0.inst 67956672 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu1.inst 21928102 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu0.inst 67956673 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu1.inst 21928101 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu2.inst 12853831 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::total 102738605 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012751 # miss rate for ReadReq accesses
|
||||
|
|
@ -1312,7 +1312,7 @@ system.cpu0.dcache.tags.tagsinuse 511.996800 # Cy
|
|||
system.cpu0.dcache.tags.total_refs 47004235 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 834243 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 56.343577 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.853552 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.631337 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.511911 # Average occupied blocks per requestor
|
||||
|
|
@ -1385,20 +1385,20 @@ system.cpu0.dcache.overall_misses::total 2415821 # nu
|
|||
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905009250 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5267719081 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.ReadReq_miss_latency::total 6172728331 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1312526367 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1312527367 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70730774620 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::total 72043300987 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::total 72043301987 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46439000 # number of LoadLockedReq miss cycles
|
||||
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132211248 # number of LoadLockedReq miss cycles
|
||||
system.cpu0.dcache.LoadLockedReq_miss_latency::total 178650248 # number of LoadLockedReq miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 181001 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_miss_latency::total 181001 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu1.data 2217535617 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu1.data 2217536617 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu2.data 75998493701 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 78216029318 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu1.data 2217535617 # number of overall miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 78216030318 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu1.data 2217536617 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu2.data 75998493701 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 78216029318 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 78216030318 # number of overall miss cycles
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 13978898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu1.data 4464539 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu2.data 8831614 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1457,20 +1457,20 @@ system.cpu0.dcache.overall_miss_rate::total 0.049804 #
|
|||
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15234.307141 # average ReadReq miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16643.399254 # average ReadReq miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10902.316965 # average ReadReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38658.293090 # average WriteReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38658.322544 # average WriteReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46242.623438 # average WriteReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42156.544929 # average WriteReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42156.545514 # average WriteReq miss latency
|
||||
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14140.986602 # average LoadLockedReq miss latency
|
||||
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13638.461729 # average LoadLockedReq miss latency
|
||||
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10253.701888 # average LoadLockedReq miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13923.153846 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12066.733333 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23753.032595 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23753.043306 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41167.876557 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 34378.677509 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19537.930880 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 34378.677948 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19537.939691 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39756.878574 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 32376.583082 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 32376.583496 # average overall miss latency
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 377833 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 25059 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 25141 # number of cycles access was blocked
|
||||
|
|
@ -1518,9 +1518,9 @@ system.cpu0.dcache.overall_mshr_misses::total 437625
|
|||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 783780250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2132755212 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2916535462 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238573617 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238574617 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5438601702 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677175319 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6677176319 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 253255500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 658822506 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 912078006 # number of SoftPFReq MSHR miss cycles
|
||||
|
|
@ -1529,12 +1529,12 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35809251
|
|||
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57420251 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 154999 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 154999 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022353867 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022354867 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7571356914 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 9593710781 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275609367 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 9593711781 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275610367 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8230179420 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 10505788787 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 10505789787 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019366000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1693120500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712486500 # number of ReadReq MSHR uncacheable cycles
|
||||
|
|
@ -1567,9 +1567,9 @@ system.cpu0.dcache.overall_mshr_miss_rate::total 0.009022
|
|||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13217.873586 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13255.489335 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13245.359580 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.137164 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.166618 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45391.659659 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.981212 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.987715 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.063291 # average SoftPFReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15002.220335 # average SoftPFReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14326.207587 # average SoftPFReq mshr miss latency
|
||||
|
|
@ -1578,12 +1578,12 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12420.829344
|
|||
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13561.703118 # average LoadLockedReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.673509 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21687.684233 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26972.070614 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.376888 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.314206 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25654.379562 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20138.323056 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25352.804212 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.372550 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24006.374835 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
|
|
@ -1657,7 +1657,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu1.itb.inst_hits 21928102 # ITB inst hits
|
||||
system.cpu1.itb.inst_hits 21928101 # ITB inst hits
|
||||
system.cpu1.itb.inst_misses 848 # ITB inst misses
|
||||
system.cpu1.itb.read_hits 0 # DTB read hits
|
||||
system.cpu1.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -1674,26 +1674,26 @@ system.cpu1.itb.domain_faults 0 # Nu
|
|||
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu1.itb.inst_accesses 21928950 # ITB inst accesses
|
||||
system.cpu1.itb.hits 21928102 # DTB hits
|
||||
system.cpu1.itb.inst_accesses 21928949 # ITB inst accesses
|
||||
system.cpu1.itb.hits 21928101 # DTB hits
|
||||
system.cpu1.itb.misses 848 # DTB misses
|
||||
system.cpu1.itb.accesses 21928950 # DTB accesses
|
||||
system.cpu1.itb.accesses 21928949 # DTB accesses
|
||||
system.cpu1.numCycles 158012618 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 21219740 # Number of instructions committed
|
||||
system.cpu1.committedOps 25418010 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 22602371 # Number of integer alu accesses
|
||||
system.cpu1.committedInsts 21219739 # Number of instructions committed
|
||||
system.cpu1.committedOps 25418009 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 22602370 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 1626 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 2405283 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 2700826 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 22602371 # number of integer instructions
|
||||
system.cpu1.num_int_insts 22602370 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 1626 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 41665137 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 15857681 # number of times the integer registers were written
|
||||
system.cpu1.num_int_register_reads 41665136 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 15857680 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 1178 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written
|
||||
system.cpu1.num_cc_register_reads 92378686 # number of times the CC registers were read
|
||||
system.cpu1.num_cc_register_reads 92378683 # number of times the CC registers were read
|
||||
system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written
|
||||
system.cpu1.num_mem_refs 8126078 # number of memory refs
|
||||
system.cpu1.num_load_insts 4682102 # Number of load instructions
|
||||
|
|
@ -1704,7 +1704,7 @@ system.cpu1.not_idle_fraction 0.041047 # Pe
|
|||
system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles
|
||||
system.cpu1.Branches 5257577 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 17988056 68.83% 68.83% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 17988055 68.83% 68.83% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction
|
||||
|
|
@ -1737,7 +1737,7 @@ system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Cl
|
|||
system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 26134332 # Class of executed instruction
|
||||
system.cpu1.op_class::total 26134331 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu2.branchPred.lookups 17411527 # Number of BP lookups
|
||||
|
|
|
|||
|
|
@ -37,13 +37,13 @@ load_offset=2147483648
|
|||
machine_type=VExpress_EMM
|
||||
mem_mode=timing
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.realview.vram system.physmem system.realview.nvmem
|
||||
memories=system.realview.nvmem system.physmem system.realview.vram
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5.latest/tests/halt.sh
|
||||
readfile=/work/gem5.ext/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
|||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
|
||||
warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1]
|
||||
warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[5]
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[1]
|
||||
|
|
@ -43,7 +44,7 @@ warn: Ignoring write to miscreg pmcr
|
|||
warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[6]
|
||||
warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
|
||||
warn: CP14 unimplemented crn[4], opc1[5], crm[12], opc2[1]
|
||||
warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[1]
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
@ -57,7 +58,3 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 29 2014 09:18:22
|
||||
gem5 started Oct 29 2014 10:21:54
|
||||
gem5 compiled Oct 31 2014 10:01:44
|
||||
gem5 started Oct 31 2014 11:48:14
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu0.isa: ISA system set to: 0x422cb00 0x422cb00
|
||||
0: system.cpu1.isa: ISA system set to: 0x422cb00 0x422cb00
|
||||
0: system.cpu0.isa: ISA system set to: 0x4f45680 0x4f45680
|
||||
0: system.cpu1.isa: ISA system set to: 0x4f45680 0x4f45680
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -37,13 +37,13 @@ load_offset=2147483648
|
|||
machine_type=VExpress_EMM
|
||||
mem_mode=timing
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
memories=system.realview.nvmem system.physmem system.realview.vram
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5.latest/tests/halt.sh
|
||||
readfile=/work/gem5.ext/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 29 2014 09:18:22
|
||||
gem5 started Oct 29 2014 10:26:21
|
||||
gem5 compiled Oct 31 2014 10:01:44
|
||||
gem5 started Oct 31 2014 11:48:18
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu0.isa: ISA system set to: 0x3fa4b00 0x3fa4b00
|
||||
0: system.cpu1.isa: ISA system set to: 0x3fa4b00 0x3fa4b00
|
||||
0: system.cpu0.isa: ISA system set to: 0x4989680 0x4989680
|
||||
0: system.cpu1.isa: ISA system set to: 0x4989680 0x4989680
|
||||
|
|
|
|||
|
|
@ -4,15 +4,27 @@ sim_seconds 2.904683 # Nu
|
|||
sim_ticks 2904682547500 # Number of ticks simulated
|
||||
final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 708228 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 853902 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 18288406087 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 555560 # Number of bytes of host memory used
|
||||
host_seconds 158.83 # Real time elapsed on the host
|
||||
sim_insts 112485368 # Number of instructions simulated
|
||||
sim_ops 135622164 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 680974 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 821042 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 17584626781 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 555668 # Number of bytes of host memory used
|
||||
host_seconds 165.18 # Real time elapsed on the host
|
||||
sim_insts 112485367 # Number of instructions simulated
|
||||
sim_ops 135622163 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
|
||||
|
|
@ -117,7 +129,7 @@ system.physmem.perBankWrBursts::14 7309 # Pe
|
|||
system.physmem.perBankWrBursts::15 7126 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 2904682126000 # Total gap between requests
|
||||
system.physmem.totGap 2904682181000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
|
||||
|
|
@ -228,20 +240,20 @@ system.physmem.wrQLenPdf::60 18 # Wh
|
|||
system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 58497 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 315.331590 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 184.690243 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 335.870742 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 21229 36.29% 36.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 14764 25.24% 61.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5739 9.81% 71.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3179 5.43% 76.77% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2288 3.91% 80.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1563 2.67% 83.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1023 1.75% 85.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1098 1.88% 86.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7614 13.02% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 58497 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::samples 58500 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 315.315419 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 184.678002 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 335.865343 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 21233 36.30% 36.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 14762 25.23% 61.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5740 9.81% 71.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3179 5.43% 76.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2292 3.92% 80.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1563 2.67% 83.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1019 1.74% 85.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1097 1.88% 86.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7615 13.02% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 58500 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5866 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 28.752472 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 562.127013 # Reads before turning the bus around for writes
|
||||
|
|
@ -283,12 +295,12 @@ system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Wr
|
|||
system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1486718500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 4649281000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 1487003250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 4649565750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 8814.36 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 8816.05 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27564.36 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27566.05 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -299,49 +311,37 @@ system.physmem.busUtilRead 0.03 # Da
|
|||
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 139009 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 139006 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 90713 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.41 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9939406.19 # Average gap between requests
|
||||
system.physmem.avgGap 9939406.38 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 2756104323000 # Time in different power states
|
||||
system.physmem.memoryStateTime::IDLE 2756104234500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 96993520000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 51578552000 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 51578640500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem.actEnergy::0 224721000 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.actEnergy::1 217516320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.preEnergy::0 122615625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.preEnergy::1 118684500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.actEnergy::0 224736120 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.actEnergy::1 217523880 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.preEnergy::0 122623875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.preEnergy::1 118688625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.readEnergy::0 697031400 # Energy for read commands per rank (pJ)
|
||||
system.physmem.readEnergy::1 618579000 # Energy for read commands per rank (pJ)
|
||||
system.physmem.writeEnergy::0 388618560 # Energy for write commands per rank (pJ)
|
||||
system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ)
|
||||
system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem.actBackEnergy::0 86947680015 # Energy for active background per rank (pJ)
|
||||
system.physmem.actBackEnergy::1 86005039095 # Energy for active background per rank (pJ)
|
||||
system.physmem.preBackEnergy::0 1666535934000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.preBackEnergy::1 1667362812000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.totalEnergy::0 1944635925720 # Total energy per rank (pJ)
|
||||
system.physmem.totalEnergy::1 1944428021475 # Total energy per rank (pJ)
|
||||
system.physmem.averagePower::0 669.484538 # Core power per rank (mW)
|
||||
system.physmem.averagePower::1 669.412962 # Core power per rank (mW)
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 70577 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 70577 # Transaction distribution
|
||||
system.physmem.actBackEnergy::0 86947691130 # Energy for active background per rank (pJ)
|
||||
system.physmem.actBackEnergy::1 86007166335 # Energy for active background per rank (pJ)
|
||||
system.physmem.preBackEnergy::0 1666535924250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.preBackEnergy::1 1667360946000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.totalEnergy::0 1944635950455 # Total energy per rank (pJ)
|
||||
system.physmem.totalEnergy::1 1944428294400 # Total energy per rank (pJ)
|
||||
system.physmem.averagePower::0 669.484547 # Core power per rank (mW)
|
||||
system.physmem.averagePower::1 669.413056 # Core power per rank (mW)
|
||||
system.membus.trans_dist::ReadReq 70576 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 70576 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27613 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27613 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 82818 # Transaction distribution
|
||||
|
|
@ -353,21 +353,21 @@ system.membus.trans_dist::UpgradeResp 4512 # Tr
|
|||
system.membus.trans_dist::ReadExReq 129059 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 129059 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438206 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 545872 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 545870 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 618569 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 618567 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 15710305 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 18029601 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 219 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 283020 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
|
|
@ -382,13 +382,13 @@ system.membus.snoop_fanout::max_value 1 # Re
|
|||
system.membus.snoop_fanout::total 283020 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer5.occupancy 1336695500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 1640330738 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.occupancy 1640331988 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks)
|
||||
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -508,25 +508,25 @@ system.l2c.UpgradeReq_miss_latency::cpu1.data 231490
|
|||
system.l2c.UpgradeReq_miss_latency::total 463980 # number of UpgradeReq miss cycles
|
||||
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 45998 # number of SCUpgradeReq miss cycles
|
||||
system.l2c.SCUpgradeReq_miss_latency::total 45998 # number of SCUpgradeReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu0.data 4342067899 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu0.data 4342132899 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::cpu1.data 4712323819 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 9054391718 # number of ReadExReq miss cycles
|
||||
system.l2c.ReadExReq_miss_latency::total 9054456718 # number of ReadExReq miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.dtb.walker 74500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.inst 591637750 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.data 4732980399 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu0.data 4733045399 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.dtb.walker 566500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.inst 717694500 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::cpu1.data 5241329319 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 11284357968 # number of demand (read+write) miss cycles
|
||||
system.l2c.demand_miss_latency::total 11284422968 # number of demand (read+write) miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.dtb.walker 74500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.inst 591637750 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.data 4732980399 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu0.data 4733045399 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.dtb.walker 566500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.inst 717694500 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::cpu1.data 5241329319 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 11284357968 # number of overall miss cycles
|
||||
system.l2c.overall_miss_latency::total 11284422968 # number of overall miss cycles
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 6207 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 3384 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 844619 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -609,25 +609,25 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 161.767994
|
|||
system.l2c.UpgradeReq_avg_miss_latency::total 170.080645 # average UpgradeReq miss latency
|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 22999 # average SCUpgradeReq miss latency
|
||||
system.l2c.SCUpgradeReq_avg_miss_latency::total 22999 # average SCUpgradeReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69654.745961 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69655.788681 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68789.031575 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 69201.486675 # average ReadExReq miss latency
|
||||
system.l2c.ReadExReq_avg_miss_latency::total 69201.983461 # average ReadExReq miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu0.inst 72584.682861 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu0.data 70159.804314 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu0.data 70160.767848 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.inst 72729.479124 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::cpu1.data 69400.438529 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 70084.391551 # average overall miss latency
|
||||
system.l2c.demand_avg_miss_latency::total 70084.795250 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu0.inst 72584.682861 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu0.data 70159.804314 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu0.data 70160.767848 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80928.571429 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.inst 72729.479124 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::cpu1.data 69400.438529 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 70084.391551 # average overall miss latency
|
||||
system.l2c.overall_avg_miss_latency::total 70084.795250 # average overall miss latency
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -683,36 +683,36 @@ system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14335431
|
|||
system.l2c.UpgradeReq_mshr_miss_latency::total 27310228 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20002 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3544164101 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3544229101 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3834753681 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 7378917782 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 7378982782 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.inst 488618750 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.data 3871171601 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.data 3871236601 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 479000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.inst 592932000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 4276118181 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 9229444532 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 9229509532 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 62500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.inst 488618750 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.data 3871171601 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.data 3871236601 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 479000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.inst 592932000 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 4276118181 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 9229444532 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 474790500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2494979250 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 9229509532 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 474215000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2495734500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2890261000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 5860030750 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_uncacheable_latency::total 5860210500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1979887500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2118425500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.WriteReq_mshr_uncacheable_latency::total 4098313000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 474790500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4474866750 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 474215000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4475622000 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5008686500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 9958343750 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.overall_mshr_uncacheable_latency::total 9958523500 # number of overall MSHR uncacheable cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -758,25 +758,25 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488
|
|||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.080645 # average UpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56854.903204 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56855.945923 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55978.536742 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56396.066844 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56396.563631 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57384.696131 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57385.659665 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 57321.826037 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 57322.229736 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57384.696131 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57385.659665 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 57321.826037 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 57322.229736 # average overall mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
||||
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
||||
|
|
@ -826,8 +826,8 @@ system.cf0.dma_read_txs 1 # Nu
|
|||
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
||||
system.toL2Bus.trans_dist::ReadReq 2301461 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2301446 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadReq 2301460 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2301445 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 686956 # Transaction distribution
|
||||
|
|
@ -837,16 +837,16 @@ system.toL2Bus.trans_dist::SCUpgradeReq 2 # Tr
|
|||
system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 295910 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 295910 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415394 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457263 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 5925128 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750524 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 5925126 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868197 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46148 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 205689601 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 205689597 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 53732 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 3283133 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram
|
||||
|
|
@ -863,13 +863,13 @@ system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 3283133 # Request fanout histogram
|
||||
system.toL2Bus.reqLayer0.occupancy 4418861248 # Layer occupancy (ticks)
|
||||
system.toL2Bus.reqLayer0.occupancy 4418860748 # Layer occupancy (ticks)
|
||||
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks)
|
||||
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.toL2Bus.respLayer0.occupancy 7658492249 # Layer occupancy (ticks)
|
||||
system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks)
|
||||
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.toL2Bus.respLayer1.occupancy 3782893262 # Layer occupancy (ticks)
|
||||
system.toL2Bus.respLayer1.occupancy 3782893012 # Layer occupancy (ticks)
|
||||
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks)
|
||||
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -1064,20 +1064,20 @@ system.cpu0.itb.accesses 58036248 # DT
|
|||
system.cpu0.numCycles 2905319694 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 56513152 # Number of instructions committed
|
||||
system.cpu0.committedOps 68067865 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 60172056 # Number of integer alu accesses
|
||||
system.cpu0.committedInsts 56513151 # Number of instructions committed
|
||||
system.cpu0.committedOps 68067864 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 60172055 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 4924591 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 7649382 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 60172056 # number of integer instructions
|
||||
system.cpu0.num_int_insts 60172055 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 6287 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 109432778 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 41532373 # number of times the integer registers were written
|
||||
system.cpu0.num_int_register_reads 109432777 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 41532372 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written
|
||||
system.cpu0.num_cc_register_reads 245794862 # number of times the CC registers were read
|
||||
system.cpu0.num_cc_register_writes 26123490 # number of times the CC registers were written
|
||||
system.cpu0.num_cc_register_reads 245794859 # number of times the CC registers were read
|
||||
system.cpu0.num_cc_register_writes 26123489 # number of times the CC registers were written
|
||||
system.cpu0.num_mem_refs 22763355 # number of memory refs
|
||||
system.cpu0.num_load_insts 12450624 # Number of load instructions
|
||||
system.cpu0.num_store_insts 10312731 # Number of store instructions
|
||||
|
|
@ -1087,7 +1087,7 @@ system.cpu0.not_idle_fraction 0.075576 # Pe
|
|||
system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles
|
||||
system.cpu0.Branches 12983474 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 46789640 67.21% 67.21% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 46789639 67.21% 67.21% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 58624 0.08% 67.30% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction
|
||||
|
|
@ -1120,7 +1120,7 @@ system.cpu0.op_class::MemRead 12450624 17.88% 85.19% # Cl
|
|||
system.cpu0.op_class::MemWrite 10312731 14.81% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 69618096 # Class of executed instruction
|
||||
system.cpu0.op_class::total 69618095 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed
|
||||
system.cpu0.icache.tags.replacements 1698167 # number of replacements
|
||||
|
|
@ -1222,10 +1222,10 @@ system.cpu0.icache.demand_mshr_miss_latency::total 19874171251
|
|||
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9830070251 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10044101000 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.overall_mshr_miss_latency::total 19874171251 # number of overall MSHR miss cycles
|
||||
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 598490500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 598490500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1255,7 +1255,7 @@ system.cpu0.dcache.tags.total_refs 43241496 # To
|
|||
system.cpu0.dcache.tags.sampled_refs 823497 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 52.509597 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068899 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068900 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781856 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625135 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374574 # Average percentage of cache occupancy
|
||||
|
|
@ -1312,20 +1312,20 @@ system.cpu0.dcache.overall_misses::total 820469 # nu
|
|||
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2867929500 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3066278250 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.ReadReq_miss_latency::total 5934207750 # number of ReadReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744425374 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744490374 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6031803093 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::total 11776228467 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.WriteReq_miss_latency::total 11776293467 # number of WriteReq miss cycles
|
||||
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 135157750 # number of LoadLockedReq miss cycles
|
||||
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 145057500 # number of LoadLockedReq miss cycles
|
||||
system.cpu0.dcache.LoadLockedReq_miss_latency::total 280215250 # number of LoadLockedReq miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52002 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_miss_latency::total 52002 # number of StoreCondReq miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu0.data 8612354874 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu0.data 8612419874 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::cpu1.data 9098081343 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 17710436217 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu0.data 8612354874 # number of overall miss cycles
|
||||
system.cpu0.dcache.demand_miss_latency::total 17710501217 # number of demand (read+write) miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu0.data 8612419874 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::cpu1.data 9098081343 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 17710436217 # number of overall miss cycles
|
||||
system.cpu0.dcache.overall_miss_latency::total 17710501217 # number of overall miss cycles
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11778885 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu1.data 11739375 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 23518260 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -1370,20 +1370,20 @@ system.cpu0.dcache.overall_miss_rate::total 0.019012 #
|
|||
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14536.618683 # average ReadReq miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14919.319642 # average ReadReq miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.880595 # average ReadReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38246.448777 # average WriteReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38246.881547 # average WriteReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40627.504567 # average WriteReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.084500 # average WriteReq miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.302139 # average WriteReq miss latency
|
||||
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12146.827537 # average LoadLockedReq miss latency
|
||||
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12456.633748 # average LoadLockedReq miss latency
|
||||
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12305.254260 # average LoadLockedReq miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26001 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26001 # average StoreCondReq miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24784.824882 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24785.011940 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25701.520786 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 25247.423240 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21211.913043 # average overall miss latency
|
||||
system.cpu0.dcache.demand_avg_miss_latency::total 25247.515901 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21212.073135 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21951.968959 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 21585.746953 # average overall miss latency
|
||||
system.cpu0.dcache.overall_avg_miss_latency::total 21585.826176 # average overall miss latency
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
|
||||
|
|
@ -1429,9 +1429,9 @@ system.cpu0.dcache.overall_mshr_misses::total 817721
|
|||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467791750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647821500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115613250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416554578 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416619578 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704545869 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121100447 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121165447 # number of WriteReq MSHR miss cycles
|
||||
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles
|
||||
|
|
@ -1440,21 +1440,21 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750
|
|||
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884346328 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884411328 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352367369 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 16236713697 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580384578 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.demand_mshr_miss_latency::total 16236778697 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580449578 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094611369 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 17674995947 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2687639750 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_miss_latency::total 17675060947 # number of overall MSHR miss cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688394500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5790667250 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791422000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4852954750 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4853709500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220469750 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221224500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016725 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1478,9 +1478,9 @@ system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948
|
|||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.670914 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.865085 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12719.109819 # average ReadReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36063.481328 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36063.914098 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.247538 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37236.533886 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37236.751524 # average WriteReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency
|
||||
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency
|
||||
|
|
@ -1489,12 +1489,12 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746
|
|||
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.501570 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.688783 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.807486 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.843160 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.664959 # average overall mshr miss latency
|
||||
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.935903 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.825517 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22027.037543 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.946843 # average overall mshr miss latency
|
||||
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21615.026332 # average overall mshr miss latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
|
|
|
|||
|
|
@ -37,13 +37,13 @@ load_offset=2147483648
|
|||
machine_type=VExpress_EMM
|
||||
mem_mode=atomic
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.realview.nvmem system.physmem system.realview.vram
|
||||
memories=system.physmem system.realview.vram system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5.latest/tests/halt.sh
|
||||
readfile=/work/gem5.ext/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 29 2014 15:46:15
|
||||
gem5 started Oct 29 2014 15:58:03
|
||||
gem5 compiled Oct 31 2014 10:01:44
|
||||
gem5 started Oct 31 2014 11:25:21
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
0: system.cpu0.isa: ISA system set to: 0x530db00 0x530db00
|
||||
0: system.cpu1.isa: ISA system set to: 0x530db00 0x530db00
|
||||
0: system.cpu0.isa: ISA system set to: 0x53ff680 0x53ff680
|
||||
0: system.cpu1.isa: ISA system set to: 0x53ff680 0x53ff680
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
|
|
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
|||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2802882496500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2802882713500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -43,7 +43,7 @@ num_work_ids=16
|
|||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5.latest/tests/halt.sh
|
||||
readfile=/work/gem5.ext/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 29 2014 15:46:15
|
||||
gem5 started Oct 29 2014 15:56:38
|
||||
gem5 compiled Oct 31 2014 10:01:44
|
||||
gem5 started Oct 31 2014 11:25:21
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
0: system.cpu.isa: ISA system set to: 0x55e4b00 0x55e4b00
|
||||
0: system.cpu.isa: ISA system set to: 0x5299680 0x5299680
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
|
|
@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
|||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2783853461500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2783854177000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.783853 # Number of seconds simulated
|
||||
sim_ticks 2783853461500 # Number of ticks simulated
|
||||
final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.783854 # Number of seconds simulated
|
||||
sim_ticks 2783854177000 # Number of ticks simulated
|
||||
final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1369296 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1666897 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26699855189 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 553552 # Number of bytes of host memory used
|
||||
host_seconds 104.26 # Real time elapsed on the host
|
||||
sim_insts 142769281 # Number of instructions simulated
|
||||
sim_ops 173798567 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1378246 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26874016957 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 553624 # Number of bytes of host memory used
|
||||
host_seconds 103.59 # Real time elapsed on the host
|
||||
sim_insts 142771179 # Number of instructions simulated
|
||||
sim_ops 173800939 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||
|
|
@ -21,56 +21,56 @@ system.physmem.bytes_read::cpu.data 10345892 # Nu
|
|||
system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8857332 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142503 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 74236 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74236 # Transaction distribution
|
||||
system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 74235 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74235 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27560 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27560 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 101898 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 101899 # Transaction distribution
|
||||
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
||||
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
|
|
@ -79,33 +79,33 @@ system.membus.trans_dist::UpgradeResp 4509 # Tr
|
|||
system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 322857 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 322858 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 322857 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 322858 # Request fanout histogram
|
||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
@ -222,9 +222,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT
|
|||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 31525428 # DTB read hits
|
||||
system.cpu.dtb.read_hits 31525864 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8580 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23123837 # DTB write hits
|
||||
system.cpu.dtb.write_hits 23124034 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1448 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
|
|
@ -235,12 +235,12 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 31534008 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125285 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 31534444 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125482 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 54649265 # DTB hits
|
||||
system.cpu.dtb.hits 54649898 # DTB hits
|
||||
system.cpu.dtb.misses 10028 # DTB misses
|
||||
system.cpu.dtb.accesses 54659293 # DTB accesses
|
||||
system.cpu.dtb.accesses 54659926 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
|
|
@ -262,7 +262,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 147035651 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 147037671 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -279,38 +279,38 @@ system.cpu.itb.domain_faults 0 # Nu
|
|||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 147040413 # ITB inst accesses
|
||||
system.cpu.itb.hits 147035651 # DTB hits
|
||||
system.cpu.itb.inst_accesses 147042433 # ITB inst accesses
|
||||
system.cpu.itb.hits 147037671 # DTB hits
|
||||
system.cpu.itb.misses 4762 # DTB misses
|
||||
system.cpu.itb.accesses 147040413 # DTB accesses
|
||||
system.cpu.numCycles 5567710004 # number of cpu cycles simulated
|
||||
system.cpu.itb.accesses 147042433 # DTB accesses
|
||||
system.cpu.numCycles 5567711435 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 142769281 # Number of instructions committed
|
||||
system.cpu.committedOps 173798567 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153158502 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 142771179 # Number of instructions committed
|
||||
system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 16873305 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730015 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153158502 # number of integer instructions
|
||||
system.cpu.num_func_calls 16873782 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153160639 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11484 # number of float instructions
|
||||
system.cpu.num_int_register_reads 285052059 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107176408 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 530840054 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62363143 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55937812 # number of memory refs
|
||||
system.cpu.num_load_insts 31855061 # Number of load instructions
|
||||
system.cpu.num_store_insts 24082751 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389631214.604722 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178078789.395278 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.031984 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.968016 # Percentage of idle cycles
|
||||
system.cpu.Branches 36396067 # Number of branches fetched
|
||||
system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55938446 # number of memory refs
|
||||
system.cpu.num_load_insts 31855497 # Number of load instructions
|
||||
system.cpu.num_store_insts 24082949 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
||||
system.cpu.Branches 36396779 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121149664 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116881 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
||||
|
|
@ -338,19 +338,19 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855061 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24082751 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177215263 # Class of executed instruction
|
||||
system.cpu.op_class::total 177217756 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 1698994 # number of replacements
|
||||
system.cpu.icache.tags.replacements 1699006 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145339246 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
|
||||
|
|
@ -360,26 +360,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 148738270 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148738270 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145339246 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145339246 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145339246 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145339246 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145339246 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145339246 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699512 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699512 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699512 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699512 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699512 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699512 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147038758 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147038758 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147038758 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145341254 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699524 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
|
||||
|
|
@ -396,16 +396,16 @@ system.cpu.icache.fast_writes 0 # nu
|
|||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 110027 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.315266 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2727659 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 15.559239 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.653997 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309992 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
|
|
@ -422,29 +422,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 26202376 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 26202376 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681137 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 505491 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2197846 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 682038 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 682038 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151041 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151041 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681137 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2348887 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681137 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2348887 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses
|
||||
|
|
@ -468,47 +468,47 @@ system.cpu.l2cache.overall_misses::cpu.data 163398 #
|
|||
system.cpu.l2cache.overall_misses::total 181765 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699495 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 521025 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2231747 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 682038 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 682038 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298905 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699495 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530652 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699495 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530652 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029814 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494686 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
|
|
@ -518,15 +518,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101898 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101899 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu.dcache.tags.replacements 819392 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53783051 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.595966 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
|
|
@ -535,56 +535,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 219231854 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219231854 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128262 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128262 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339512 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395063 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395063 # number of SoftPFReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52467774 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52467774 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52862837 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52862837 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396291 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396291 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301661 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301661 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116123 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116123 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52863480 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697952 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697952 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814075 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30524553 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641173 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814065 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53165726 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53676912 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53676912 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012983 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227164 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227164 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
||||
|
|
@ -601,29 +601,29 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 682038 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682038 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682036 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 36632 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
|
||||
|
|
@ -641,12 +641,12 @@ system.cpu.toL2Bus.snoop_fanout::min_value 5 #
|
|||
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram
|
||||
system.iocache.tags.replacements 36430 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor
|
||||
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
|
|
|
|||
|
|
@ -37,13 +37,13 @@ load_offset=2147483648
|
|||
machine_type=VExpress_EMM
|
||||
mem_mode=timing
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.realview.nvmem system.physmem system.realview.vram
|
||||
memories=system.physmem system.realview.vram system.realview.nvmem
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5.latest/tests/halt.sh
|
||||
readfile=/work/gem5.ext/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 29 2014 15:46:15
|
||||
gem5 started Oct 29 2014 15:58:33
|
||||
gem5 compiled Oct 31 2014 10:01:44
|
||||
gem5 started Oct 31 2014 11:25:21
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
0: system.cpu0.isa: ISA system set to: 0x5550b00 0x5550b00
|
||||
0: system.cpu1.isa: ISA system set to: 0x5550b00 0x5550b00
|
||||
0: system.cpu0.isa: ISA system set to: 0x4f96680 0x4f96680
|
||||
0: system.cpu1.isa: ISA system set to: 0x4f96680 0x4f96680
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
|
|
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
|||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2866929256000 because m5_exit instruction encountered
|
||||
Exiting @ tick 2866923142000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -43,7 +43,7 @@ num_work_ids=16
|
|||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5.latest/tests/halt.sh
|
||||
readfile=/work/gem5.ext/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 29 2014 15:46:15
|
||||
gem5 started Oct 29 2014 15:58:15
|
||||
gem5 compiled Oct 31 2014 10:01:44
|
||||
gem5 started Oct 31 2014 11:25:21
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
0: system.cpu.isa: ISA system set to: 0x56b5b00 0x56b5b00
|
||||
0: system.cpu.isa: ISA system set to: 0x44d4680 0x44d4680
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@ sim_seconds 2.902619 # Nu
|
|||
sim_ticks 2902619131000 # Number of ticks simulated
|
||||
final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 744858 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 898074 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 19216925045 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 553548 # Number of bytes of host memory used
|
||||
host_seconds 151.05 # Real time elapsed on the host
|
||||
sim_insts 112506996 # Number of instructions simulated
|
||||
sim_ops 135649573 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 756630 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 912268 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 19520630002 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 553652 # Number of bytes of host memory used
|
||||
host_seconds 148.70 # Real time elapsed on the host
|
||||
sim_insts 112506995 # Number of instructions simulated
|
||||
sim_ops 135649572 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||
|
|
@ -100,7 +100,7 @@ system.physmem.perBankWrBursts::14 7284 # Pe
|
|||
system.physmem.perBankWrBursts::15 7101 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 2902618699500 # Total gap between requests
|
||||
system.physmem.totGap 2902618754500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
|
||||
|
|
@ -211,20 +211,20 @@ system.physmem.wrQLenPdf::60 13 # Wh
|
|||
system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 183.647731 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 334.576547 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 21465 36.66% 36.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 14645 25.01% 61.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5517 9.42% 71.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2275 3.89% 80.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1002 1.71% 85.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1065 1.82% 87.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7538 12.87% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes
|
||||
|
|
@ -268,12 +268,12 @@ system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Wr
|
|||
system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1491787750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 4643569000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 1492072500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 8874.67 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27624.67 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -284,49 +284,49 @@ system.physmem.busUtilRead 0.03 # Da
|
|||
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 138438 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 138435 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 90000 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9972509.98 # Average gap between requests
|
||||
system.physmem.avgGap 9972510.17 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 2755208941000 # Time in different power states
|
||||
system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 96924620000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 50485479500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem.actEnergy::0 226724400 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.actEnergy::1 215943840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.preEnergy::0 123708750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.preEnergy::1 117826500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ)
|
||||
system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ)
|
||||
system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ)
|
||||
system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ)
|
||||
system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ)
|
||||
system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem.actBackEnergy::0 86731413750 # Energy for active background per rank (pJ)
|
||||
system.physmem.actBackEnergy::1 85564066005 # Energy for active background per rank (pJ)
|
||||
system.physmem.preBackEnergy::0 1665487627500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.preBackEnergy::1 1666511616750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.totalEnergy::0 1943242616760 # Total energy per rank (pJ)
|
||||
system.physmem.totalEnergy::1 1942987016415 # Total energy per rank (pJ)
|
||||
system.physmem.averagePower::0 669.480430 # Core power per rank (mW)
|
||||
system.physmem.averagePower::1 669.392372 # Core power per rank (mW)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 70650 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 70650 # Transaction distribution
|
||||
system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ)
|
||||
system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ)
|
||||
system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ)
|
||||
system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ)
|
||||
system.physmem.averagePower::0 669.480439 # Core power per rank (mW)
|
||||
system.physmem.averagePower::1 669.392466 # Core power per rank (mW)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
||||
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
||||
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 70649 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 70649 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27618 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27618 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 82180 # Transaction distribution
|
||||
|
|
@ -338,21 +338,21 @@ system.membus.trans_dist::UpgradeResp 4505 # Tr
|
|||
system.membus.trans_dist::ReadExReq 128451 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 128451 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544160 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 616857 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635013 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17954309 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 219 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 281834 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
|
|
@ -367,13 +367,13 @@ system.membus.snoop_fanout::max_value 1 # Re
|
|||
system.membus.snoop_fanout::total 281834 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer2.occupancy 1594856745 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks)
|
||||
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks)
|
||||
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -604,20 +604,20 @@ system.cpu.itb.accesses 115610659 # DT
|
|||
system.cpu.numCycles 5805238262 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 112506996 # Number of instructions committed
|
||||
system.cpu.committedOps 135649573 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 119948924 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 112506995 # Number of instructions committed
|
||||
system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 9898964 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 119948924 # number of integer instructions
|
||||
system.cpu.num_int_insts 119948923 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11161 # number of float instructions
|
||||
system.cpu.num_int_register_reads 218165442 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 82686636 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 489970612 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 51914328 # number of times the CC registers were written
|
||||
system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 45428231 # number of memory refs
|
||||
system.cpu.num_load_insts 24855392 # Number of load instructions
|
||||
system.cpu.num_store_insts 20572839 # Number of store instructions
|
||||
|
|
@ -627,7 +627,7 @@ system.cpu.not_idle_fraction 0.072139 # Pe
|
|||
system.cpu.idle_fraction 0.927861 # Percentage of idle cycles
|
||||
system.cpu.Branches 25929456 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 93218055 67.17% 67.18% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 93218054 67.17% 67.18% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 114528 0.08% 67.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
|
||||
|
|
@ -660,7 +660,7 @@ system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Cl
|
|||
system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 138771626 # Class of executed instruction
|
||||
system.cpu.op_class::total 138771625 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 1699818 # number of replacements
|
||||
|
|
@ -736,10 +736,10 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835992000
|
|||
system.cpu.icache.demand_mshr_miss_latency::total 19835992000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835992000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 19835992000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 598490500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 598490500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 598490500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 598490500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses
|
||||
|
|
@ -837,18 +837,18 @@ system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 467980
|
|||
system.cpu.l2cache.UpgradeReq_miss_latency::total 467980 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46998 # number of SCUpgradeReq miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982693466 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8982693466 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8982758466 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8982758466 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 567750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 1312883000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9901382466 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 11214982716 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9901447466 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 11215047716 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 567750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 1312883000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9901382466 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 11214982716 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9901447466 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 11215047716 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7104 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3702 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1700312 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -902,18 +902,18 @@ system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748
|
|||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.960157 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.960157 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68973.459254 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68973.459254 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69886.602914 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 69887.007964 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72780.253894 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.487074 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69886.602914 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69519.943451 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 69887.007964 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -954,26 +954,26 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719
|
|||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352957534 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352957534 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353022534 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353022534 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087047500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119492534 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9207145784 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119557534 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9207210784 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087047500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119492534 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9207145784 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474790500 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385176750 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5859967250 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119557534 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9207210784 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474790500 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9483342750 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958133250 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -1004,18 +1004,18 @@ system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904
|
|||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.151027 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.151027 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.650125 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.650125 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60260.962359 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.499389 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57374.688635 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57008.955767 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57375.093685 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
|
|
@ -1072,16 +1072,16 @@ system.cpu.dcache.overall_misses::cpu.data 820348 #
|
|||
system.cpu.dcache.overall_misses::total 820348 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658401753 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 11658401753 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 17559222003 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 17559222003 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 17559222003 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 17559222003 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -1112,16 +1112,16 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.019004
|
|||
system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.919957 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.919957 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.924268 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 25041.924268 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.601465 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21404.601465 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
|
||||
|
|
@ -1156,24 +1156,24 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 817570
|
|||
system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002851247 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002851247 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086554497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 16086554497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497744497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 17497744497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790648000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790648000 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10220326000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10220326000 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -1190,18 +1190,18 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.633982 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.633982 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.225539 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.225539 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.136205 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.136205 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||||
|
|
@ -1209,8 +1209,8 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
|
|||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 2294827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2294812 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution
|
||||
|
|
@ -1220,16 +1220,16 @@ system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 #
|
|||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418694 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 5912643 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856060 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205706333 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 52963 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram
|
||||
|
|
@ -1246,13 +1246,13 @@ system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% #
|
|||
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2353775000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 2564913000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1311853505 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -37,13 +37,13 @@ load_offset=2147483648
|
|||
machine_type=VExpress_EMM
|
||||
mem_mode=atomic
|
||||
mem_ranges=2147483648:2415919103
|
||||
memories=system.physmem system.realview.nvmem system.realview.vram
|
||||
memories=system.realview.nvmem system.physmem system.realview.vram
|
||||
multi_proc=true
|
||||
num_work_ids=16
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5.latest/tests/halt.sh
|
||||
readfile=/work/gem5.ext/tests/halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
work_begin_ckpt_count=0
|
||||
|
|
|
|||
|
|
@ -38,7 +38,3 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Oct 29 2014 15:46:15
|
||||
gem5 started Oct 29 2014 16:00:04
|
||||
gem5 compiled Oct 31 2014 10:01:44
|
||||
gem5 started Oct 31 2014 11:27:15
|
||||
gem5 executing on u200540-lin
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.cpu0.isa: ISA system set to: 0x50c1b00 0x50c1b00
|
||||
0: system.cpu1.isa: ISA system set to: 0x50c1b00 0x50c1b00
|
||||
0: system.cpu0.isa: ISA system set to: 0x4171680 0x4171680
|
||||
0: system.cpu1.isa: ISA system set to: 0x4171680 0x4171680
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
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Reference in a new issue