2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 2.909604 # Number of seconds simulated
sim_ticks 2909603958500 # Number of ticks simulated
final_tick 2909603958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-11-16 12:08:57 +01:00
host_inst_rate 491347 # Simulator instruction rate (inst/s)
host_op_rate 592409 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 12712752157 # Simulator tick rate (ticks/s)
host_mem_usage 616676 # Number of bytes of host memory used
host_seconds 228.87 # Real time elapsed on the host
2015-11-06 09:26:50 +01:00
sim_insts 112455934 # Number of instructions simulated
sim_ops 135586369 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2014-10-30 05:18:29 +01:00
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.inst 1186596 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8901732 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1186596 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::cpu.inst 26994 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 139609 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::cpu.inst 407820 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3059431 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::total 3467779 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 407820 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 407820 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2581795 # Write bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::total 2587817 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2581795 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_total::cpu.inst 407820 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3065454 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_total::total 6055597 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 166627 # Number of read requests accepted
system.physmem.writeReqs 121756 # Number of write requests accepted
system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10656896 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue
system.physmem.bytesWritten 7542080 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue
2015-07-03 16:15:03 +02:00
system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one
2015-11-06 09:26:50 +01:00
system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10077 # Per bank write bursts
system.physmem.perBankRdBursts::1 9979 # Per bank write bursts
system.physmem.perBankRdBursts::2 10695 # Per bank write bursts
system.physmem.perBankRdBursts::3 10661 # Per bank write bursts
system.physmem.perBankRdBursts::4 18797 # Per bank write bursts
system.physmem.perBankRdBursts::5 9659 # Per bank write bursts
system.physmem.perBankRdBursts::6 9665 # Per bank write bursts
system.physmem.perBankRdBursts::7 10488 # Per bank write bursts
system.physmem.perBankRdBursts::8 9276 # Per bank write bursts
system.physmem.perBankRdBursts::9 9973 # Per bank write bursts
system.physmem.perBankRdBursts::10 9230 # Per bank write bursts
system.physmem.perBankRdBursts::11 8679 # Per bank write bursts
system.physmem.perBankRdBursts::12 9820 # Per bank write bursts
system.physmem.perBankRdBursts::13 10379 # Per bank write bursts
system.physmem.perBankRdBursts::14 9723 # Per bank write bursts
system.physmem.perBankRdBursts::15 9413 # Per bank write bursts
system.physmem.perBankWrBursts::0 7393 # Per bank write bursts
system.physmem.perBankWrBursts::1 7263 # Per bank write bursts
system.physmem.perBankWrBursts::2 8282 # Per bank write bursts
system.physmem.perBankWrBursts::3 8171 # Per bank write bursts
system.physmem.perBankWrBursts::4 7489 # Per bank write bursts
system.physmem.perBankWrBursts::5 7265 # Per bank write bursts
system.physmem.perBankWrBursts::6 7108 # Per bank write bursts
system.physmem.perBankWrBursts::7 7662 # Per bank write bursts
system.physmem.perBankWrBursts::8 7080 # Per bank write bursts
system.physmem.perBankWrBursts::9 7523 # Per bank write bursts
system.physmem.perBankWrBursts::10 6693 # Per bank write bursts
system.physmem.perBankWrBursts::11 6470 # Per bank write bursts
system.physmem.perBankWrBursts::12 7534 # Per bank write bursts
system.physmem.perBankWrBursts::13 7859 # Per bank write bursts
system.physmem.perBankWrBursts::14 7265 # Per bank write bursts
system.physmem.perBankWrBursts::15 6788 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2909603601500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.readPktSize::6 157055 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.writePktSize::6 117375 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 165631 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::15 2117 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2472 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5973 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7372 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6828 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7824 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7975 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6630 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6710 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5995 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 113 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 58748 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 309.779261 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 182.856223 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.388013 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 21447 36.51% 36.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14643 24.93% 61.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6082 10.35% 71.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3222 5.48% 77.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2599 4.42% 81.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1493 2.54% 84.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1038 1.77% 86.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1067 1.82% 87.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7157 12.18% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 58748 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5762 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.896737 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 590.107660 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 5761 99.98% 99.98% # Reads before turning the bus around for writes
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
2015-11-06 09:26:50 +01:00
system.physmem.rdPerTurnAround::total 5762 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5762 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.452100 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.700018 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.100411 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 4964 86.15% 86.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 94 1.63% 87.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 35 0.61% 88.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 168 2.92% 91.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 22 0.38% 91.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 152 2.64% 94.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 51 0.89% 95.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 7 0.12% 95.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 11 0.19% 95.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 15 0.26% 95.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 3 0.05% 95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 4 0.07% 95.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 174 3.02% 98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 7 0.12% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 3 0.05% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 18 0.31% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 4 0.07% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 2 0.03% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 15 0.26% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5762 # Writes before turning the bus around for reads
system.physmem.totQLat 1626690000 # Total ticks spent queuing
system.physmem.totMemAccLat 4748827500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 832570000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9769.09 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-11-06 09:26:50 +01:00
system.physmem.avgMemAccLat 28519.09 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-03-02 11:04:20 +01:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2014-10-30 05:18:29 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing
system.physmem.readRowHits 136108 # Number of row buffer hits during reads
system.physmem.writeRowHits 89502 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes
system.physmem.avgGap 10089372.82 # Average gap between requests
system.physmem.pageHitRate 79.33 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 230496840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 125767125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 702163800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 90194010705 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1666640821500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1948326896850 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.620811 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2772423900000 # Time in different power states
system.physmem_0.memoryStateTime::REF 97157840000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::ACT 40015565000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.actEnergy 213638040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 116568375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 596637600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 88104913965 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1668473362500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1947916589280 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.479792 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2775503002250 # Time in different power states
system.physmem_1.memoryStateTime::REF 97157840000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::ACT 36942968250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-11-03 17:14:42 +01:00
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
2011-08-19 22:08:09 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walks 9546 # Table walker walks requested
system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 13188.702249 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 10926.693941 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 9189.684239 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst
2011-08-19 22:08:09 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2015-11-06 09:26:50 +01:00
system.cpu.dtb.read_hits 24520223 # DTB read hits
system.cpu.dtb.read_misses 8124 # DTB read misses
system.cpu.dtb.write_hits 19606444 # DTB write hits
system.cpu.dtb.write_misses 1422 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-11-06 09:26:50 +01:00
system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch
2011-08-19 22:08:09 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2014-10-30 05:18:29 +01:00
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
2015-11-06 09:26:50 +01:00
system.cpu.dtb.read_accesses 24528347 # DTB read accesses
system.cpu.dtb.write_accesses 19607866 # DTB write accesses
2011-02-08 04:23:11 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2015-11-06 09:26:50 +01:00
system.cpu.dtb.hits 44126667 # DTB hits
system.cpu.dtb.misses 9546 # DTB misses
system.cpu.dtb.accesses 44136213 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walks 4763 # Table walker walks requested
system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 1638383000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 1638383000 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.itb.inst_hits 115553087 # ITB inst hits
2015-09-25 13:27:03 +02:00
system.cpu.itb.inst_misses 4763 # ITB inst misses
2011-08-19 22:08:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
2011-08-19 22:08:09 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2015-11-06 09:26:50 +01:00
system.cpu.itb.inst_accesses 115557850 # ITB inst accesses
system.cpu.itb.hits 115553087 # DTB hits
2015-09-25 13:27:03 +02:00
system.cpu.itb.misses 4763 # DTB misses
2015-11-06 09:26:50 +01:00
system.cpu.itb.accesses 115557850 # DTB accesses
system.cpu.numCycles 5819207917 # number of cpu cycles simulated
2011-08-19 22:08:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed
system.cpu.committedInsts 112455934 # Number of instructions committed
system.cpu.committedOps 135586369 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 119891885 # Number of integer alu accesses
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
2015-11-06 09:26:50 +01:00
system.cpu.num_func_calls 9891908 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 15230427 # number of instructions that are conditional controls
system.cpu.num_int_insts 119891885 # number of integer instructions
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_insts 11161 # number of float instructions
2015-11-06 09:26:50 +01:00
system.cpu.num_int_register_reads 218060317 # number of times the integer registers were read
system.cpu.num_int_register_writes 82644878 # number of times the integer registers were written
2015-03-02 11:04:20 +01:00
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
2014-10-30 05:18:29 +01:00
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
2015-11-06 09:26:50 +01:00
system.cpu.num_cc_register_reads 489736143 # number of times the CC registers were read
system.cpu.num_cc_register_writes 51894204 # number of times the CC registers were written
system.cpu.num_mem_refs 45406948 # number of memory refs
system.cpu.num_load_insts 24842511 # Number of load instructions
system.cpu.num_store_insts 20564437 # Number of store instructions
system.cpu.num_idle_cycles 5379072532.100152 # Number of idle cycles
system.cpu.num_busy_cycles 440135384.899849 # Number of busy cycles
system.cpu.not_idle_fraction 0.075635 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.924365 # Percentage of idle cycles
system.cpu.Branches 25916368 # Number of branches fetched
2014-10-30 05:18:29 +01:00
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::IntAlu 93174225 67.17% 67.18% # Class of executed instruction
system.cpu.op_class::IntMult 114427 0.08% 67.26% # Class of executed instruction
2014-10-30 05:18:29 +01:00
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
2015-07-03 16:15:03 +02:00
system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Class of executed instruction
2014-10-30 05:18:29 +01:00
system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::MemRead 24842511 17.91% 85.17% # Class of executed instruction
system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2015-11-06 09:26:50 +01:00
system.cpu.op_class::total 138706392 # Class of executed instruction
system.cpu.dcache.tags.replacements 819093 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 43235572 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 819605 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 52.751718 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tag_accesses 177109325 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 177109325 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23112645 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23112645 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 18823942 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 18823942 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 392782 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 392782 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443235 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 443235 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460203 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460203 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 41936587 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41936587 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 42329369 # number of overall hits
system.cpu.dcache.overall_hits::total 42329369 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 399856 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 399856 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 298641 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 298641 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 118367 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 118367 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22751 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22751 # number of LoadLockedReq misses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_misses::cpu.data 698497 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 698497 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 816864 # number of overall misses
system.cpu.dcache.overall_misses::total 816864 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6484051000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6484051000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19116145000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 19116145000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294006500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 294006500 # number of LoadLockedReq miss cycles
2015-03-02 11:04:20 +01:00
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 25600196000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 25600196000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 25600196000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 25600196000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23512501 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23512501 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511149 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511149 # number of SoftPFReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465986 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 465986 # number of LoadLockedReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460205 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460205 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 42635084 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 42635084 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43146233 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43146233 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231570 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.231570 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048823 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048823 # miss rate for LoadLockedReq accesses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.016383 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.018932 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16215.965247 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16215.965247 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64010.450675 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64010.450675 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12922.794602 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12922.794602 # average LoadLockedReq miss latency
2015-03-02 11:04:20 +01:00
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36650.402221 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36650.402221 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31339.606103 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31339.606103 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.dcache.writebacks::writebacks 683726 # number of writebacks
system.cpu.dcache.writebacks::total 683726 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 924 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 924 # number of ReadReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14242 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14242 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 924 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 924 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 924 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 924 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398932 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 398932 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298641 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 298641 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116310 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 116310 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8509 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8509 # number of LoadLockedReq MSHR misses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 697573 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 697573 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 813883 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 813883 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6055510500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6055510500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18817504000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 18817504000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617135000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617135000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115280000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115280000 # number of LoadLockedReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24873014500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 24873014500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26490149500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26490149500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279074500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279074500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089978000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089978000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369052500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369052500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016967 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227546 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227546 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018260 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018260 # mshr miss rate for LoadLockedReq accesses
2014-11-12 15:05:25 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016361 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018863 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15179.304994 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15179.304994 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63010.450675 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63010.450675 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13903.662626 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13903.662626 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13548.007992 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13548.007992 # average LoadLockedReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35656.504050 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35656.504050 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32547.859459 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 32547.859459 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201653.108742 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201653.108742 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.022581 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.022581 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193591.576277 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193591.576277 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.replacements 1695571 # number of replacements
system.cpu.icache.tags.tagsinuse 510.436867 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 113856998 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1696083 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 67.129379 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.436867 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tag_accesses 117249176 # Number of tag accesses
system.cpu.icache.tags.data_accesses 117249176 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 113856998 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 113856998 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 113856998 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 113856998 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 113856998 # number of overall hits
system.cpu.icache.overall_hits::total 113856998 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1696089 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1696089 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1696089 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1696089 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1696089 # number of overall misses
system.cpu.icache.overall_misses::total 1696089 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24269708000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24269708000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24269708000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24269708000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24269708000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24269708000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 115553087 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 115553087 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 115553087 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 115553087 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 115553087 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 115553087 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014678 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014678 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014678 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014678 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014678 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014678 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.218443 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14309.218443 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.218443 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14309.218443 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.218443 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14309.218443 # average overall miss latency
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 1695571 # number of writebacks
system.cpu.icache.writebacks::total 1695571 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696089 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1696089 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1696089 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1696089 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1696089 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1696089 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22573619000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22573619000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22573619000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22573619000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22573619000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22573619000 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014678 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.218443 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.218443 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.218443 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.218443 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.replacements 87564 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64865.227437 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4544047 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 152799 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 29.738722 # Average number of references to valid blocks.
2014-11-12 15:05:25 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50197.653066 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799333 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012653 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.739092 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.023293 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.765955 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148037 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.075714 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6852 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56198 # Occupied blocks per task id
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 40507837 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 40507837 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7811 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 11850 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 683726 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 683726 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1664804 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1664804 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 166964 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 166964 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678077 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1678077 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511579 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 511579 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7811 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1678077 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 678543 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2368470 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7811 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1678077 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 678543 # number of overall hits
system.cpu.l2cache.overall_hits::total 2368470 # number of overall hits
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2740 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2740 # number of UpgradeReq misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 128914 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 128914 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17979 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 17979 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 141086 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 159074 # number of demand (read+write) misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 17979 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 141086 # number of overall misses
system.cpu.l2cache.overall_misses::total 159074 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1147500 # number of ReadReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_miss_latency::total 1413500 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1857500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16391193500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 16391193500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2350840500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2350840500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1613502500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1613502500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1147500 # number of demand (read+write) miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 2350840500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 18004696000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20356950000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1147500 # number of overall miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 2350840500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 18004696000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20356950000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7818 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 11859 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 683726 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 683726 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1664804 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1664804 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2763 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses)
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 295878 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 295878 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696056 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1696056 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523751 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 523751 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7818 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1696056 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 819629 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2527544 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7818 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 4041 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1696056 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 819629 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2527544 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000895 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000759 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991676 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435700 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.435700 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010600 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010600 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023240 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023240 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000895 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010600 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.172134 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.062936 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000895 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010600 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.172134 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.062936 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 163928.571429 # average ReadReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::total 157055.555556 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 677.919708 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 677.919708 # average UpgradeReq miss latency
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127148.281025 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127148.281025 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130754.797263 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130754.797263 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132558.535984 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132558.535984 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 163928.571429 # average overall miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130754.797263 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127615.043307 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 127971.572979 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 163928.571429 # average overall miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130754.797263 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127615.043307 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 127971.572979 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks
system.cpu.l2cache.writebacks::total 81185 # number of writebacks
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2740 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128914 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 128914 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17979 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17979 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12172 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12172 # number of ReadSharedReq MSHR misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 17979 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 141086 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 159074 # number of demand (read+write) MSHR misses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
2013-05-30 18:54:18 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 17979 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141086 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 159074 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1077500 # number of ReadReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1323500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 194003000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 194003000 # number of UpgradeReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15102053500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15102053500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171050500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171050500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1491782500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1491782500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1077500 # number of demand (read+write) MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171050500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16593836000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 18766210000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1077500 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171050500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16593836000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 18766210000 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5889729000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6919495000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574500 # number of WriteReq MSHR uncacheable cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10662303500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11692069500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991676 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435700 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435700 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023240 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023240 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.062936 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.062936 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average ReadReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 147055.555556 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.014599 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.014599 # average UpgradeReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.281025 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.281025 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120754.797263 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120754.797263 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122558.535984 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122558.535984 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189149.238872 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172298.182271 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.310559 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.310559 # average WriteReq mshr uncacheable latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181557.094692 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172579.218881 # average overall mshr uncacheable latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5052300 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536604 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2287266 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 801101 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1664804 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 134612 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 295878 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 295878 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696089 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 523979 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074993 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574186 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25655 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7688091 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215131128 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96411485 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31272 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 311590049 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 175874 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2773719 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.020869 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.142946 # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2715834 97.91% 97.91% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 57885 2.09% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::total 2773719 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4957066000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 2553155500 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 1275758999 # Layer occupancy (ticks)
2014-10-30 05:18:29 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks)
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.trans_dist::ReadReq 30177 # Transaction distribution
system.iobus.trans_dist::ReadResp 30177 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer6.occupancy 94500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer7.occupancy 644500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer23.occupancy 6288500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer24.occupancy 174000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer25.occupancy 36469500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer26.occupancy 127000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer27.occupancy 186222546 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iocache.tags.replacements 36418 # number of replacements
2015-11-06 09:26:50 +01:00
system.iocache.tags.tagsinuse 1.084136 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2015-11-06 09:26:50 +01:00
system.iocache.tags.warmup_cycle 313818895000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.084136 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.iocache.tags.tag_accesses 328068 # Number of tag accesses
system.iocache.tags.data_accesses 328068 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses
system.iocache.ReadReq_misses::total 228 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2015-09-25 13:27:03 +02:00
system.iocache.demand_misses::realview.ide 228 # number of demand (read+write) misses
system.iocache.demand_misses::total 228 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 228 # number of overall misses
system.iocache.overall_misses::total 228 # number of overall misses
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4715427169 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4715427169 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles
system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.iocache.demand_accesses::realview.ide 228 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 228 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 228 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 228 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130174.115752 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130174.115752 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 753 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked
2011-08-19 22:08:09 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.296296 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2011-08-19 22:08:09 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2015-09-25 13:27:03 +02:00
system.iocache.demand_mshr_misses::realview.ide 228 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904227169 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2904227169 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80174.115752 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80174.115752 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 40160 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 70548 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
system.membus.trans_dist::WriteResp 27589 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution
system.membus.trans_dist::CleanEvict 6392 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution
2014-11-12 15:05:25 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution
system.membus.trans_dist::ReadExReq 127157 # Transaction distribution
system.membus.trans_dist::ReadExResp 127157 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546415 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302268 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465621 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size::total 17782741 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.snoops 492 # Total snoops (count)
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::samples 389999 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::1 389999 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 389999 # Request fanout histogram
system.membus.reqLayer0.occupancy 90471000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer5.occupancy 823075656 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer2.occupancy 952261248 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer3.occupancy 64129261 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-09-25 13:27:03 +02:00
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
