stats: Update stats to reflect snoop-filter changes
This commit is contained in:
Andreas Hansson
parent
a9a7002a3b
commit
806e1fbf0f
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
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sim_ticks 51111152682000 # Number of ticks simulated
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final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 926984 # Simulator instruction rate (inst/s)
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host_op_rate 1089358 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 48121696814 # Simulator tick rate (ticks/s)
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host_mem_usage 716268 # Number of bytes of host memory used
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host_seconds 1062.12 # Real time elapsed on the host
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host_inst_rate 1154147 # Simulator instruction rate (inst/s)
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host_op_rate 1356312 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 59914222846 # Simulator tick rate (ticks/s)
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host_mem_usage 725376 # Number of bytes of host memory used
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host_seconds 853.07 # Real time elapsed on the host
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sim_insts 984570519 # Number of instructions simulated
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sim_ops 1157031967 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -414,9 +414,9 @@ system.cpu.icache.cache_copies 0 # nu
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 1722572 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 46968482 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.total_refs 46966735 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 26.300086 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 26.299108 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor
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@ -439,8 +439,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910
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system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.tag_accesses 426199223 # Number of tag accesses
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system.cpu.l2cache.tags.data_accesses 426199223 # Number of data accesses
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system.cpu.l2cache.tags.tag_accesses 426185247 # Number of tag accesses
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system.cpu.l2cache.tags.data_accesses 426185247 # Number of data accesses
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system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits
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@ -554,12 +554,18 @@ system.cpu.l2cache.cache_copies 0 # nu
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system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks
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system.cpu.l2cache.writebacks::total 1503689 # number of writebacks
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter.
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system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data.
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system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
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system.cpu.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter.
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system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
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system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
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system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
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@ -569,28 +575,28 @@ system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 #
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system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42974207 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35074071 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42972629 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35073902 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count::total 80350446 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
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system.cpu.toL2Bus.snoop_fanout::samples 53244635 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::mean 1.023788 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::stdev 0.152389 # Request fanout histogram
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system.cpu.toL2Bus.snoops 1954373 # Total snoops (count)
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system.cpu.toL2Bus.snoop_fanout::samples 55082670 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::1 51978030 97.62% 97.62% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::2 1266605 2.38% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::0 54487002 98.92% 98.92% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::1 595668 1.08% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::total 53244635 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::total 55082670 # Request fanout histogram
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system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
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system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
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system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
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@ -708,7 +714,7 @@ system.membus.trans_dist::ReadResp 525878 # Tr
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system.membus.trans_dist::WriteReq 33606 # Transaction distribution
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system.membus.trans_dist::WriteResp 33606 # Transaction distribution
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system.membus.trans_dist::Writeback 1610320 # Transaction distribution
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system.membus.trans_dist::CleanEvict 228940 # Transaction distribution
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system.membus.trans_dist::CleanEvict 225581 # Transaction distribution
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system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
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system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
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system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
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@ -720,11 +726,11 @@ system.membus.trans_dist::InvalidateResp 106664 # Tr
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5530871 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5660063 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 6006568 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5529643 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5658835 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 6003209 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
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@ -734,17 +740,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040
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system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 3922914 # Request fanout histogram
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system.membus.snoop_fanout::samples 3921686 # Request fanout histogram
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::1 3922914 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::1 3921686 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 1 # Request fanout histogram
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system.membus.snoop_fanout::max_value 1 # Request fanout histogram
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system.membus.snoop_fanout::total 3922914 # Request fanout histogram
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system.membus.snoop_fanout::total 3921686 # Request fanout histogram
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system.realview.ethernet.txBytes 966 # Bytes Transmitted
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system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
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system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
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File diff suppressed because it is too large
Load diff
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@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
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sim_ticks 51111152682000 # Number of ticks simulated
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final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 921297 # Simulator instruction rate (inst/s)
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host_op_rate 1082675 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 47826467843 # Simulator tick rate (ticks/s)
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host_mem_usage 712064 # Number of bytes of host memory used
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host_seconds 1068.68 # Real time elapsed on the host
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host_inst_rate 1157716 # Simulator instruction rate (inst/s)
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host_op_rate 1360507 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 60099512933 # Simulator tick rate (ticks/s)
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host_mem_usage 720388 # Number of bytes of host memory used
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host_seconds 850.44 # Real time elapsed on the host
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sim_insts 984570519 # Number of instructions simulated
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sim_ops 1157031967 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -414,9 +414,9 @@ system.cpu.icache.cache_copies 0 # nu
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 1722572 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 46968482 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.total_refs 46966735 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 26.300086 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 26.299108 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor
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@ -439,8 +439,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910
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system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.tag_accesses 426199223 # Number of tag accesses
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system.cpu.l2cache.tags.data_accesses 426199223 # Number of data accesses
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system.cpu.l2cache.tags.tag_accesses 426185247 # Number of tag accesses
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system.cpu.l2cache.tags.data_accesses 426185247 # Number of data accesses
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system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits
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@ -554,12 +554,18 @@ system.cpu.l2cache.cache_copies 0 # nu
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system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks
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system.cpu.l2cache.writebacks::total 1503689 # number of writebacks
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter.
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system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data.
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system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
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system.cpu.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter.
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system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
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system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
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system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
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@ -569,28 +575,28 @@ system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 #
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system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42974207 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35074071 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42972629 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35073902 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 80350446 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 53244635 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.023788 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.152389 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoops 1954373 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55082670 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 51978030 97.62% 97.62% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1266605 2.38% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54487002 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 595668 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 53244635 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55082670 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
||||
|
|
@ -708,7 +714,7 @@ system.membus.trans_dist::ReadResp 525878 # Tr
|
|||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1610320 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 228940 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 225581 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
|
||||
|
|
@ -720,11 +726,11 @@ system.membus.trans_dist::InvalidateResp 106664 # Tr
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5530871 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5660063 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6006568 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5529643 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5658835 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6003209 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -734,17 +740,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040
|
|||
system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3922914 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3921686 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3922914 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3921686 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3922914 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3921686 # Request fanout histogram
|
||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
|
|||
sim_ticks 51111152682000 # Number of ticks simulated
|
||||
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 916811 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1077403 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 47593586653 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 712068 # Number of bytes of host memory used
|
||||
host_seconds 1073.91 # Real time elapsed on the host
|
||||
host_inst_rate 1150787 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1352364 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59739798990 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 722184 # Number of bytes of host memory used
|
||||
host_seconds 855.56 # Real time elapsed on the host
|
||||
sim_insts 984570519 # Number of instructions simulated
|
||||
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -788,9 +788,9 @@ system.iocache.writebacks::total 106631 # nu
|
|||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 1722562 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65341.862549 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 47050546 # Total number of references to valid blocks.
|
||||
system.l2c.tags.total_refs 47048799 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1785858 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 26.346185 # Average number of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 26.345207 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 37097.979539 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460552 # Average occupied blocks per requestor
|
||||
|
|
@ -821,8 +821,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 4910 #
|
|||
system.l2c.tags.age_task_id_blocks_1024::4 54672 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.961609 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 426855693 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 426855693 # Number of data accesses
|
||||
system.l2c.tags.tag_accesses 426841717 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 426841717 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits
|
||||
|
|
@ -1001,7 +1001,7 @@ system.membus.trans_dist::ReadResp 525866 # Tr
|
|||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1610322 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 228928 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 225569 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution
|
||||
|
|
@ -1013,11 +1013,11 @@ system.membus.trans_dist::InvalidateResp 106664 # Tr
|
|||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5530845 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 5660037 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346505 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 346505 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6006542 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5529617 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 5658809 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6003183 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -1027,17 +1027,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040
|
|||
system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220300218 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3922896 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3921668 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3922896 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3921668 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3922896 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3921668 # Request fanout histogram
|
||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||
|
|
@ -1090,12 +1090,18 @@ system.realview.realview_io.osc_peripheral.clock 41667
|
|||
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.toL2Bus.snoop_filter.tot_requests 52477792 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 26568978 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.trans_dist::ReadReq 1320350 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 16986503 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution
|
||||
|
|
@ -1105,27 +1111,27 @@ system.toL2Bus.trans_dist::ReadCleanReq 14296158 # Tr
|
|||
system.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42974207 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35074075 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42972629 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35073906 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 80535624 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 80533877 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 2159735666 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 116338 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 53337224 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 1.025483 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.157587 # Request fanout histogram
|
||||
system.toL2Bus.snoops 1954363 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 55175249 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.011169 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.105093 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 51978032 97.45% 97.45% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 1359192 2.55% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 54558983 98.88% 98.88% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 616266 1.12% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 53337224 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 55175249 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.061241 # Number of seconds simulated
|
||||
sim_ticks 61240850500 # Number of ticks simulated
|
||||
final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 61241011500 # Number of ticks simulated
|
||||
final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 182783 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 183693 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 123547949 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 442472 # Number of bytes of host memory used
|
||||
host_seconds 495.69 # Real time elapsed on the host
|
||||
host_inst_rate 252391 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 253648 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 170598134 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 450980 # Number of bytes of host memory used
|
||||
host_seconds 358.98 # Real time elapsed on the host
|
||||
sim_insts 90602850 # Number of instructions simulated
|
||||
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu
|
|||
system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 808870 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 15466760 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 16275629 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 808870 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 808870 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 808870 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 15466760 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 16275629 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 15574 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 61240757000 # Total gap between requests
|
||||
system.physmem.totGap 61240917000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 73458500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1543 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 644.935839 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 438.870546 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 402.302511 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 247 16.01% 16.01% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 187 12.12% 28.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 93 6.03% 34.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 68 4.41% 38.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 69 4.47% 43.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 87 5.64% 48.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 73241750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -220,35 +220,35 @@ system.physmem.readRowHits 14026 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 3932243.29 # Average gap between requests
|
||||
system.physmem.avgGap 3932253.56 # Average gap between requests
|
||||
system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 671.518851 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 671.511702 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 671.514525 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 671.513254 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 20752188 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted
|
||||
|
|
@ -377,29 +377,29 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 122481701 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 122482023 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90602850 # Number of instructions committed
|
||||
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2176623 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.351853 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.739726 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.351856 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.739724 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 946097 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.872758 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.883026 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.883026 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses
|
||||
|
|
@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data 989217 # n
|
|||
system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 989221 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.036309
|
|||
system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950190
|
|||
system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -516,69 +516,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 5 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27770468 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 34626.518703 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 689.439811 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.336641 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.336641 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27770466 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 55543342 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 55543342 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27770468 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27770468 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27770468 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27770468 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27770468 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27770468 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 802 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 59898000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 59898000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 59898000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 59898000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 59898000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 59898000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27771270 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27771270 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27771270 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27771270 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27771270 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27771270 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 74685.785536 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 74685.785536 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802
|
|||
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59096000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 59096000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59096000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 59096000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59096000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 59096000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.312670 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
||||
|
|
@ -660,18 +660,18 @@ system.cpu.l2cache.demand_misses::total 15582 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1147383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 57828000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1089555000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1147383000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -698,18 +698,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -740,18 +740,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -764,19 +764,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution
|
||||
|
|
@ -792,14 +798,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks)
|
||||
|
|
@ -827,9 +833,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15574 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.361489 # Number of seconds simulated
|
||||
sim_ticks 361488535500 # Number of ticks simulated
|
||||
final_tick 361488535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 361488536500 # Number of ticks simulated
|
||||
final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1224088 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1224138 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1814798992 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 426288 # Number of bytes of host memory used
|
||||
host_seconds 199.19 # Real time elapsed on the host
|
||||
host_inst_rate 1117046 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1656101101 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 428664 # Number of bytes of host memory used
|
||||
host_seconds 218.28 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -31,7 +31,7 @@ system.physmem.bw_total::cpu.data 2606821 # To
|
|||
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 722977071 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 722977073 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 243825150 # Number of instructions committed
|
||||
|
|
@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu
|
|||
system.cpu.num_load_insts 82803521 # Number of load instructions
|
||||
system.cpu.num_store_insts 22907920 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 722977070.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29302884 # Number of branches fetched
|
||||
|
|
@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 244431613 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3562.469039 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 134366268500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469039 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n
|
|||
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
|
|||
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720878000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720878000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893170000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11893170000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893170000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11893170000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -206,24 +206,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.385281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.139334 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.412974 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412974 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
|
||||
|
|
@ -304,13 +304,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9730.625133 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670093 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635586 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
|
|
@ -458,6 +458,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution
|
||||
|
|
@ -473,14 +479,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1875953 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.061602 # Nu
|
|||
sim_ticks 61602395500 # Number of ticks simulated
|
||||
final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 83209 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 146518 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32444685 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 451056 # Number of bytes of host memory used
|
||||
host_seconds 1898.69 # Real time elapsed on the host
|
||||
host_inst_rate 109389 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 192617 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42652748 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 458300 # Number of bytes of host memory used
|
||||
host_seconds 1444.28 # Real time elapsed on the host
|
||||
sim_insts 157988547 # Number of instructions simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -222,12 +222,12 @@ system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Wr
|
|||
system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 132992250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 132940250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -249,28 +249,28 @@ system.physmem_0.preEnergy 5960625 # En
|
|||
system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 673.233667 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 673.233237 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 673.432156 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 673.431985 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 36908902 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted
|
||||
|
|
@ -325,24 +325,24 @@ system.cpu.decode.SquashCycles 776598 # Nu
|
|||
system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking
|
||||
system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename
|
||||
system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups
|
||||
system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 492 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads.
|
||||
|
|
@ -358,13 +358,13 @@ system.cpu.iq.issued_per_cycle::samples 123139971 # Nu
|
|||
system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
|
|
@ -401,7 +401,7 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # at
|
|||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
|
|
@ -441,15 +441,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued
|
||||
system.cpu.iq.rate 2.484506 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
|
|
@ -464,14 +464,14 @@ system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Nu
|
|||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly
|
||||
|
|
@ -485,7 +485,7 @@ system.cpu.iew.exec_refs 131430383 # nu
|
|||
system.cpu.iew.exec_branches 31401847 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 33679798 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.476825 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 230213925 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value
|
||||
|
|
@ -500,14 +500,14 @@ system.cpu.commit.committed_per_cycle::samples 117119203
|
|||
system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
|
|
@ -570,7 +570,7 @@ system.cpu.cpi_total 0.779834 # CP
|
|||
system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 491477122 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 239432261 # number of integer regfile writes
|
||||
system.cpu.int_regfile_writes 239432260 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 110 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 84 # number of floating regfile writes
|
||||
system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads
|
||||
|
|
@ -609,14 +609,14 @@ system.cpu.dcache.demand_misses::cpu.data 2785082 # n
|
|||
system.cpu.dcache.demand_misses::total 2785082 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2785082 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2785082 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304422000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 32304422000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -633,19 +633,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306
|
|||
system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -667,14 +667,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2076410
|
|||
system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -683,22 +683,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 53 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 825.040012 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.402852 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id
|
||||
|
|
@ -721,12 +721,12 @@ system.cpu.icache.demand_misses::cpu.inst 1323 # n
|
|||
system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1323 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 97269000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 97269000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 97269000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 97269000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 97269000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 97269000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27443892 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27443892 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27443892 # number of demand (read+write) accesses
|
||||
|
|
@ -739,12 +739,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000048
|
|||
system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73521.541950 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 73521.541950 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 73521.541950 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 73521.541950 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 73521.541950 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -765,34 +765,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1014
|
|||
system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77416000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 77416000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77416000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 77416000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77416000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 77416000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76347.140039 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76347.140039 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76347.140039 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76347.140039 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 487 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20712.335895 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.711824 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576431 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841934 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917530 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.603991 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy
|
||||
|
|
@ -834,18 +834,18 @@ system.cpu.l2cache.demand_misses::total 30422 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30422 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118154500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2118154500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75720000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 75720000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32849000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 32849000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 75720000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 2151003500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 2226723500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 75720000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 2151003500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 2226723500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2066601 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2066601 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses)
|
||||
|
|
@ -874,18 +874,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014644 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.847921 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.847921 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75871.743487 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75871.743487 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77110.328638 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77110.328638 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73194.513839 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75871.743487 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73103.707858 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73194.513839 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -910,18 +910,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30422
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828174500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828174500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65740000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65740000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28589000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28589000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65740000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856763500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1922503500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65740000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -936,19 +936,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution
|
||||
|
|
@ -966,15 +972,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 487 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
|
||||
|
|
@ -1005,7 +1011,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 30636 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu
|
|||
sim_ticks 365988859500 # Number of ticks simulated
|
||||
final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 643347 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1132831 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1490347920 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 451472 # Number of bytes of host memory used
|
||||
host_seconds 245.57 # Real time elapsed on the host
|
||||
host_inst_rate 563395 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 992048 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1305133674 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 455224 # Number of bytes of host memory used
|
||||
host_seconds 280.42 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution
|
||||
|
|
@ -464,15 +470,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 313 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.000076 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.008704 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000048 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.006906 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 4130394 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 313 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 4130510 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 197 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.412080 # Nu
|
|||
sim_ticks 412080064500 # Number of ticks simulated
|
||||
final_tick 412080064500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 229857 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 229857 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 154795079 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293864 # Number of bytes of host memory used
|
||||
host_seconds 2662.10 # Real time elapsed on the host
|
||||
host_inst_rate 310711 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 310711 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 209245414 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301844 # Number of bytes of host memory used
|
||||
host_seconds 1969.36 # Real time elapsed on the host
|
||||
sim_insts 611901617 # Number of instructions simulated
|
||||
sim_ops 611901617 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -704,6 +704,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5082760 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538418 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2391 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2391 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1766182 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2633081 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 252234 # Transaction distribution
|
||||
|
|
@ -719,15 +725,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 312573696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 346897 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5429657 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.063889 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.244556 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000440 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.020980 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5082760 93.61% 93.61% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 346897 6.39% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5427266 99.96% 99.96% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2391 0.04% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5429657 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4881002000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.707533 # Number of seconds simulated
|
||||
sim_ticks 707533448500 # Number of ticks simulated
|
||||
final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.707537 # Number of seconds simulated
|
||||
sim_ticks 707536959500 # Number of ticks simulated
|
||||
final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1147583 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1607870578 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 316160 # Number of bytes of host memory used
|
||||
host_seconds 440.04 # Real time elapsed on the host
|
||||
host_inst_rate 1064510 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1491485099 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319084 # Number of bytes of host memory used
|
||||
host_seconds 474.38 # Real time elapsed on the host
|
||||
sim_insts 504986854 # Number of instructions simulated
|
||||
sim_ops 546878105 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 139793 # Nu
|
|||
system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1415066897 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1415073919 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504986854 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu
|
|||
system.cpu.num_load_insts 115884756 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 121548302 # Number of branches fetched
|
||||
|
|
@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 548695379 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n
|
|||
system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766
|
|||
system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917
|
|||
system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
|
|
@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n
|
|||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses
|
||||
|
|
@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022
|
|||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -415,38 +415,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521
|
|||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 253923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253923000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 253923000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253923000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 253923000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109779 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27249.065072 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 338493397000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705162 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.355202 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110362 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831575 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
||||
|
|
@ -485,14 +485,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500
|
|||
system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053299500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053299500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -523,14 +523,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004
|
|||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -559,14 +559,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500
|
|||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -585,15 +585,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004
|
|||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution
|
||||
|
|
@ -609,14 +615,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 109779 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks)
|
||||
|
|
@ -646,9 +652,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 251058 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 1.647861 # Nu
|
|||
sim_ticks 1647861059500 # Number of ticks simulated
|
||||
final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 708384 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1309882 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1411719986 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323600 # Number of bytes of host memory used
|
||||
host_seconds 1167.27 # Real time elapsed on the host
|
||||
host_inst_rate 657040 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1214941 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1309397988 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 327616 # Number of bytes of host memory used
|
||||
host_seconds 1258.49 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -455,6 +455,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution
|
||||
|
|
@ -470,15 +476,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 348182 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.064657 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.245920 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000321 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.017916 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5036887 93.53% 93.53% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 348182 6.47% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5383340 99.97% 99.97% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1729 0.03% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.225711 # Nu
|
|||
sim_ticks 225710988500 # Number of ticks simulated
|
||||
final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 225638 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 225638 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 127748919 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297512 # Number of bytes of host memory used
|
||||
host_seconds 1766.83 # Real time elapsed on the host
|
||||
host_inst_rate 311102 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 311102 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 176136084 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304484 # Number of bytes of host memory used
|
||||
host_seconds 1281.46 # Real time elapsed on the host
|
||||
sim_insts 398664665 # Number of instructions simulated
|
||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -661,6 +661,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 13288 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3958 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 3304 # Transaction distribution
|
||||
|
|
@ -676,15 +682,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 638976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 13288 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 13288 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 13288 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 13288 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7298000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.067874 # Nu
|
|||
sim_ticks 67874346000 # Number of ticks simulated
|
||||
final_tick 67874346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 172313 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 172313 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31140671 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 298536 # Number of bytes of host memory used
|
||||
host_seconds 2179.60 # Real time elapsed on the host
|
||||
host_inst_rate 238872 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 238872 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43169272 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305488 # Number of bytes of host memory used
|
||||
host_seconds 1572.28 # Real time elapsed on the host
|
||||
sim_insts 375574808 # Number of instructions simulated
|
||||
sim_ops 375574808 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -955,6 +955,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65792.367963
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 11134 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2903 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5042 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 656 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2247 # Transaction distribution
|
||||
|
|
@ -970,15 +976,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 568768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11134 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 11134 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11134 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11134 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 6223000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
|
|||
sim_ticks 567335097500 # Number of ticks simulated
|
||||
final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1293186 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1293186 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1840317995 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300812 # Number of bytes of host memory used
|
||||
host_seconds 308.28 # Real time elapsed on the host
|
||||
host_inst_rate 1348015 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1348015 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1918345002 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301916 # Number of bytes of host memory used
|
||||
host_seconds 295.74 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -472,6 +472,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution
|
||||
|
|
@ -487,15 +493,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 10358 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 10358 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.215506 # Number of seconds simulated
|
||||
sim_ticks 215505832500 # Number of ticks simulated
|
||||
final_tick 215505832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.215510 # Number of seconds simulated
|
||||
sim_ticks 215510486500 # Number of ticks simulated
|
||||
final_tick 215510486500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 114925 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 137980 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 90709005 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317788 # Number of bytes of host memory used
|
||||
host_seconds 2375.79 # Real time elapsed on the host
|
||||
host_inst_rate 166248 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 199599 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 131220473 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 326292 # Number of bytes of host memory used
|
||||
host_seconds 1642.35 # Real time elapsed on the host
|
||||
sim_insts 273037857 # Number of instructions simulated
|
||||
sim_ops 327812214 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 218880 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1015657 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1236013 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2251670 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1015657 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1015657 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1015657 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1236013 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2251670 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1015635 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1235986 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2251621 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1015635 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1015635 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1015635 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1235986 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2251621 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7582 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 215505593500 # Total gap between requests
|
||||
system.physmem.totGap 215510247500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 892 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 893 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 318.272548 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 188.961816 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 330.159233 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 550 36.21% 36.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 342 22.51% 58.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 179 11.78% 70.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 82 5.40% 75.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 73 4.81% 80.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 43 2.83% 83.54% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 37 2.44% 85.98% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 30 1.97% 87.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 183 12.05% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52046750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 194209250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1514 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 319.408190 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 189.009179 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 331.260420 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 549 36.26% 36.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 346 22.85% 59.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 166 10.96% 70.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 79 5.22% 75.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 78 5.15% 80.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 48 3.17% 83.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 37 2.44% 86.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 27 1.78% 87.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 184 12.15% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1514 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52026250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 194188750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6864.51 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6861.81 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25614.51 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25611.81 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.02 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6056 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6062 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 79.87 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 79.95 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 28423317.53 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.87 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 4997160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2726625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 28423931.35 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.95 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5632744275 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 124359177000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 144104965380 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.699601 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 206882994500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7196020000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5660638650 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 124339380000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 144113699910 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.715971 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 206848311250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1423707500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1464242250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 6388200 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3485625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5808881115 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 124204671000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 144127934910 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.806188 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 206624169250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7196020000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5785657605 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 124229714250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 144130146360 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.792285 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 206662748250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1683261250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1649073000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 32816945 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 16892744 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 32816918 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 16892730 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 17497063 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15468368 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 17497037 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15468342 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 88.405511 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 88.405494 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
|
|
@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 431011665 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 431020973 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037857 # Number of instructions committed
|
||||
system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 3889170 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.578578 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.633481 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 427409330 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3602335 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.578612 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.633468 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 427416493 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3604480 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 1354 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3085.814933 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168714880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3085.814208 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37400.771448 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814933 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814208 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
||||
|
|
@ -404,42 +404,42 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 337448855 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337448855 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86582107 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86582107 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82047449 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82047449 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 337448859 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337448859 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86582109 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86582109 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168629556 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168629556 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168693090 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168693090 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168629560 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168629560 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168693094 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168693094 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5228 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5228 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 7287 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7287 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7292 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7292 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 135542000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 135542000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 392317500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 392317500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 527859500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 527859500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 527859500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 527859500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86584166 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86584166 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 7285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7290 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 136254500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 136254500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 393515500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 393515500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 529770000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 529770000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 529770000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 529770000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses)
|
||||
|
|
@ -448,10 +448,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168636843 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168636843 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168700382 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168700382 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168636845 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168636845 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168700384 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168700384 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
|
||||
|
|
@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72438.520653 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72388.850795 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72720.658888 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72670.781893 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -482,12 +482,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu
|
|||
system.cpu.dcache.writebacks::total 1010 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2358 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2358 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
|
||||
|
|
@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4508
|
|||
system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109498500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109498500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218637500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 218637500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109975000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109975000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219249000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219249000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 328136000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 328136000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 328374000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 328374000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329224000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 329224000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329462000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 329462000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 36873 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1923.841153 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 72548906 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1923.840697 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 72548791 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1869.383545 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1869.380582 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1923.841153 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939376 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939376 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1923.840697 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939375 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939375 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
|
||||
|
|
@ -545,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 145214241 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 145214241 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 72548906 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 72548906 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 72548906 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 72548906 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 72548906 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 72548906 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 72548791 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 72548791 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 72548791 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 72548791 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 72548791 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 72548791 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 38810 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 726866500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 726866500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 726866500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 726866500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 726866500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 726866500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 72587716 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 72587716 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 72587716 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 72587716 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 72587716 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 72587716 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 740838000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 740838000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 740838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 740838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 740838000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 740838000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 72587601 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 72587601 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 72587601 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 72587601 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 72587601 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 72587601 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18728.845658 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18728.845658 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18728.845658 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18728.845658 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18728.845658 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19088.843082 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19088.843082 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19088.843082 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19088.843082 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38810
|
|||
system.cpu.icache.demand_mshr_misses::total 38810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 38810 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 38810 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 688057500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 688057500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 688057500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 688057500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 688057500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 688057500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702029000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 702029000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702029000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 702029000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702029000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 702029000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17728.871425 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17728.871425 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17728.871425 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 17728.871425 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18088.868848 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4197.344986 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 4197.348676 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 57958 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.268958 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.814355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200376 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.330255 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.816119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200424 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.332133 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy
|
||||
|
|
@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 7626 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3422 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7626 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214130000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 214130000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 258275500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 258275500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104189000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 104189000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 258275500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 318319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 576594500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 258275500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 318319000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 576594500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214741500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 214741500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257334000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 257334000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104502500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 104502500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 257334000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 319244000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 576578000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 257334000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 319244000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 576578000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.176035 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75199.883109 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77409.259259 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77409.259259 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75606.871230 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75606.871230 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7582
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 185590000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 185590000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223941000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223941000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88101000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88101000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223941000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 273691000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 497632000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223941000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 273691000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 497632000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186201500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186201500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222999500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222999500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88418500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88418500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222999500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 497619500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222999500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274620000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 497619500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 81548 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 38331 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution
|
||||
|
|
@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.369574 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.482692 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 81548 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 51410 63.04% 63.04% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 30138 36.96% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks)
|
||||
|
|
@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7582 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 8866500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 40238250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 40241250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.517235 # Number of seconds simulated
|
||||
sim_ticks 517235407500 # Number of ticks simulated
|
||||
final_tick 517235407500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.517243 # Number of seconds simulated
|
||||
sim_ticks 517243165500 # Number of ticks simulated
|
||||
final_tick 517243165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 785915 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 943520 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1490444540 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 321320 # Number of bytes of host memory used
|
||||
host_seconds 347.03 # Real time elapsed on the host
|
||||
host_inst_rate 702843 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 843789 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1332923086 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 322968 # Number of bytes of host memory used
|
||||
host_seconds 388.05 # Real time elapsed on the host
|
||||
sim_insts 272739286 # Number of instructions simulated
|
||||
sim_ops 327433744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 166912 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 322700 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 522656 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 322700 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 322700 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 322700 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522656 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 322695 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 522648 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 845343 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 322695 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 322695 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 322695 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522648 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845343 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 1034470815 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1034486331 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 272739286 # Number of instructions committed
|
||||
|
|
@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu
|
|||
system.cpu.num_load_insts 85732248 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1034470814.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1034486330.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563503 # Number of branches fetched
|
||||
|
|
@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 327812214 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.445031 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3078.444355 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445031 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.444355 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
|
||||
|
|
@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n
|
|||
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78396000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78396000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78469000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78469000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157423500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 157423500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 235819500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235819500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 235819500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235819500 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 235892500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235892500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 235892500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235892500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48875.311721 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48875.311721 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52685.321716 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52685.321716 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52650.033490 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52650.033490 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52701.630920 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52666.331770 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475
|
|||
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76753000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 76753000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 76826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 154551500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 154551500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 162000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231304500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 231304500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231466500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 231466500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231377500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 231377500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231539500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 231539500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47880.848409 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47880.848409 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51688.156425 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51688.156425 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51689.705226 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51689.705226 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1766.007653 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1766.007280 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007653 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007280 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
|
||||
|
|
@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n
|
|||
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 312483000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 312483000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 312483000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 312483000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 312483000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 312483000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 320168000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 320168000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 320168000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 320168000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 320168000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 320168000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
|
||||
|
|
@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045
|
|||
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20027.110171 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20027.110171 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20027.110171 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20027.110171 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20027.110171 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20519.643658 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20519.643658 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603
|
|||
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 296880000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 296880000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296880000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 296880000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304565000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 304565000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304565000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 304565000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304565000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 304565000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19027.110171 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19027.110171 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19027.110171 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19027.110171 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.764994 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.764139 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.623058 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.427152 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714783 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.622938 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.426609 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714591 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy
|
||||
|
|
@ -588,6 +588,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6465 # Transaction distribution
|
||||
|
|
@ -603,14 +609,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 35209 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.438041 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.496153 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 35209 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 19786 56.20% 56.20% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 15423 43.80% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 35209 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 18602500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.560940 # Nu
|
|||
sim_ticks 560939659000 # Number of ticks simulated
|
||||
final_tick 560939659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 234960 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 234960 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 141903449 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300504 # Number of bytes of host memory used
|
||||
host_seconds 3952.97 # Real time elapsed on the host
|
||||
host_inst_rate 314051 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 314051 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 189670339 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308244 # Number of bytes of host memory used
|
||||
host_seconds 2957.45 # Real time elapsed on the host
|
||||
sim_insts 928789150 # Number of instructions simulated
|
||||
sim_ops 928789150 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -693,6 +693,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1580028 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 787095 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2077 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2077 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723921 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 155535 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 890983 # Transaction distribution
|
||||
|
|
@ -708,15 +714,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 56434176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 259423 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1839451 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.141033 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.348056 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001129 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.033584 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1580028 85.90% 85.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 259423 14.10% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1837374 99.89% 99.89% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2077 0.11% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1839451 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 878866000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.276406 # Nu
|
|||
sim_ticks 276406029500 # Number of ticks simulated
|
||||
final_tick 276406029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 130885 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 130885 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42946592 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301528 # Number of bytes of host memory used
|
||||
host_seconds 6436.04 # Real time elapsed on the host
|
||||
host_inst_rate 172081 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 172081 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56464121 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308248 # Number of bytes of host memory used
|
||||
host_seconds 4895.25 # Real time elapsed on the host
|
||||
sim_insts 842382029 # Number of instructions simulated
|
||||
sim_ops 842382029 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -1000,6 +1000,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1569303 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781752 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1986 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1986 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 718745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 155563 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 885494 # Transaction distribution
|
||||
|
|
@ -1015,15 +1021,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 56091520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 259305 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1828608 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.141805 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.348850 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.032938 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1569303 85.82% 85.82% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 259305 14.18% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1826622 99.89% 99.89% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1986 0.11% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1828608 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 873531500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.286279 # Nu
|
|||
sim_ticks 1286278511500 # Number of ticks simulated
|
||||
final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1355944 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1355944 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1878251411 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303804 # Number of bytes of host memory used
|
||||
host_seconds 684.83 # Real time elapsed on the host
|
||||
host_inst_rate 1389844 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1389844 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1925210162 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305148 # Number of bytes of host memory used
|
||||
host_seconds 668.12 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -484,6 +484,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution
|
||||
|
|
@ -499,15 +505,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258580 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.141585 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.348624 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000941 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.030656 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1567746 85.84% 85.84% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 258580 14.16% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1824608 99.91% 99.91% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1718 0.09% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,69 +1,69 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.542258 # Number of seconds simulated
|
||||
sim_ticks 542257602500 # Number of ticks simulated
|
||||
final_tick 542257602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 542257676500 # Number of ticks simulated
|
||||
final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 121737 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 149875 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 103039759 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317376 # Number of bytes of host memory used
|
||||
host_seconds 5262.61 # Real time elapsed on the host
|
||||
host_inst_rate 169610 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 208813 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 143560034 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325880 # Number of bytes of host memory used
|
||||
host_seconds 3777.22 # Real time elapsed on the host
|
||||
sim_insts 640655085 # Number of instructions simulated
|
||||
sim_ops 788730744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18470528 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18635200 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288602 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291175 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 303679 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 34062276 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 34365954 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 303679 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 303679 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7801222 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7801222 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7801222 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 303679 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 34062276 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42167176 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 291175 # Number of read requests accepted
|
||||
system.physmem.writeReqs 66098 # Number of write requests accepted
|
||||
system.physmem.readBursts 291175 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 18614208 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue
|
||||
system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 18635200 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18282 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18134 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18219 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18172 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18271 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18399 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18135 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18173 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18273 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18400 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18176 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 17991 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 18028 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 17989 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 18030 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18057 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18104 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18195 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18215 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18268 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 18078 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18214 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18267 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18257 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 4171 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 4098 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
|
||||
|
|
@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe
|
|||
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 542257509000 # Total gap between requests
|
||||
system.physmem.totGap 542257582000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 290456 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 377 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
|
|
@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 111041 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 205.695554 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 133.912944 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 256.637901 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 45880 41.32% 41.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43577 39.24% 80.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 9434 8.50% 89.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1633 1.47% 90.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 691 0.62% 91.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 667 0.60% 91.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 550 0.50% 92.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8094 7.29% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 111041 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 48.509833 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 34.246439 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 506.588678 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
|
|
@ -224,12 +224,12 @@ system.physmem.wrPerTurnAround::17 1 0.02% 77.65% # Wr
|
|||
system.physmem.wrPerTurnAround::18 897 22.33% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 2871354000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8324735250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1454235000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 9872.39 # Average queueing delay per DRAM burst
|
||||
system.physmem.totQLat 2868100000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28622.39 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -240,47 +240,47 @@ system.physmem.busUtilRead 0.27 # Da
|
|||
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 26.15 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 194229 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 51633 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 66.78 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 78.12 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1517767.95 # Average gap between requests
|
||||
system.physmem.pageHitRate 68.88 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 420124320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 229234500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1135836000 # Energy for read commands per rank (pJ)
|
||||
system.physmem.readRowHits 194250 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 51642 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1517768.15 # Average gap between requests
|
||||
system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 215518320 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 107502461415 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 231049769250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 375970079325 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 693.351550 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 383670371250 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 693.324021 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 18106920000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 140473012000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 419247360 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 228756000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1132271400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 212615280 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 108055650690 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 230564511000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 376030187250 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 693.462409 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 382864555750 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 693.447269 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 18106920000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 141281958750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 154805772 # Number of BP lookups
|
||||
system.cpu.branchPred.lookups 154805770 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 105138293 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 90693369 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 91.615651 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 19277594 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
|
|
@ -401,24 +401,24 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 1084515205 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1084515353 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 640655085 # Number of instructions committed
|
||||
system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 23906785 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.692822 # CPI: cycles per instruction
|
||||
system.cpu.cpi 1.692823 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.590729 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1025899032 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 58616173 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 778339 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4092.484062 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484062 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -454,14 +454,14 @@ system.cpu.dcache.demand_misses::cpu.data 851588 # n
|
|||
system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 851729 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762813000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 24762813000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105718500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10105718500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 34868531500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 34868531500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 34868531500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 34868531500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -486,14 +486,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34687.835142 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34687.835142 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73382.991315 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73382.991315 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40945.306298 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 40945.306298 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40938.527982 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 40938.527982 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -522,16 +522,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782296
|
|||
system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24034165000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24034165000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067912500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067912500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1855000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1855000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29102077500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 29102077500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29103932500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 29103932500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -542,24 +542,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33709.735558 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33709.735558 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73106.841984 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73106.841984 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37200.851724 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37200.851724 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37196.613776 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37196.613776 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 23591 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1713.095623 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 291576498 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11505.662458 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095623 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
|
||||
|
|
@ -567,44 +567,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 58
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 583229024 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 583229024 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 291576498 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 291576498 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 291576498 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 291576498 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 291576498 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 291576498 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 291576499 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 25343 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 25343 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 25343 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 25343 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 25343 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 25343 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 498098000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 498098000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 498098000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 498098000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 498098000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 498098000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 291601841 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 291601841 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 291601841 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 291601841 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 291601841 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 291601841 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19654.263505 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19654.263505 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19654.263505 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19654.263505 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19701.317918 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -619,37 +619,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25343
|
|||
system.cpu.icache.demand_mshr_misses::total 25343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 25343 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 25343 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 472756000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 472756000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 472756000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 472756000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 472756000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 472756000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473948500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 473948500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473948500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 473948500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473948500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 473948500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18654.302963 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18654.302963 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18654.302963 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18654.302963 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 258395 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32574.709364 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 32574.709394 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1245326 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291139 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.277428 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156166 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.700113 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29894.853085 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156414 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.726448 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.079015 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002768 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.912319 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002738 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.912348 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994101 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
||||
|
|
@ -686,18 +686,18 @@ system.cpu.l2cache.demand_misses::total 291208 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288630 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291208 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4930001500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4930001500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195708000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 195708000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17815243000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17815243000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 195708000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22745244500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22940952500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 195708000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22745244500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22940952500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929880500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4929880500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195624000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 195624000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17812302500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17812302500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 195624000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22742183000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22937807000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 195624000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22742183000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22937807000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 88920 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 88920 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -724,18 +724,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.360505 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101724 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368887 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.360505 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74594.142924 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74594.142924 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75914.662529 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75914.662529 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80054.475845 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80054.475845 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75914.662529 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78804.159304 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 78778.579229 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75914.662529 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78804.159304 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 78778.579229 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -746,69 +746,75 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 28 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 28 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 376 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 376 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2574 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2574 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222511 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222511 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288602 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2573 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2573 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222512 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222512 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2573 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291176 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288602 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2573 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288603 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291176 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4269091500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4269091500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169723000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169723000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15588307500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15588307500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169723000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19857399000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20027122000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169723000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19857399000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20027122000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268970500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268970500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169583000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169583000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15585424500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15585424500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169583000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19854395000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20023978000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169583000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19854395000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20023978000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101567 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312028 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312028 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101527 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312029 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312029 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64594.142924 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64594.142924 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65937.451437 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65937.451437 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70056.345529 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70056.345529 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3351 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 155018 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 901956 # Transaction distribution
|
||||
|
|
@ -824,21 +830,21 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 57388608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258395 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1868103 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1609708 86.17% 86.17% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 258395 13.83% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1868103 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 893774000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 38014996 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1173666472 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 225084 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66098 # Transaction distribution
|
||||
|
|
@ -861,9 +867,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 547917 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 917948500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1554418250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.043722 # Number of seconds simulated
|
||||
sim_ticks 1043722398500 # Number of ticks simulated
|
||||
final_tick 1043722398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.043724 # Number of seconds simulated
|
||||
sim_ticks 1043723537500 # Number of ticks simulated
|
||||
final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 921530 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1132156 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1504334297 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 320916 # Number of bytes of host memory used
|
||||
host_seconds 693.81 # Real time elapsed on the host
|
||||
host_inst_rate 832063 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1358287943 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323064 # Number of bytes of host memory used
|
||||
host_seconds 768.41 # Real time elapsed on the host
|
||||
sim_insts 639366787 # Number of instructions simulated
|
||||
sim_ops 785501035 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -26,16 +26,16 @@ system.physmem.num_reads::total 290359 # Nu
|
|||
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 17696046 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 17804520 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4053062 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4053062 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4053062 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17696046 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21857582 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 2087444797 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 2087447075 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 639366787 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu
|
|||
system.cpu.num_load_insts 252240938 # Number of load instructions
|
||||
system.cpu.num_store_insts 128980497 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2087444796.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 137364860 # Number of branches fetched
|
||||
|
|
@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 788730744 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 778046 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4093.640641 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 996416500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640641 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n
|
|||
system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 782143 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18609964000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18609964000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22287133000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22287133000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22287133000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22287133000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26112.614199 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26112.614199 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28500.024297 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28500.024297 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28494.959362 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28494.959362 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003
|
|||
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17897244000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17897244000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21505090000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 21505090000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21506842000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 21506842000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25112.594713 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25112.594713 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27500.009591 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27500.009591 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27497.362372 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27497.362372 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 8769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1391.464534 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464534 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
|
||||
|
|
@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n
|
|||
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 10208 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207153000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 207153000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 207153000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 207153000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 207153000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 207153000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses
|
||||
|
|
@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016
|
|||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20293.201411 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20293.201411 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20293.201411 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20293.201411 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20293.201411 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -419,34 +419,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208
|
|||
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 196945000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 196945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 196945000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19293.201411 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19293.201411 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19293.201411 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19293.201411 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 257579 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32626.732272 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2506.606006 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754528 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.371738 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy
|
||||
|
|
@ -490,14 +490,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000
|
|||
system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681386500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681386500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15151332500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15244353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15151332500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15244353500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -528,14 +528,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767
|
|||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.321366 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.321366 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.742670 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.238782 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.742670 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -564,14 +564,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000
|
|||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456416500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456416500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265432500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12340763500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265432500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12340763500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -590,15 +590,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767
|
|||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.321366 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.321366 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.238782 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.742670 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution
|
||||
|
|
@ -614,14 +620,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 257579 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.140237 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.347233 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1579165 85.98% 85.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 257579 14.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.059549 # Nu
|
|||
sim_ticks 59549031000 # Number of ticks simulated
|
||||
final_tick 59549031000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 231283 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 231283 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 155732739 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 299636 # Number of bytes of host memory used
|
||||
host_seconds 382.38 # Real time elapsed on the host
|
||||
host_inst_rate 320796 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 320796 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 216005540 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 307628 # Number of bytes of host memory used
|
||||
host_seconds 275.68 # Real time elapsed on the host
|
||||
sim_insts 88438073 # Number of instructions simulated
|
||||
sim_ops 88438073 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -696,6 +696,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 713379 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 353617 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 216203 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 282838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 203224 # Transaction distribution
|
||||
|
|
@ -711,15 +717,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 33805696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 132445 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 845824 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.156587 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.363411 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004759 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.068819 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 713379 84.34% 84.34% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 132445 15.66% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 841799 99.52% 99.52% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 4025 0.48% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 845824 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 525142500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.022357 # Nu
|
|||
sim_ticks 22356634500 # Number of ticks simulated
|
||||
final_tick 22356634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 154709 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154709 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43456447 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300660 # Number of bytes of host memory used
|
||||
host_seconds 514.46 # Real time elapsed on the host
|
||||
host_inst_rate 213363 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 213363 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59931818 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308400 # Number of bytes of host memory used
|
||||
host_seconds 373.03 # Real time elapsed on the host
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_ops 79591756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -994,6 +994,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 591735 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 292795 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 155540 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 283136 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 141723 # Transaction distribution
|
||||
|
|
@ -1009,15 +1015,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 29934528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 132064 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 723799 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.182459 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.386223 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.005561 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.074364 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 591735 81.75% 81.75% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 132064 18.25% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 719774 99.44% 99.44% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 4025 0.56% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 723799 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 464655500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.056986 # Number of seconds simulated
|
||||
sim_ticks 56986224500 # Number of ticks simulated
|
||||
final_tick 56986224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.056991 # Number of seconds simulated
|
||||
sim_ticks 56991022500 # Number of ticks simulated
|
||||
final_tick 56991022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 135704 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 173546 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 109049636 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317176 # Number of bytes of host memory used
|
||||
host_seconds 522.57 # Real time elapsed on the host
|
||||
host_inst_rate 186679 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 238735 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 150024942 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325676 # Number of bytes of host memory used
|
||||
host_seconds 379.88 # Real time elapsed on the host
|
||||
sim_insts 70915128 # Number of instructions simulated
|
||||
sim_ops 90690084 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,24 +25,24 @@ system.physmem.num_reads::cpu.data 123811 # Nu
|
|||
system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 5592931 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 139049464 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 144642395 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 5592931 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 5592931 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 96761069 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 96761069 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 96761069 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 5592931 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 139049464 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 241403464 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 5592460 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 139037758 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 144630218 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 5592460 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 5592460 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 96752923 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 96752923 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 96752923 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 5592460 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 139037758 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 241383141 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 128791 # Number of read requests accepted
|
||||
system.physmem.writeReqs 86157 # Number of write requests accepted
|
||||
system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 5512000 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesWritten 5512640 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
|
||||
|
|
@ -66,15 +66,15 @@ system.physmem.perBankRdBursts::14 7975 # Pe
|
|||
system.physmem.perBankRdBursts::15 7995 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 5393 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 5541 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 5463 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 5328 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 5464 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 5326 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 5352 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 5545 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 5246 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 5547 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 5252 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 5180 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 5155 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 5101 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 5289 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 5292 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 5270 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 5531 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
|
||||
|
|
@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 5703 # Pe
|
|||
system.physmem.perBankWrBursts::15 5431 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 56986193500 # Total gap between requests
|
||||
system.physmem.totGap 56990990500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 86157 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 116559 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 12202 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 116650 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 12110 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 656 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4080 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 5286 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 5311 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 5306 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 5318 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 5318 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 5323 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 5350 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 5376 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5428 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 5451 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 5897 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 5469 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 649 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4071 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 5170 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 5285 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 5306 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 5310 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 5310 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 5336 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 5367 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5452 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 5431 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 5478 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 5464 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
||||
|
|
@ -193,98 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 38656 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 355.735099 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 216.399320 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 335.915140 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 12161 31.46% 31.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8166 21.12% 52.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4096 10.60% 63.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2818 7.29% 70.47% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2687 6.95% 77.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1672 4.33% 81.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1300 3.36% 85.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1153 2.98% 88.09% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 4603 11.91% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 38656 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5291 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 24.313362 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 352.121472 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 5289 99.96% 99.96% # Reads before turning the bus around for writes
|
||||
system.physmem.bytesPerActivate::samples 38662 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 355.683203 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 216.343519 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 336.125731 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 12148 31.42% 31.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 8177 21.15% 52.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4090 10.58% 63.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2852 7.38% 70.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2693 6.97% 77.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 1623 4.20% 81.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 1296 3.35% 85.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1161 3.00% 88.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 4622 11.95% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 38662 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 24.322124 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 352.056892 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 5291 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 5291 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.277641 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.260577 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.779844 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 4640 87.70% 87.70% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 6 0.11% 87.81% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 513 9.70% 97.51% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 107 2.02% 99.53% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 18 0.34% 99.87% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 4 0.08% 99.94% # Writes before turning the bus around for reads
|
||||
system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.273380 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.256688 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.768255 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 4654 87.93% 87.93% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 4 0.08% 88.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 500 9.45% 97.45% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 109 2.06% 99.51% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 18 0.34% 99.85% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 5 0.09% 99.94% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5291 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1688662500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 4103362500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 1683428000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 4098128000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 13112.36 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 13071.72 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 31862.36 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 144.63 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 31821.72 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 144.62 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 144.64 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 144.63 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 96.75 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 1.89 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 112105 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 64137 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 74.44 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 265116.18 # Average gap between requests
|
||||
system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 112096 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 64153 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.04 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 74.46 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 265138.50 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 512194800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 278951040 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 11693696490 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 23930394000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 40371922185 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 708.527477 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 39682710000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1902680000 # Time in different power states
|
||||
system.physmem_0.actEnergy 151963560 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 82916625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 512397600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 278957520 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 11726025750 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 23906742000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 40381153695 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 708.591931 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 39643767750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1902940000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 15394661250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 15441187500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 140086800 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 76436250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 491673000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 140313600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 76560000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 491751000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 11090732535 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 24459309750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 40259019375 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 706.546032 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 40563908250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1902680000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 11059172775 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 24491665500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 40260752475 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 706.479908 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 40617302250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1902940000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14513554250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14467595250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 14800511 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9905691 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 381680 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 9439152 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6732150 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 14800541 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 9905717 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 381681 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 9438549 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 6732145 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 71.321555 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1714112 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 71.326059 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1714124 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
|
|
@ -404,67 +404,67 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 113972449 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 113982045 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70915128 # Number of instructions committed
|
||||
system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1144886 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 1144890 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.607167 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.622213 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 95596263 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 18376186 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.607302 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.622161 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 95587829 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 18394216 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 156435 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4067.140403 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42624247 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4067.142814 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42624094 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 265.520348 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 822680500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.140403 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 265.519395 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.142814 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2936 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1110 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 86016733 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 86016733 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22866807 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22866807 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19642189 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19642189 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 83413 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 83413 # number of SoftPFReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 86016729 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 86016729 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22866654 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22866654 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19642187 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19642187 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 83415 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 83415 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 42508996 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42508996 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 42592409 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42592409 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 51550 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 51550 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 207712 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 207712 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 44592 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 44592 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 259262 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 259262 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 303854 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 303854 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489104500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1489104500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16802314000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 16802314000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 18291418500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 18291418500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 18291418500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 18291418500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_hits::cpu.data 42508841 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42508841 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 42592256 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42592256 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 51701 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 51701 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 207714 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 207714 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 259415 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 259415 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 304005 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 304005 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1492164500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1492164500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16804934500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 16804934500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 18297099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 18297099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 18297099000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 18297099000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22918355 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22918355 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses)
|
||||
|
|
@ -473,28 +473,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 42768256 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 42768256 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 42896261 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 42896261 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002256 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002256 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348361 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.348361 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28886.605238 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28886.605238 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80892.360576 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 80892.360576 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70551.868380 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 70551.868380 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60198.050709 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60198.050709 # average overall miss latency
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348346 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.348346 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28861.424344 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28861.424344 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80904.197599 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 80904.197599 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70532.155041 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 70532.155041 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60186.835743 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60186.835743 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -505,14 +505,14 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 128400 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22032 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 22032 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100684 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 100684 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 122716 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 122716 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 122716 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 122716 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22183 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 22183 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100686 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 100686 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 122869 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 122869 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 122869 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 122869 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses
|
||||
|
|
@ -523,16 +523,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136546
|
|||
system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 574723500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 574723500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8485443000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8485443000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719503000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719503000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9060166500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9060166500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779669500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10779669500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 578376000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8484284000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8484284000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1716349500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1716349500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9062660000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9062660000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779009500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10779009500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -543,70 +543,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19470.272376 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19470.272376 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79282.458796 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79282.458796 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71690.765061 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71690.765061 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66352.485609 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66352.485609 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67150.080047 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67150.080047 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19594.010434 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19594.010434 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79271.629854 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79271.629854 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71559.287054 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71559.287054 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66370.746855 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66370.746855 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67145.968691 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67145.968691 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 42865 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1852.538301 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 24941041 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 44907 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 555.393168 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 42866 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1852.547846 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 24941084 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 44908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 555.381758 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1852.538301 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.904560 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.904560 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1852.547846 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.904564 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.904564 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 50016805 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 50016805 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24941041 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24941041 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24941041 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24941041 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24941041 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24941041 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 44908 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 44908 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 44908 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 44908 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 44908 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 44908 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 926324500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 926324500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 926324500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 926324500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 926324500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 926324500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24985949 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24985949 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24985949 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24985949 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24985949 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24985949 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 50016894 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 50016894 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 24941084 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 24941084 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 24941084 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 24941084 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 24941084 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 24941084 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 44909 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 44909 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 44909 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 44909 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 44909 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 44909 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 929470000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 929470000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 929470000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 929470000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 929470000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 929470000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 24985993 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 24985993 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 24985993 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 24985993 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 24985993 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 24985993 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20627.159971 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20627.159971 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20627.159971 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20627.159971 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20627.159971 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20696.742301 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20696.742301 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20696.742301 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20696.742301 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -615,67 +615,67 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44908 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 44908 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 44908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 44908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 44908 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 44908 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 881417500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 881417500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 881417500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 881417500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 881417500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 881417500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44909 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 44909 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 44909 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 44909 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 44909 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 44909 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 884562000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 884562000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 884562000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 884562000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 884562000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 884562000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19627.182239 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19627.182239 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19627.182239 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19627.182239 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19696.764568 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19696.764568 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19696.764568 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19696.764568 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 95654 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29860.809495 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 161643 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 29860.905704 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 161645 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 126772 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.275069 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.275084 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26579.265460 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.835593 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.708442 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.811135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049464 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.050681 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.911280 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 26579.253739 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1620.855600 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1660.796365 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.811134 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049465 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.050683 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.911283 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1806 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12714 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15870 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1809 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12704 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15880 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 604 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3409200 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3409200 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 3409216 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3409216 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 128400 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 128400 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39917 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 39917 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 39918 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 39918 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31903 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 31903 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 39917 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 39918 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 36655 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 76572 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 39917 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 76573 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 39918 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 36655 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 76572 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 76573 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4991 # number of ReadCleanReq misses
|
||||
|
|
@ -688,56 +688,56 @@ system.cpu.l2cache.demand_misses::total 128867 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 4991 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 123876 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 128867 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8274960000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8274960000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394876000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 394876000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1878573500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1878573500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 394876000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10153533500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 10548409500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 394876000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10153533500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 10548409500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8273802000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 8273802000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 394300500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 394300500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1875098000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1875098000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 394300500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10148900000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 10543200500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 394300500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10148900000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 10543200500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 128400 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 128400 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44908 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 44908 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44909 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 44909 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 44908 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 44909 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 160531 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 205439 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 44908 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 205440 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 44909 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 160531 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 205439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 205440 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111138 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111138 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111136 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111136 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403716 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403716 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111138 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111136 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.627276 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111138 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.627273 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111136 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.627276 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80908.130940 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80908.130940 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79117.611701 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79117.611701 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86970.995370 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86970.995370 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81855.009428 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79117.611701 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81965.299977 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81855.009428 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.627273 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80896.808635 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80896.808635 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79002.304147 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79002.304147 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86810.092593 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86810.092593 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 81814.587908 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79002.304147 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81927.895638 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 81814.587908 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -772,75 +772,81 @@ system.cpu.l2cache.demand_mshr_misses::total 128792
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7252200000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7252200000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 344388000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 344388000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658643500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658643500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 344388000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8910843500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9255231500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 344388000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8910843500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9255231500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7251042000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7251042000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 343845500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 343845500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655136500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655136500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 343845500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8906178500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 9250024000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 343845500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8906178500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 9250024000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110916 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110913 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.626911 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.626908 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.626911 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70908.130940 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70908.130940 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69140.333266 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69140.333266 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77020.826561 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77020.826561 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.626908 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70896.808635 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70896.808635 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69031.419394 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69031.419394 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76857.975389 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76857.975389 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 98410 # Transaction distribution
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 404741 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 199337 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 98411 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 72583 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 72584 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 44908 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 44909 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129101 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129104 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 602363 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 602366 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 21365632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 21365696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 95654 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 500393 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.191158 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.393213 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 500395 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.038076 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.191682 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 404739 80.88% 80.88% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 95654 19.12% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 481371 96.20% 96.20% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 18995 3.80% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 500393 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 330769500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 500395 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 330770500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 67366488 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 67369485 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 240828935 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 240829933 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 26515 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 86157 # Transaction distribution
|
||||
|
|
@ -863,9 +869,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 222458 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 591536000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 591531500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 679701000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 679686000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 1.208801 # Nu
|
|||
sim_ticks 1208800797500 # Number of ticks simulated
|
||||
final_tick 1208800797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 239332 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 239332 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 158403619 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291552 # Number of bytes of host memory used
|
||||
host_seconds 7631.14 # Real time elapsed on the host
|
||||
host_inst_rate 309355 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 309355 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 204748768 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 299532 # Number of bytes of host memory used
|
||||
host_seconds 5903.82 # Real time elapsed on the host
|
||||
sim_insts 1826378509 # Number of instructions simulated
|
||||
sim_ops 1826378509 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -703,6 +703,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18249028 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121989 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1267 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1267 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7239716 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4708732 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6334139 # Transaction distribution
|
||||
|
|
@ -718,15 +724,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 820072320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1920882 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20169910 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.095235 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.293539 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.007925 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 18249028 90.48% 90.48% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1920882 9.52% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20168643 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1267 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20169910 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12811105000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.669557 # Nu
|
|||
sim_ticks 669556582000 # Number of ticks simulated
|
||||
final_tick 669556582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 125035 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 125035 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48223337 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292576 # Number of bytes of host memory used
|
||||
host_seconds 13884.49 # Real time elapsed on the host
|
||||
host_inst_rate 160543 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 160543 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61918292 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 299292 # Number of bytes of host memory used
|
||||
host_seconds 10813.55 # Real time elapsed on the host
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_ops 1736043781 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -1026,6 +1026,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18419494 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207224 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1279 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7333064 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4752054 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6384201 # Transaction distribution
|
||||
|
|
@ -1041,15 +1047,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 828161152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1929031 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20348525 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.094800 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.292938 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.007928 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 18419494 90.52% 90.52% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1929031 9.48% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20347246 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1279 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20348525 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12937495000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.623057 # Nu
|
|||
sim_ticks 2623057163500 # Number of ticks simulated
|
||||
final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1251674 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1251674 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1804181213 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294596 # Number of bytes of host memory used
|
||||
host_seconds 1453.88 # Real time elapsed on the host
|
||||
host_inst_rate 1405944 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1405944 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2026548224 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297224 # Number of bytes of host memory used
|
||||
host_seconds 1294.35 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -478,6 +478,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution
|
||||
|
|
@ -493,15 +499,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919524 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.095310 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.293643 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000056 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.007464 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 18220175 90.47% 90.47% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1919524 9.53% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20138577 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,69 +1,69 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.116876 # Number of seconds simulated
|
||||
sim_ticks 1116876142500 # Number of ticks simulated
|
||||
final_tick 1116876142500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.116866 # Number of seconds simulated
|
||||
sim_ticks 1116865669500 # Number of ticks simulated
|
||||
final_tick 1116865669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 161785 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 174299 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 116987267 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309392 # Number of bytes of host memory used
|
||||
host_seconds 9546.99 # Real time elapsed on the host
|
||||
host_inst_rate 226280 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 243783 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 163622006 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317884 # Number of bytes of host memory used
|
||||
host_seconds 6825.89 # Real time elapsed on the host
|
||||
sim_insts 1544563088 # Number of instructions simulated
|
||||
sim_ops 1664032481 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 130931520 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 130931456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 67207936 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 67207936 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2045805 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1050124 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1050124 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 45097 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 117230116 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 117275213 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 45097 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 45097 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 60174923 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 60174923 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 60174923 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 45097 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 117230116 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 177450137 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 2046592 # Number of read requests accepted
|
||||
system.physmem.writeReqs 1050124 # Number of write requests accepted
|
||||
system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 1050124 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 130897216 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 84672 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 67206464 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 67207936 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 1323 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.num_reads::cpu.data 2045804 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 45098 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 117231158 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 45098 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 45098 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 45098 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 117231158 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 2046591 # Number of read requests accepted
|
||||
system.physmem.writeReqs 1050123 # Number of write requests accepted
|
||||
system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 130897024 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 84800 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 1325 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 127284 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 124662 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 121597 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::0 127282 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 124660 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 121599 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 123658 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 122617 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 122616 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 122675 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 123246 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 123759 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 123764 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 131397 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 133511 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 132080 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 133309 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 133252 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 133368 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 129308 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 129546 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 133514 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 132084 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 133304 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 133248 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 133365 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 129309 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 129545 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 66136 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 64410 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 62576 # Per bank write bursts
|
||||
|
|
@ -71,34 +71,34 @@ system.physmem.perBankWrBursts::3 63006 # Pe
|
|||
system.physmem.perBankWrBursts::4 63000 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 63100 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 64443 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 65435 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 67311 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 67795 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 67548 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 67883 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 67328 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 65436 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 67310 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 67797 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 67549 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 67882 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 67326 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 67793 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 66483 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 66482 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 65854 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 1116876049000 # Total gap between requests
|
||||
system.physmem.totGap 1116865575000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 2046592 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 2046591 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 1050124 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 1916546 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 128705 # What read queue length does an incoming req see
|
||||
system.physmem.writePktSize::6 1050123 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 1916631 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 128617 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 32789 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 34054 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 56903 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 61212 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 61641 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 61593 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 61666 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 61641 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 61698 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 61718 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 61664 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 62178 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 62548 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 62056 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 62535 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 61302 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 61133 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 74 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 32784 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 34018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 56910 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 61213 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 61610 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 61708 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 61596 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 61643 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 61643 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 61703 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 61754 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 61670 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 62179 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 62537 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 62061 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 62560 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 61129 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 78 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
|
||||
|
|
@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1910492 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 103.692259 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 81.833601 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 125.494474 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 1485528 77.76% 77.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 305524 15.99% 93.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 52470 2.75% 96.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 20903 1.09% 97.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 13406 0.70% 98.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 7575 0.40% 98.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 5481 0.29% 98.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 5100 0.27% 99.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 14505 0.76% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1910492 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 61132 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 33.413630 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 160.636391 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 61087 99.93% 99.93% # Reads before turning the bus around for writes
|
||||
system.physmem.bytesPerActivate::samples 1910448 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 103.693777 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 81.830782 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 125.503425 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 1485607 77.76% 77.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 305343 15.98% 93.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 20883 1.09% 97.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 13429 0.70% 98.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 7609 0.40% 98.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 5497 0.29% 98.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 5095 0.27% 99.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 14491 0.76% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1910448 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 61128 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 33.415767 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 160.633753 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 61083 99.93% 99.93% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
|
||||
|
|
@ -220,76 +220,76 @@ system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% #
|
|||
system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 61132 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 61132 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 17.177599 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 17.142637 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 1.096979 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 26963 44.11% 44.11% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 1122 1.84% 45.94% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 28754 47.04% 92.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 3885 6.36% 99.33% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 352 0.58% 99.91% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 46 0.08% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.rdPerTurnAround::total 61128 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 61128 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 17.178707 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 17.143614 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 1.099153 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 26983 44.14% 44.14% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 1095 1.79% 45.93% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 28688 46.93% 92.86% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 3942 6.45% 99.31% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::20 361 0.59% 99.90% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 61132 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 38139021250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 76487815000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 10226345000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 18647.44 # Average queueing delay per DRAM burst
|
||||
system.physmem.wrPerTurnAround::total 61128 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 38113681000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 76462418500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 10226330000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 18635.07 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 37397.44 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 37385.07 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 60.17 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 1.39 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 773003 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 411872 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 37.79 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 360664.67 # Average gap between requests
|
||||
system.physmem.readRowHits 773150 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 411758 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 39.21 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 360661.52 # Average gap between requests
|
||||
system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 7041119400 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3841880625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 7718053200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 420554384415 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 301217964750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 816640712790 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 731.183278 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 498392390000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 37294920000 # Time in different power states
|
||||
system.physmem_0.actEnergy 7040439000 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3841509375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 7717788000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 420410239110 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 301335056250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 816611331495 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 731.167175 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 498591665750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 581188236250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 580976292250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 7402200120 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 4038898875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 8234990400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 3486207600 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 429475728015 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 293392224750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 818979113280 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 733.276976 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 485326311500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 37294920000 # Time in different power states
|
||||
system.physmem_1.actEnergy 7402532760 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 4039080375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 8234920200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 429557025690 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 293311559250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 818979159315 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 733.287251 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 485194866750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 594254742500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 594372992750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 239639069 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 186342280 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 239639075 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 186342287 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 130646098 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 122079384 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 130646101 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 122079387 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target.
|
||||
|
|
@ -412,68 +412,68 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 2233752285 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 2233731339 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1544563088 # Number of instructions committed
|
||||
system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 41470092 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 41470082 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.446203 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.691466 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1834122948 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 399629337 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.446190 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.691472 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1834124286 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 399607053 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 9221039 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4085.616333 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 624218905 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4085.616235 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 624218894 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 67.665016 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 67.665015 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616333 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616235 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1276841915 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1276841915 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 453887721 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 453887721 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170331061 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 170331061 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 1276841917 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1276841917 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 453887722 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 453887722 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170331049 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 170331049 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 624218782 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 624218782 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 624218783 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 624218783 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 624218771 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 624218771 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 624218772 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 624218772 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2254986 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2254986 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2254998 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2254998 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9589483 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9589483 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9589485 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9589485 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 190949826000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 109060330000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 300010156000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 300010156000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 300010156000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 300010156000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 461222218 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 461222218 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 9589495 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9589495 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9589497 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9589497 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 190935436500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 109060065500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 299995502000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 299995502000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 299995502000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 299995502000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 461222219 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 461222219 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses)
|
||||
|
|
@ -482,10 +482,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 633808265 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 633808265 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 633808268 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 633808268 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 633808266 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 633808266 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 633808269 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 633808269 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses
|
||||
|
|
@ -496,14 +496,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015130
|
|||
system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31285.331649 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31285.325124 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31283.764369 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31283.757845 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -516,12 +516,12 @@ system.cpu.dcache.writebacks::writebacks 3684564 # nu
|
|||
system.cpu.dcache.writebacks::total 3684564 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364134 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 364134 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 364349 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 364349 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 364349 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 364349 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364146 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 364146 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 364361 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 364361 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 364361 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 364361 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses
|
||||
|
|
@ -532,16 +532,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9225134
|
|||
system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183609818500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 183609818500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84766639000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84766639000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84757207500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84757207500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268376457500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 268376457500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268376531500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 268376531500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 268352592000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 268352666000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -552,24 +552,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25034.463973 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25034.463973 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44829.864527 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44829.864527 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.876335 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.876335 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.881203 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.881203 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 29 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 661.386126 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 465281345 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 661.385274 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 465281545 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 567416.274390 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 567416.518293 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 661.386126 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 661.385274 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id
|
||||
|
|
@ -577,44 +577,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 930565150 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 930565150 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 465281345 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 465281345 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 465281345 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 465281345 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 465281345 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 465281345 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 930565550 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 930565550 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 465281545 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 465281545 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 465281545 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 465281545 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 465281545 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 465281545 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 820 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62363500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 62363500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 62363500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 62363500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 62363500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 62363500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 465282165 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 465282165 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 465282165 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 465282165 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 465282165 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 465282165 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 62174000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 62174000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 62174000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 62174000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 62174000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 62174000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 465282365 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 465282365 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 465282365 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 465282365 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 465282365 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 465282365 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.048780 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76053.048780 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76053.048780 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76053.048780 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75821.951220 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75821.951220 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -629,35 +629,35 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 820
|
|||
system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61543500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 61543500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61543500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 61543500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61543500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 61543500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61354000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 61354000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61354000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 61354000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61354000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 61354000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 2013891 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31258.308104 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14509189 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2043666 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.099589 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 2013890 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31258.297879 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14509190 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2043665 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.099593 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14832.412998 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.306662 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.452649 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 14832.420356 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588666 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.288857 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.452650 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000811 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.500467 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy
|
||||
|
|
@ -668,46 +668,46 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 151497950 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 151497950 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 151497949 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 151497949 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3684564 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3684564 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1089696 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1089696 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1089697 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1089697 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7179326 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7179358 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7179327 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7179359 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7179326 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7179358 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 801156 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 801156 # number of ReadExReq misses
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7179327 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7179359 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 801155 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 801155 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 788 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 788 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244653 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1244653 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2045809 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 2046597 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 2045808 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2045809 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 2046597 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70430633500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 70430633500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59976000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 59976000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108661637000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 108661637000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 59976000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 179092270500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 179152246500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 59976000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 179092270500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 179152246500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2045808 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70421216500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 70421216500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59756500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 59756500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108645799000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 108645799000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 59756500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 179067015500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 179126772000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 59756500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 179067015500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 179126772000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3684564 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3684564 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890852 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -734,18 +734,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.221830 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87911.260104 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87911.260104 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76111.675127 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76111.675127 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87302.755869 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87302.755869 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 87536.650596 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 87536.650596 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87899.615555 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87899.615555 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75833.121827 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75833.121827 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87290.031037 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87290.031037 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 87524.246114 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 87524.246114 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -754,8 +754,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1050124 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1050124 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1050123 # number of writebacks
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits
|
||||
|
|
@ -768,30 +768,30 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 4
|
|||
system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801156 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 801156 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801155 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 801155 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 787 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 787 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2045805 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 2045804 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2045805 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62419073500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62419073500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52090500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52090500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96214883500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96214883500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52090500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158633957000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 158686047500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52090500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158633957000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 158686047500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2045804 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62409666500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62409666500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51871000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51871000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96199045500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96199045500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51871000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158608712000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 158660583000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51871000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158608712000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 158660583000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -806,21 +806,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18447023 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221080 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4734688 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4734687 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution
|
||||
|
|
@ -832,18 +838,18 @@ system.cpu.toL2Bus.pkt_count::total 27671384 # Pa
|
|||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 2013891 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20460914 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.098426 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.297890 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoops 2013890 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20460913 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000220 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.014837 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 18447023 90.16% 90.16% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 2013891 9.84% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20456426 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 4481 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20460914 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20460913 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks)
|
||||
|
|
@ -851,29 +857,29 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L
|
|||
system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1245436 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1050124 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1050123 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 962723 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 801156 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 801156 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 801155 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 801155 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 198189824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106028 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6106028 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 4059439 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 4059437 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 4059437 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 4059439 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8663029500 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 4059437 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8662977500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 11191724000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 11191643250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.363367 # Number of seconds simulated
|
||||
sim_ticks 2363367211500 # Number of ticks simulated
|
||||
final_tick 2363367211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.363368 # Number of seconds simulated
|
||||
sim_ticks 2363368369500 # Number of ticks simulated
|
||||
final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1091670 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1176427 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1676685643 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 312924 # Number of bytes of host memory used
|
||||
host_seconds 1409.55 # Real time elapsed on the host
|
||||
host_inst_rate 1008024 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1548215415 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 315828 # Number of bytes of host memory used
|
||||
host_seconds 1526.51 # Real time elapsed on the host
|
||||
sim_insts 1538759602 # Number of instructions simulated
|
||||
sim_ops 1658228915 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -26,16 +26,16 @@ system.physmem.num_reads::total 1951712 # Nu
|
|||
system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52835693 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52852374 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27652126 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27652126 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27652126 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52835693 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80504500 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 4726734423 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4726736739 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1538759602 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu
|
|||
system.cpu.num_load_insts 458306334 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4726734422.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462427 # Number of branches fetched
|
||||
|
|
@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032481 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.732137 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25164659500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732137 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n
|
|||
system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143051795500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143051795500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200460716500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200460716500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200460716500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200460716500 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526
|
|||
system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.580818 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.580818 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.831971 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21991.831971 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.829559 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21991.829559 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235
|
|||
system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135825709500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 135825709500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191345481500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191345481500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191345535500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191345535500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.580818 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.580818 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.831971 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.831971 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.835593 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.835593 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 515.003161 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.003161 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
|
||||
|
|
@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n
|
|||
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 638 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34212000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34212000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34212000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34212000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34212000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34212000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
|
||||
|
|
@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53623.824451 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53623.824451 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53623.824451 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53623.824451 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53623.824451 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -411,34 +411,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638
|
|||
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33574000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 33574000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33574000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 33574000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33574000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 33574000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52623.824451 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52623.824451 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52623.824451 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52623.824451 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1919018 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31008.198929 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14386233 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948786 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.382151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 150067845000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15515.969324 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734669 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494937 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.473510 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.472061 # Average percentage of cache occupancy
|
||||
|
|
@ -482,14 +482,14 @@ system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41062370000
|
|||
system.cpu.l2cache.ReadExReq_miss_latency::total 41062370000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 32383000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 32383000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386841500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386841500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102449211500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 102481594500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32383000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102449211500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 102481594500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3681379 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3681379 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -520,14 +520,14 @@ system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565
|
|||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.885372 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.885372 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52508.564020 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.544685 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52508.564020 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -556,14 +556,14 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000
|
|||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697201500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697201500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938251500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 82964474500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938251500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 82964474500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -582,15 +582,21 @@ system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565
|
|||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.885372 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.885372 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.544685 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.564020 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution
|
||||
|
|
@ -606,15 +612,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919018 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.095255 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.293567 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 18227021 90.47% 90.47% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1919018 9.53% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.882285 # Nu
|
|||
sim_ticks 5882284743500 # Number of ticks simulated
|
||||
final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 724530 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1128884 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1416814365 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314268 # Number of bytes of host memory used
|
||||
host_seconds 4151.77 # Real time elapsed on the host
|
||||
host_inst_rate 704974 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1098413 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1378571885 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317252 # Number of bytes of host memory used
|
||||
host_seconds 4266.94 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution
|
||||
|
|
@ -464,15 +470,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919162 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.095286 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.293609 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000050 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.007053 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 18221943 90.47% 90.47% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1919162 9.53% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20140103 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1002 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.051911 # Nu
|
|||
sim_ticks 51910606500 # Number of ticks simulated
|
||||
final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 229005 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 229005 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 129351336 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295204 # Number of bytes of host memory used
|
||||
host_seconds 401.31 # Real time elapsed on the host
|
||||
host_inst_rate 339215 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 339215 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 191602600 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303192 # Number of bytes of host memory used
|
||||
host_seconds 270.93 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -663,6 +663,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution
|
||||
|
|
@ -678,15 +684,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 32052 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 32052 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.021919 # Nu
|
|||
sim_ticks 21919473500 # Number of ticks simulated
|
||||
final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 134628 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 134628 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35055621 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296224 # Number of bytes of host memory used
|
||||
host_seconds 625.28 # Real time elapsed on the host
|
||||
host_inst_rate 199769 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 199769 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52017673 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 302932 # Number of bytes of host memory used
|
||||
host_seconds 421.39 # Real time elapsed on the host
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_ops 84179709 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -971,6 +971,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 23293 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9635 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution
|
||||
|
|
@ -986,15 +992,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 23293 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 23293 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.130773 # Number of seconds simulated
|
||||
sim_ticks 130772636500 # Number of ticks simulated
|
||||
final_tick 130772636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 130772642500 # Number of ticks simulated
|
||||
final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 167747 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 176832 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 127303889 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 312696 # Number of bytes of host memory used
|
||||
host_seconds 1027.25 # Real time elapsed on the host
|
||||
host_inst_rate 233615 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 246267 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 177290947 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 321196 # Number of bytes of host memory used
|
||||
host_seconds 737.62 # Real time elapsed on the host
|
||||
sim_insts 172317810 # Number of instructions simulated
|
||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -22,12 +22,12 @@ system.physmem.num_reads::cpu.inst 2158 # Nu
|
|||
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 835894 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 835893 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 835894 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 835893 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3866 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 130772543000 # Total gap between requests
|
||||
system.physmem.totGap 130772548000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3617 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # By
|
|||
system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 28055750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100543250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 27654500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100142000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7257.05 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7153.26 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26007.05 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25903.26 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -220,35 +220,35 @@ system.physmem.readRowHits 2957 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 33826317.38 # Average gap between requests
|
||||
system.physmem.avgGap 33826318.68 # Average gap between requests
|
||||
system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3568801635 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 75331661250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 87462680535 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.826718 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 125318913500 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 3568631490 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 75331810500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 87462659640 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.826558 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 125319167750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1084715250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1084461000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3564422325 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 75335511000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 87460741830 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.811822 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 125325774500 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 3564306900 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 75335612250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 87460727655 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.811714 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 125325942500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1078159500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1077991500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 49732170 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted
|
||||
|
|
@ -377,7 +377,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 261545273 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 261545285 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 172317810 # Number of instructions committed
|
||||
|
|
@ -386,15 +386,15 @@ system.cpu.discardedOps 11660914 # Nu
|
|||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.517808 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.658845 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 255251954 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 6293319 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 255252020 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 6293265 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 42 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1377.707601 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1377.707606 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707601 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707606 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
|
||||
|
|
@ -430,14 +430,14 @@ system.cpu.dcache.demand_misses::cpu.data 2442 # n
|
|||
system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2443 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58025500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 58025500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 126322500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 126322500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 184348000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 184348000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 184348000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 184348000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 58082000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 58082000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 126294500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 126294500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 184376500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 184376500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 184376500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 184376500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 75490.581491 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 75459.680720 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 75502.252252 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 75471.346705 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809
|
|||
system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51768000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51768000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85075000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85075000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51822500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51822500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85060000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85060000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 136843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136913000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 136913000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136882500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 136882500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136952500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 136952500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -518,24 +518,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 2888 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1423.991727 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1423.991712 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991727 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991712 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id
|
||||
|
|
@ -559,12 +559,12 @@ system.cpu.icache.demand_misses::cpu.inst 4685 # n
|
|||
system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4685 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 199910500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 199910500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 199910500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 199910500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 199910500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 199910500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 199916500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 199916500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 199916500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 199916500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 199916500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 199916500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses
|
||||
|
|
@ -577,12 +577,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066
|
|||
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42670.330843 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42670.330843 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 42671.611526 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 42671.611526 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -597,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4685
|
|||
system.cpu.icache.demand_mshr_misses::total 4685 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4685 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4685 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195226500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 195226500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195226500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 195226500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195226500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 195226500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195232500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 195232500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195232500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 195232500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195232500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 195232500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41670.544290 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41670.544290 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41670.544290 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41670.544290 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2000.604150 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2000.604140 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5191 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2784 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.864583 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029284 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756657 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818208 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029285 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.756648 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.818207 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045983 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy
|
||||
|
|
@ -664,18 +664,18 @@ system.cpu.l2cache.demand_misses::total 3883 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3883 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83342500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 83342500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161697500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 161697500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49918000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49918000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 161697500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 133260500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 294958000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 161697500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 133260500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 294958000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83327500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 83327500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 161329500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 161329500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49900500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49900500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 161329500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 133228000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 294557500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -702,18 +702,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.597844 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461259 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.597844 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76461.009174 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76461.009174 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74825.312355 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74825.312355 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78984.177215 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78984.177215 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75961.370075 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74825.312355 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77387.049942 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75961.370075 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -744,18 +744,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3867
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72442500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72442500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139969500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139969500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42776000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42776000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139969500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115218500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 255188000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139969500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115218500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 255188000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72427500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72427500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 139601500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 139601500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 42758500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 42758500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139601500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115186000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 254787500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139601500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115186000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 254787500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -768,19 +768,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9425 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3064 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution
|
||||
|
|
@ -796,14 +802,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 9425 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks)
|
||||
|
|
@ -831,9 +837,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3866 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4535000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 4535500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 20543000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 20543250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu
|
|||
sim_ticks 1869358498000 # Number of ticks simulated
|
||||
final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2452265 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2452264 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 70524991939 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 374768 # Number of bytes of host memory used
|
||||
host_seconds 26.51 # Real time elapsed on the host
|
||||
host_inst_rate 2397277 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 68943602925 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 377676 # Number of bytes of host memory used
|
||||
host_seconds 27.11 # Real time elapsed on the host
|
||||
sim_insts 65000470 # Number of instructions simulated
|
||||
sim_ops 65000470 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu0.inst 763584 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 68173952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 763584 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 869824 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.inst 11931 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1065218 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.inst 408474 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 36469170 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 408474 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 465306 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 408474 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40660828 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -737,20 +737,20 @@ system.iocache.cache_copies 0 # nu
|
|||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 999684 # number of replacements
|
||||
system.l2c.tags.replacements 999687 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4588619 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1064734 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 4.309639 # Average number of references to valid blocks.
|
||||
system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 55911.037805 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4939.570238 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4176.759225 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.853135 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.075372 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063732 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy
|
||||
|
|
@ -761,8 +761,8 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 #
|
|||
system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 49101323 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 49101323 # Number of data accesses
|
||||
system.l2c.tags.tag_accesses 46365678 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46365678 # Number of data accesses
|
||||
system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 777520 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits
|
||||
|
|
@ -774,22 +774,22 @@ system.l2c.SCUpgradeReq_hits::total 50 # nu
|
|||
system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 606993 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 986545 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 606993 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910322 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 606993 # number of overall hits
|
||||
system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738161 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 185616 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910322 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910319 # number of overall hits
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses
|
||||
|
|
@ -799,22 +799,22 @@ system.l2c.SCUpgradeReq_misses::total 2285 # nu
|
|||
system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 11931 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 13591 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 11931 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1066177 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11931 # number of overall misses
|
||||
system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12102 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066177 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066180 # number of overall misses
|
||||
system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses)
|
||||
|
|
@ -851,22 +851,22 @@ system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # mi
|
|||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019277 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.013589 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.019277 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.358198 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.019277 # miss rate for overall accesses
|
||||
system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358198 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -879,49 +879,55 @@ system.l2c.writebacks::writebacks 80913 # nu
|
|||
system.l2c.writebacks::total 80913 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948863 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948866 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 122433 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 922490 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917961 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 126472 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 124247 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941414 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3178369 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3222443 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3347604 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73455442 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76124178 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2210194 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2205834 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2210194 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2210194 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2205834 # Request fanout histogram
|
||||
system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 2204578 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution
|
||||
|
|
@ -929,30 +935,30 @@ system.toL2Bus.trans_dist::ReadExReq 295246 # Tr
|
|||
system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856188 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450155 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143095 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684380 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 9133818 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1705094 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5410979 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 41895 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 6099689 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 3.006841 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.082430 # Request fanout histogram
|
||||
system.toL2Bus.snoops 1083281 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::3 6057958 99.32% 99.32% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::4 41731 0.68% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 6099689 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu
|
|||
sim_ticks 1829332273500 # Number of ticks simulated
|
||||
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2495393 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2495392 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 76033049021 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 371696 # Number of bytes of host memory used
|
||||
host_seconds 24.06 # Real time elapsed on the host
|
||||
host_inst_rate 2390951 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72850763127 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 374092 # Number of bytes of host memory used
|
||||
host_seconds 25.11 # Real time elapsed on the host
|
||||
sim_insts 60038341 # Number of instructions simulated
|
||||
sim_ops 60038341 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -338,9 +338,9 @@ system.cpu.icache.cache_copies 0 # nu
|
|||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 992219 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor
|
||||
|
|
@ -356,8 +356,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
|
|
@ -429,36 +429,42 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74334 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoops 1075788 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -561,7 +567,7 @@ system.membus.trans_dist::ReadResp 948374 # Tr
|
|||
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 115846 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 918371 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917156 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116946 # Transaction distribution
|
||||
|
|
@ -570,11 +576,11 @@ system.membus.trans_dist::ReadSharedReq 941190 # Tr
|
|||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -582,17 +588,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904
|
|||
system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2151059 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2150005 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2151059 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2150005 # Request fanout histogram
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
|||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 714694 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 870026 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 13935517761 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 573808 # Number of bytes of host memory used
|
||||
host_seconds 199.77 # Real time elapsed on the host
|
||||
host_inst_rate 1159279 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22604281025 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 628452 # Number of bytes of host memory used
|
||||
host_seconds 123.16 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -403,9 +403,9 @@ system.cpu.icache.cache_copies 0 # nu
|
|||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
|
||||
|
|
@ -428,8 +428,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits
|
||||
|
|
@ -535,12 +535,18 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101949 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
|
|
@ -548,28 +554,28 @@ system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoops 182974 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
|
|
@ -678,7 +684,7 @@ system.membus.trans_dist::ReadResp 74202 # Tr
|
|||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8204 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
|
|
@ -692,9 +698,9 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -746,13 +752,13 @@ system.realview.ethernet.totalRxOrn 0 # to
|
|||
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
|
|
|
|||
|
|
@ -4,66 +4,70 @@ sim_seconds 2.802895 # Nu
|
|||
sim_ticks 2802894699500 # Number of ticks simulated
|
||||
final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1155692 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1408193 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22061708570 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 584036 # Number of bytes of host memory used
|
||||
host_seconds 127.05 # Real time elapsed on the host
|
||||
host_inst_rate 1151168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1402682 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21975358508 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 637292 # Number of bytes of host memory used
|
||||
host_seconds 127.55 # Real time elapsed on the host
|
||||
sim_insts 146828240 # Number of instructions simulated
|
||||
sim_ops 178908039 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 1090916 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 9418084 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 146388 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 1083988 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 1095972 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 9418276 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 148052 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 1084052 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11740912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 1090916 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 146388 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1237304 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8475264 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::total 11747952 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 1095972 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 148052 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1244024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8467328 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8492828 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8484892 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 25499 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 147677 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 2442 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 16958 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 25578 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 147680 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 2468 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 16959 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 192600 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 132426 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 192710 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 132302 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 136817 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 136693 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 389210 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 3360128 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 52227 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 386739 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 391014 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 3360196 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 52821 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 386762 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4188852 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 389210 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 52227 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 441438 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3023754 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4191364 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 391014 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 52821 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 443835 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3020923 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3030020 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3023754 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3027189 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3020923 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 389210 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 3366380 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 52227 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 386753 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 391014 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 3366448 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 52821 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 386776 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7218873 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7218553 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
|
||||
|
|
@ -367,8 +371,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 511204 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 511204 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::writebacks 511149 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 511149 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 1109735 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use
|
||||
|
|
@ -427,9 +431,9 @@ system.cpu0.l2cache.prefetcher.pfRemovedFull 0
|
|||
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
||||
system.cpu0.l2cache.tags.replacements 252605 # number of replacements
|
||||
system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use
|
||||
system.cpu0.l2cache.tags.total_refs 3093887 # Total number of references to valid blocks.
|
||||
system.cpu0.l2cache.tags.total_refs 3066089 # Total number of references to valid blocks.
|
||||
system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks.
|
||||
system.cpu0.l2cache.tags.avg_refs 11.510039 # Average number of references to valid blocks.
|
||||
system.cpu0.l2cache.tags.avg_refs 11.406624 # Average number of references to valid blocks.
|
||||
system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor
|
||||
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor
|
||||
|
|
@ -454,13 +458,13 @@ system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582
|
|||
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id
|
||||
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id
|
||||
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id
|
||||
system.cpu0.l2cache.tags.tag_accesses 60120327 # Number of tag accesses
|
||||
system.cpu0.l2cache.tags.data_accesses 60120327 # Number of data accesses
|
||||
system.cpu0.l2cache.tags.tag_accesses 59674327 # Number of tag accesses
|
||||
system.cpu0.l2cache.tags.data_accesses 59674327 # Number of data accesses
|
||||
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits
|
||||
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits
|
||||
system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits
|
||||
system.cpu0.l2cache.Writeback_hits::writebacks 511204 # number of Writeback hits
|
||||
system.cpu0.l2cache.Writeback_hits::total 511204 # number of Writeback hits
|
||||
system.cpu0.l2cache.Writeback_hits::writebacks 511149 # number of Writeback hits
|
||||
system.cpu0.l2cache.Writeback_hits::total 511149 # number of Writeback hits
|
||||
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits
|
||||
system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits
|
||||
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits
|
||||
|
|
@ -505,8 +509,8 @@ system.cpu0.l2cache.overall_misses::total 348765 # n
|
|||
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.l2cache.Writeback_accesses::writebacks 511204 # number of Writeback accesses(hits+misses)
|
||||
system.cpu0.l2cache.Writeback_accesses::total 511204 # number of Writeback accesses(hits+misses)
|
||||
system.cpu0.l2cache.Writeback_accesses::writebacks 511149 # number of Writeback accesses(hits+misses)
|
||||
system.cpu0.l2cache.Writeback_accesses::total 511149 # number of Writeback accesses(hits+misses)
|
||||
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses)
|
||||
|
|
@ -558,15 +562,21 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.l2cache.writebacks::writebacks 192999 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 192999 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::writebacks 192992 # number of writebacks
|
||||
system.cpu0.l2cache.writebacks::total 192992 # number of writebacks
|
||||
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.toL2Bus.snoop_filter.tot_requests 3720205 # Total number of requests made to the snoop filter.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860284 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.tot_snoops 118049 # Total number of snoops made to the snoop filter.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 117943 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::Writeback 511204 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::CleanEvict 1292017 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::Writeback 511149 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::CleanEvict 1264197 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution
|
||||
|
|
@ -574,28 +584,28 @@ system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # T
|
|||
system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution
|
||||
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution
|
||||
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348291 # Packet count per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402034 # Packet count per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395204 # Packet count per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_count::total 5791961 # Packet count per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_count::total 5764086 # Packet count per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887684 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80884164 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.pkt_size::total 152063428 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.snoops 327822 # Total snoops (count)
|
||||
system.cpu0.toL2Bus.snoop_fanout::samples 4022806 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::mean 1.061160 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::stdev 0.239623 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.pkt_size::total 152059908 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu0.toL2Bus.snoops 522626 # Total snoops (count)
|
||||
system.cpu0.toL2Bus.snoop_fanout::samples 4217611 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::mean 0.044172 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::stdev 0.205599 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::1 3776773 93.88% 93.88% # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::2 246033 6.12% 100.00% # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::0 4031417 95.59% 95.59% # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::1 186088 4.41% 100.00% # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::2 106 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::total 4022806 # Request fanout histogram
|
||||
system.cpu0.toL2Bus.snoop_fanout::total 4217611 # Request fanout histogram
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -873,8 +883,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 120813 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 120813 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::writebacks 120812 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 120812 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.icache.tags.replacements 523373 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use
|
||||
|
|
@ -932,9 +942,9 @@ system.cpu1.l2cache.prefetcher.pfRemovedFull 0
|
|||
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
||||
system.cpu1.l2cache.tags.replacements 48465 # number of replacements
|
||||
system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use
|
||||
system.cpu1.l2cache.tags.total_refs 1307502 # Total number of references to valid blocks.
|
||||
system.cpu1.l2cache.tags.total_refs 1296358 # Total number of references to valid blocks.
|
||||
system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks.
|
||||
system.cpu1.l2cache.tags.avg_refs 20.648137 # Average number of references to valid blocks.
|
||||
system.cpu1.l2cache.tags.avg_refs 20.472151 # Average number of references to valid blocks.
|
||||
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor
|
||||
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor
|
||||
|
|
@ -957,13 +967,13 @@ system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338
|
|||
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id
|
||||
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id
|
||||
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id
|
||||
system.cpu1.l2cache.tags.tag_accesses 24723530 # Number of tag accesses
|
||||
system.cpu1.l2cache.tags.data_accesses 24723530 # Number of data accesses
|
||||
system.cpu1.l2cache.tags.tag_accesses 24545002 # Number of tag accesses
|
||||
system.cpu1.l2cache.tags.data_accesses 24545002 # Number of data accesses
|
||||
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits
|
||||
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits
|
||||
system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits
|
||||
system.cpu1.l2cache.Writeback_hits::writebacks 120813 # number of Writeback hits
|
||||
system.cpu1.l2cache.Writeback_hits::total 120813 # number of Writeback hits
|
||||
system.cpu1.l2cache.Writeback_hits::writebacks 120812 # number of Writeback hits
|
||||
system.cpu1.l2cache.Writeback_hits::total 120812 # number of Writeback hits
|
||||
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
|
||||
system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits
|
||||
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits
|
||||
|
|
@ -1008,8 +1018,8 @@ system.cpu1.l2cache.overall_misses::total 131449 # n
|
|||
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.l2cache.Writeback_accesses::writebacks 120813 # number of Writeback accesses(hits+misses)
|
||||
system.cpu1.l2cache.Writeback_accesses::total 120813 # number of Writeback accesses(hits+misses)
|
||||
system.cpu1.l2cache.Writeback_accesses::writebacks 120812 # number of Writeback accesses(hits+misses)
|
||||
system.cpu1.l2cache.Writeback_accesses::total 120812 # number of Writeback accesses(hits+misses)
|
||||
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses)
|
||||
|
|
@ -1061,15 +1071,21 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.l2cache.writebacks::writebacks 32917 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 32917 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::writebacks 32915 # number of writebacks
|
||||
system.cpu1.l2cache.writebacks::total 32915 # number of writebacks
|
||||
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.toL2Bus.snoop_filter.tot_requests 1533423 # Total number of requests made to the snoop filter.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773258 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.tot_snoops 88765 # Total number of snoops made to the snoop filter.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 88649 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 116 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::Writeback 120813 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::CleanEvict 594498 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::Writeback 120812 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::CleanEvict 583341 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution
|
||||
|
|
@ -1077,28 +1093,28 @@ system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # T
|
|||
system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution
|
||||
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution
|
||||
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571497 # Packet count per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778746 # Packet count per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776513 # Packet count per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_count::total 2368937 # Packet count per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_count::total 2357779 # Packet count per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873326 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873262 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.pkt_size::total 56440062 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.snoops 568500 # Total snoops (count)
|
||||
system.cpu1.toL2Bus.snoop_fanout::samples 2040956 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::mean 1.248991 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::stdev 0.432428 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.pkt_size::total 56439998 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu1.toL2Bus.snoops 273409 # Total snoops (count)
|
||||
system.cpu1.toL2Bus.snoop_fanout::samples 1745865 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::mean 0.067447 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::stdev 0.251059 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::1 1532777 75.10% 75.10% # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::2 508179 24.90% 100.00% # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::0 1628228 93.26% 93.26% # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::1 117521 6.73% 99.99% # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::2 116 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::total 2040956 # Request fanout histogram
|
||||
system.cpu1.toL2Bus.snoop_fanout::total 1745865 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
|
||||
|
|
@ -1202,109 +1218,114 @@ system.iocache.cache_copies 0 # nu
|
|||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 106825 # number of replacements
|
||||
system.l2c.tags.tagsinuse 62089.721630 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 288805 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 167355 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 1.725703 # Average number of references to valid blocks.
|
||||
system.l2c.tags.replacements 106968 # number of replacements
|
||||
system.l2c.tags.tagsinuse 62096.352232 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 248810 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 167499 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 1.485442 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 47734.864298 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::writebacks 47767.595021 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.041981 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 7941.182718 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4069.651943 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 1613.022165 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 726.922600 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.728376 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 7914.071704 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4068.609194 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 1612.456889 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 728.691105 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.728876 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.121173 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.062098 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.024613 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.011092 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.947414 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.120759 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.062082 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.024604 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.011119 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.947515 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 60523 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 60524 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 45532 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 1892 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 13030 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 45506 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.923508 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 5581048 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 5581048 # Number of data accesses
|
||||
system.l2c.Writeback_hits::writebacks 225916 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 225916 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 290 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 72 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 362 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 60 # number of SCUpgradeReq hits
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.923523 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 5237373 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 5237373 # Number of data accesses
|
||||
system.l2c.Writeback_hits::writebacks 225907 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 225907 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 289 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 360 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 59 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 14091 # number of ReadExReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 14099 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 17178 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 17186 # number of ReadExReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.inst 28425 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 76409 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.inst 28346 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 76399 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.inst 11464 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 11380 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 127912 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.inst 11438 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 11382 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 127799 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 28425 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 90500 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 28346 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 90498 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 11464 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 14467 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 145090 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 11438 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 14469 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 144985 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 28425 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 90500 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 28346 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 90498 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 11464 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 14467 # number of overall hits
|
||||
system.l2c.overall_hits::total 145090 # number of overall hits
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 9984 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 3297 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 13281 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses
|
||||
system.l2c.overall_hits::cpu1.inst 11438 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 14469 # number of overall hits
|
||||
system.l2c.overall_hits::total 144985 # number of overall hits
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 9985 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 3298 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 13283 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 1936 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 136573 # number of ReadExReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 1937 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 136565 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 152409 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 152401 # number of ReadExReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.inst 16484 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 11221 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.inst 2277 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1138 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 31129 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.inst 16563 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 11232 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.inst 2303 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1139 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 31247 # number of ReadSharedReq misses
|
||||
system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 16484 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 147794 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 2277 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 16974 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 183538 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 16563 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 147797 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 2303 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 16975 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 183648 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 16484 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 147794 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 2277 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 16974 # number of overall misses
|
||||
system.l2c.overall_misses::total 183538 # number of overall misses
|
||||
system.l2c.Writeback_accesses::writebacks 225916 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 225916 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.overall_misses::cpu0.inst 16563 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 147797 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 2303 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 16975 # number of overall misses
|
||||
system.l2c.overall_misses::total 183648 # number of overall misses
|
||||
system.l2c.Writeback_accesses::writebacks 225907 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 225907 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses)
|
||||
|
|
@ -1317,60 +1338,63 @@ system.l2c.ReadExReq_accesses::total 169587 # nu
|
|||
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.data 87630 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 42 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.data 87631 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 43 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.data 12518 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::total 159041 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.data 12521 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::total 159046 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 238294 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 238295 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 31441 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 328628 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 31444 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 328633 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 238294 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 238295 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 31441 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 328628 # number of overall (read+write) accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971773 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978629 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.973466 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.926650 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.overall_accesses::cpu1.data 31444 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 328633 # number of overall (read+write) accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971871 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978925 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.973613 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.927873 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.966068 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.906474 # miss rate for ReadExReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.966567 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.906421 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.898707 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.898660 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367053 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128050 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.165708 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090909 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.195729 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.368812 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128174 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.167601 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090967 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.196465 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.367053 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.620217 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.165708 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.539868 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.558498 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.368812 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.620227 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.167601 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.539849 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.558824 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.367053 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.620217 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.165708 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.539868 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.558498 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.368812 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.620227 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.167601 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.539849 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.558824 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -1379,51 +1403,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
|
|||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 96236 # number of writebacks
|
||||
system.l2c.writebacks::total 96236 # number of writebacks
|
||||
system.l2c.writebacks::writebacks 96112 # number of writebacks
|
||||
system.l2c.writebacks::total 96112 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 43997 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 75378 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 75496 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 30846 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 30846 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 132426 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 15452 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 40917 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 15653 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 196055 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 151973 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 31381 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 132302 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8413 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 60363 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 40918 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 15656 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 196047 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 151965 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 31499 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666955 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 788339 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 897733 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660257 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 781641 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 890796 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17934348 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 18124130 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17933452 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 18123234 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20456418 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20455522 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 587659 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 580848 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 587659 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 580848 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 587659 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 580848 # Request fanout histogram
|
||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
@ -1455,45 +1479,51 @@ system.realview.ethernet.totalRxOrn 0 # to
|
|||
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.toL2Bus.snoop_filter.tot_requests 874927 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 450220 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 131568 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 9077 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 8809 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 225916 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 84734 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 225907 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 41761 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1184948 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 427892 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 1612840 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685820 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417842 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 45103662 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 36713 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 998221 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 1.036541 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.187632 # Request fanout histogram
|
||||
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1153838 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 416020 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 1569858 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685372 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417714 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 45103086 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 180140 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 1129657 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.285654 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.452250 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 961745 96.35% 96.35% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 36476 3.65% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 807234 71.46% 71.46% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 322155 28.52% 99.98% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 268 0.02% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 998221 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 1129657 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
|||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1188421 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1446712 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 23172506899 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 571472 # Number of bytes of host memory used
|
||||
host_seconds 120.14 # Real time elapsed on the host
|
||||
host_inst_rate 1171566 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22843865684 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 624228 # Number of bytes of host memory used
|
||||
host_seconds 121.87 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -403,9 +403,9 @@ system.cpu.icache.cache_copies 0 # nu
|
|||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
|
||||
|
|
@ -428,8 +428,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits
|
||||
|
|
@ -535,12 +535,18 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101949 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
|
|
@ -548,28 +554,28 @@ system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoops 182974 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
|
|
@ -678,7 +684,7 @@ system.membus.trans_dist::ReadResp 74202 # Tr
|
|||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8204 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
|
|
@ -692,9 +698,9 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -746,13 +752,13 @@ system.realview.ethernet.totalRxOrn 0 # to
|
|||
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
|||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1097147 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1335600 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 21392785088 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 571732 # Number of bytes of host memory used
|
||||
host_seconds 130.13 # Real time elapsed on the host
|
||||
host_inst_rate 1174884 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22908545755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 623708 # Number of bytes of host memory used
|
||||
host_seconds 121.52 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -763,9 +763,9 @@ system.iocache.writebacks::total 36190 # nu
|
|||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 109907 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4567770 # Total number of references to valid blocks.
|
||||
system.l2c.tags.total_refs 4528496 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 26.073532 # Average number of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 25.849350 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 48764.072075 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor
|
||||
|
|
@ -794,8 +794,8 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 #
|
|||
system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 40922425 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 40922425 # Number of data accesses
|
||||
system.l2c.tags.tag_accesses 40608233 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 40608233 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits
|
||||
|
|
@ -956,7 +956,7 @@ system.membus.trans_dist::ReadResp 74196 # Tr
|
|||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138133 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8204 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
|
|
@ -970,9 +970,9 @@ system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port
|
|||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723054 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -1024,22 +1024,28 @@ system.realview.ethernet.totalRxOrn 0 # to
|
|||
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.toL2Bus.snoop_filter.tot_requests 5060706 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 2541063 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.trans_dist::ReadReq 71244 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1836352 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
|
|
@ -1047,27 +1053,27 @@ system.toL2Bus.trans_dist::ReadExReq 298922 # Tr
|
|||
system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116722 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2582000 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5084714 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574734 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 7761036 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 36631 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 5176290 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 1.013064 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.113547 # Request fanout histogram
|
||||
system.toL2Bus.snoops 182968 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.134877 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 5108669 98.69% 98.69% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 67621 1.31% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 5223970 98.15% 98.15% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 98657 1.85% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 5176290 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 5322627 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu
|
|||
sim_ticks 5112152301500 # Number of ticks simulated
|
||||
final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1340669 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2744641 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34257071569 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 654012 # Number of bytes of host memory used
|
||||
host_seconds 149.23 # Real time elapsed on the host
|
||||
host_inst_rate 1349307 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34477807791 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 659588 # Number of bytes of host memory used
|
||||
host_seconds 148.27 # Real time elapsed on the host
|
||||
sim_insts 200066731 # Number of instructions simulated
|
||||
sim_ops 409580371 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -337,9 +337,9 @@ system.cpu.itb_walker_cache.writebacks::total 545
|
|||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 106193 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4345511 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.539145 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor
|
||||
|
|
@ -359,8 +359,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 39306136 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39306136 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits
|
||||
|
|
@ -456,42 +456,48 @@ system.cpu.l2cache.cache_copies 0 # nu
|
|||
system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98168 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 886676 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377686 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613888 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 35029733 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377675 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613331 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 49698 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18776912 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 3.002627 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.051183 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoops 203459 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 18727593 99.74% 99.74% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 49319 0.26% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18776912 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
|
||||
|
|
@ -600,7 +606,7 @@ system.membus.trans_dist::ReadResp 13903747 # Tr
|
|||
system.membus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 144835 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 9844 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8392 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134360 # Transaction distribution
|
||||
|
|
@ -614,11 +620,11 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav
|
|||
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 471480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28214040 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28360246 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -629,17 +635,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480
|
|||
system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 14257691 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 14256770 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14255995 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14257691 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14256770 # Request fanout histogram
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000038 # Number of seconds simulated
|
||||
sim_ticks 37552000 # Number of ticks simulated
|
||||
final_tick 37552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 37553000 # Number of ticks simulated
|
||||
final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72134 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 72118 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 423067865 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288748 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 161315 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 161262 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 945919395 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296228 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 6400 # Number of instructions simulated
|
||||
sim_ops 6400 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu
|
|||
system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 620366425 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 288027269 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 908393694 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 620366425 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 620366425 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 620366425 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 288027269 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 908393694 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 620349905 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 288019599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 908369504 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 620349905 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 620349905 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 620349905 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 288019599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 908369504 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 533 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 37447500 # Total gap between requests
|
||||
system.physmem.totGap 37448500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -206,9 +206,9 @@ system.physmem.totBusLat 2665000 # To
|
|||
system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 908.39 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBW 908.37 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 908.39 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 908.37 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.10 # Data bus utilization in percentage
|
||||
|
|
@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 70257.97 # Average gap between requests
|
||||
system.physmem.avgGap 70259.85 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -293,24 +293,24 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 75104 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 75106 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6400 # Number of instructions committed
|
||||
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 11.735000 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.085215 # IPC: instructions per cycle
|
||||
system.cpu.cpi 11.735312 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.085213 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 62587 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.idleCycles 62589 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.919220 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.920661 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.919220 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.920661 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
||||
|
|
@ -417,14 +417,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 175.811080 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 175.815240 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 175.811080 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.085845 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.085845 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 175.815240 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.085847 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.085847 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
|
||||
|
|
@ -443,12 +443,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n
|
|||
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 365 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 27931500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 27931500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 27931500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 27931500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 27931500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 27931500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 27932500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 27932500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 27932500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 27932500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 27932500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 27932500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses
|
||||
|
|
@ -461,12 +461,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.137684
|
|||
system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76524.657534 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76524.657534 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76524.657534 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76524.657534 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76527.397260 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76527.397260 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -481,33 +481,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365
|
|||
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27566500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 27566500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 27566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27566500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 27566500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27567500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 27567500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27567500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 27567500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27567500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 27567500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75524.657534 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75524.657534 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 233.447652 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 233.452540 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.824515 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623137 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.828674 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623866 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy
|
||||
|
|
@ -640,6 +640,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
|
|
@ -653,14 +659,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001873 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.043274 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 533 99.81% 99.81% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
|||
sim_ticks 21900500 # Number of ticks simulated
|
||||
final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 43231 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 43225 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 148545474 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289772 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 94413 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 94393 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 324370159 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297000 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -698,12 +698,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
|
||||
|
|
@ -724,12 +724,12 @@ system.cpu.icache.demand_misses::cpu.inst 459 # n
|
|||
system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 459 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32352500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32352500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32352500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32352500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32352500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32352500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses
|
||||
|
|
@ -742,12 +742,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.220038
|
|||
system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70484.749455 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70484.749455 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -768,24 +768,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 311
|
|||
system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23859500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23859500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23859500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23859500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23859500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23859500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use
|
||||
|
|
@ -927,6 +927,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
|
||||
|
|
@ -940,14 +946,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
sim_ticks 32544500 # Number of ticks simulated
|
||||
final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 32545500 # Number of ticks simulated
|
||||
final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 619666 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 618826 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3148046044 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291528 # Number of bytes of host memory used
|
||||
host_inst_rate 507828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 507304 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2581337246 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294696 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
|||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 65089 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 65091 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 65089 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 65091 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.755352 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.755352 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
|
||||
|
|
@ -226,14 +226,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.988451 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.988451 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062494 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062494 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
||||
|
|
@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n
|
|||
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 279 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
|
||||
|
|
@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587
|
|||
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -290,36 +290,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279
|
|||
system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15024500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15024500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15024500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15024500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15024500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15024500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.465722 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.994443 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.471279 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005629 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
||||
|
|
@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
|
|
@ -462,14 +468,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu
|
|||
sim_ticks 20075000 # Number of ticks simulated
|
||||
final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 42420 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42407 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 329231154 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 287436 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 131673 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 131586 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1021264689 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295944 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 2585 # Number of instructions simulated
|
||||
sim_ops 2585 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -634,6 +634,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 308 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
|
|
@ -647,15 +653,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu
|
|||
sim_ticks 12363500 # Number of ticks simulated
|
||||
final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 20992 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 20989 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 108692792 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288464 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 79745 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79707 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 412680664 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295680 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -919,6 +919,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
|
||||
|
|
@ -932,15 +938,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 16524500 # Number of ticks simulated
|
||||
final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 374183 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 373424 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2390351512 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291260 # Number of bytes of host memory used
|
||||
host_inst_rate 315037 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 314537 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2013954906 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293376 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -443,6 +443,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
|
|
@ -456,15 +462,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000030 # Number of seconds simulated
|
||||
sim_ticks 29941500 # Number of ticks simulated
|
||||
final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 29949500 # Number of ticks simulated
|
||||
final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 58660 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 68656 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 381226078 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304332 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 110305 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 129095 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 716958322 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313816 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 4605 # Number of instructions simulated
|
||||
sim_ops 5391 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
|
|||
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 421 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 29851000 # Total gap between requests
|
||||
system.physmem.totGap 29858000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # By
|
|||
system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2218000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 2201000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.03 # Data bus utilization in percentage
|
||||
|
|
@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 70904.99 # Average gap between requests
|
||||
system.physmem.avgGap 70921.62 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 59883 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 59899 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4605 # Number of instructions committed
|
||||
system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 13.003909 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.076900 # IPC: instructions per cycle
|
||||
system.cpu.cpi 13.007383 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.076879 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
|
|
@ -423,14 +423,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
|
|||
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 182 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -451,14 +451,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.087711
|
|||
system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -483,14 +483,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
|
|||
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -499,24 +499,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 3 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
|
||||
|
|
@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n
|
|||
system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 322 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
|
||||
|
|
@ -553,12 +553,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.143622
|
|||
system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -573,34 +573,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322
|
|||
system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
|
||||
|
|
@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data 124 #
|
|||
system.cpu.l2cache.overall_misses::total 429 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 116
|
|||
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -731,17 +731,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
|
|
@ -756,14 +762,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks)
|
||||
|
|
@ -791,7 +797,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 421 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 17163000 # Number of ticks simulated
|
||||
final_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 17170000 # Number of ticks simulated
|
||||
final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 25428 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 29777 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 95019968 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305352 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_inst_rate 50361 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 58973 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188251031 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313812 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu
|
|||
system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 396 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1025043681 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 451019220 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1476062900 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1025043681 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1025043681 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1025043681 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 451019220 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1476062900 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 396 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 17090000 # Total gap between requests
|
||||
system.physmem.totGap 17097000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # By
|
|||
system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3055250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 3045250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10470250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7690.03 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 26440.03 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1476.06 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1476.06 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.54 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 11.53 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 11.53 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
|
|
@ -220,21 +220,21 @@ system.physmem.readRowHits 330 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43156.57 # Average gap between requests
|
||||
system.physmem.avgGap 43174.24 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 10798650 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 911.198611 # Core power per rank (mW)
|
||||
system.physmem_0.totalEnergy 14433105 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 911.108972 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 16183750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -245,18 +245,18 @@ system.physmem_1.actBackEnergy 10407915 # En
|
|||
system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 807.028896 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::IDLE 672250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 2533 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 812 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 2537 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1577 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 453 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 2106 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 814 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 38.651472 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
|
|
@ -496,95 +496,95 @@ system.cpu.itb.inst_accesses 0 # IT
|
|||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 34327 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 34341 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11725 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2533 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11733 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2537 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 1135 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 4671 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 955 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 292 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 13078 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.059336 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.422082 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 10515 80.40% 80.40% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 260 1.99% 82.39% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 215 1.64% 84.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 219 1.67% 85.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 267 2.04% 87.75% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 312 2.39% 90.14% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 142 1.09% 91.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 157 1.20% 92.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 991 7.58% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked
|
||||
system.cpu.fetch.rateDist::total 13078 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.073877 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.341662 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 6351 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 4223 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2063 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch
|
||||
system.cpu.decode.UnblockCycles 119 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 322 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 11299 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1964 # Number of cycles rename is running
|
||||
system.cpu.rename.SquashCycles 322 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 6564 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 644 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2338 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 1962 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 10655 # Number of instructions processed by rename
|
||||
system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 10847 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 48852 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 11762 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 5353 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 42 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 2118 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1531 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 9695 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 7972 # Number of instructions issued
|
||||
system.cpu.iq.iqInstsIssued 7975 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedInstsExamined 4363 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 10837 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 13078 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.609803 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.341106 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 9890 75.62% 75.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1180 9.02% 84.65% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 762 5.83% 90.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 451 3.45% 93.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 329 2.52% 96.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 278 2.13% 98.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 115 0.88% 99.44% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 13078 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available
|
||||
|
|
@ -620,69 +620,69 @@ system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # at
|
|||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4886 61.27% 61.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1833 22.98% 84.38% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1246 15.62% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 7972 # Type of FU issued
|
||||
system.cpu.iq.rate 0.232237 # Inst issue rate
|
||||
system.cpu.iq.FU_type_0::total 7975 # Type of FU issued
|
||||
system.cpu.iq.rate 0.232230 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 152 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fu_busy_rate 0.019060 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 29132 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 14007 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 7313 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 8084 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 1091 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedStores 593 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewSquashCycles 322 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 611 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 9750 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 2118 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1531 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
|
||||
|
|
@ -690,43 +690,43 @@ system.cpu.iew.memOrderViolationEvents 19 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions
|
||||
system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 274 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 9 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 2930 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1433 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1194 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.224226 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7341 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3456 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6757 # num instructions consuming a value
|
||||
system.cpu.iew.exec_refs 2933 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1435 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1197 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.224251 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7436 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7345 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 3459 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6763 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.213855 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.213884 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.511459 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4371 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle
|
||||
system.cpu.commit.branchMispredicts 298 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 12306 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.437023 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.282384 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 10254 83.33% 83.33% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 882 7.17% 90.49% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 420 3.41% 93.91% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 223 1.81% 95.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 112 0.91% 96.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 213 1.73% 98.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 51 0.41% 98.77% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 40 0.33% 99.10% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 12306 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4592 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -773,32 +773,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 21783 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 20313 # The number of ROB writes
|
||||
system.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 21787 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 20281 # The number of ROB writes
|
||||
system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 21263 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4592 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 7.475392 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.133772 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 7631 # number of integer regfile reads
|
||||
system.cpu.cpi 7.478441 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.478441 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.133718 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.133718 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 7636 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 4176 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 32 # number of floating regfile reads
|
||||
system.cpu.cc_regfile_reads 27375 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 3204 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 3054 # number of misc regfile reads
|
||||
system.cpu.cc_regfile_reads 27387 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 3201 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 3057 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 87.846363 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.851603 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021448 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021448 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 87.846363 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021447 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021447 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
|
||||
|
|
@ -827,16 +827,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n
|
|||
system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 498 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10572000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10572000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22577500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 22577500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10593000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 10593000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22578500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 22578500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33149500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33149500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33149500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33149500 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 33171500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 33171500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 33171500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 33171500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -859,16 +859,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.196838
|
|||
system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58524.861878 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 58524.861878 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71225.552050 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 71225.552050 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66565.261044 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66565.261044 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66609.437751 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66609.437751 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
||||
|
|
@ -895,14 +895,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147
|
|||
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6969000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6969000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3397000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3397000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10366000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10366000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10366000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10366000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6985000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6985000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10383000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10383000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10383000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10383000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -911,66 +911,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66523.809524 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66523.809524 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 149.741808 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1582 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 149.742670 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1585 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.399317 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5.409556 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 149.741808 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.073116 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.073116 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 149.742670 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.073117 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.073117 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4229 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4229 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1582 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1582 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1582 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1582 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1582 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1582 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 4235 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4235 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1585 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1585 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1585 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1585 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1585 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1585 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 386 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 26869500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 26869500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 26869500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 26869500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 26869500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 26869500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196138 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.196138 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.196138 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.196138 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.196138 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.196138 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69610.103627 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69610.103627 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 26879500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 26879500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 26879500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 26879500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 26879500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 26879500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195840 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.195840 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.195840 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.195840 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.195840 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.195840 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69636.010363 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69636.010363 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69636.010363 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69636.010363 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
||||
|
|
@ -991,33 +991,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 293
|
|||
system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21385500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 21385500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21385500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 21385500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21385500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 21385500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148882 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.148882 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.148882 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21398500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 21398500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21398500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 21398500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21398500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 21398500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148656 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.148656 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.148656 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73032.423208 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73032.423208 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 187.228350 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 187.228140 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.551776 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.676574 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.553706 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 46.674434 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy
|
||||
|
|
@ -1051,16 +1051,16 @@ system.cpu.l2cache.overall_misses::cpu.data 126 #
|
|||
system.cpu.l2cache.overall_misses::total 401 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20756000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 20756000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6584500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6584500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20756000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9917500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30673500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20756000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9917500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30673500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20751000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 20751000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6579500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6579500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 20751000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9912500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 30663500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 20751000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9912500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 30663500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -1087,16 +1087,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76492.518703 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76492.518703 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75458.181818 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75458.181818 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78327.380952 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78327.380952 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76467.581047 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76467.581047 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -1125,16 +1125,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 121
|
|||
system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18006000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18006000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5464000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5464000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18006000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8377000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26383000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18006000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8377000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26383000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18001000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18001000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5459000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5459000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18001000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26373000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18001000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8372000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26373000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -1149,17 +1149,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65458.181818 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65458.181818 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69101.265823 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69101.265823 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 441 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
|
||||
|
|
@ -1173,14 +1179,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000018 # Number of seconds simulated
|
||||
sim_ticks 17777000 # Number of ticks simulated
|
||||
final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 17778000 # Number of ticks simulated
|
||||
final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 63242 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 74054 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 244740900 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 307828 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 58925 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 69000 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 228057572 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 310616 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu
|
|||
system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 406 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 407 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 17763500 # Total gap between requests
|
||||
system.physmem.totGap 17764500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -204,15 +204,15 @@ system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # By
|
|||
system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3130500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 3121500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.45 # Data bus utilization in percentage
|
||||
|
|
@ -224,35 +224,35 @@ system.physmem.readRowHits 340 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 43644.96 # Average gap between requests
|
||||
system.physmem.avgGap 43647.42 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 905.346375 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states
|
||||
system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 905.276555 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 805.767883 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 805.747987 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 2336 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted
|
||||
|
|
@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 35555 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 35557 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 5038 # Number of cycles decode is running
|
||||
system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 5040 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 4094 # Number of cycles rename is running
|
||||
system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 4096 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename
|
||||
system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename
|
||||
system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
|
|
@ -466,90 +466,90 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
|
|||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 7146 # Type of FU issued
|
||||
system.cpu.iq.rate 0.200984 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.FU_type_0::total 7148 # Type of FU issued
|
||||
system.cpu.iq.rate 0.201029 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed
|
||||
|
|
@ -561,9 +561,9 @@ system.cpu.iew.iewIdleCycles 0 # Nu
|
|||
system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
|
||||
|
|
@ -572,7 +572,7 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu
|
|||
system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions
|
||||
system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
|
|
@ -580,35 +580,35 @@ system.cpu.iew.exec_nop 14 # nu
|
|||
system.cpu.iew.exec_refs 2427 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1272 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1023 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.189622 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 6567 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2975 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 5372 # num instructions consuming a value
|
||||
system.cpu.iew.exec_rate 0.189667 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 6569 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2977 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 5378 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back
|
||||
system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 4592 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -655,32 +655,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 5378 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 22320 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 16439 # The number of ROB writes
|
||||
system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 22343 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 16451 # The number of ROB writes
|
||||
system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4592 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 6718 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 3745 # number of integer regfile writes
|
||||
system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 6720 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 3747 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
||||
system.cpu.cc_regfile_reads 23959 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_reads 23965 # number of cc regfile reads
|
||||
system.cpu.cc_regfile_writes 2898 # number of cc regfile writes
|
||||
system.cpu.misc_regfile_reads 2607 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
|
||||
system.cpu.dcache.tags.replacements 1 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
|
||||
|
|
@ -709,16 +709,16 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n
|
|||
system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 358 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -741,16 +741,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.158899
|
|||
system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -777,14 +777,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143
|
|||
system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5839000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5839000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8293500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -793,71 +793,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57245.098039 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57245.098039 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 42 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 136.212207 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 3460 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11.728814 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 7941 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 3459 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 7943 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 7943 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 3460 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 3460 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 3460 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 3460 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 364 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21574493 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 21574493 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 21574493 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 21574493 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 21574493 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 21574493 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 3824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 3824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 3824 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 3824 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 3824 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 3824 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095188 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.095188 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.095188 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.095188 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.095188 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.095188 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59270.585165 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 59270.585165 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 59270.585165 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 59270.585165 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 8439 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 94.820225 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -873,24 +873,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 296
|
|||
system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18788993 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 18788993 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18788993 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 18788993 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18788993 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 18788993 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077406 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.077406 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.077406 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63476.327703 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63476.327703 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified
|
||||
|
|
@ -899,18 +899,18 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu
|
|||
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
||||
system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 192.769134 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.484820 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 45.082970 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.201345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008452 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.011766 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
|
||||
|
|
@ -947,16 +947,16 @@ system.cpu.l2cache.overall_misses::cpu.data 113 #
|
|||
system.cpu.l2cache.overall_misses::total 386 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18323500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 18323500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 18323500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 26192500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 18323500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 26192500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 296 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -983,16 +983,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67119.047619 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67119.047619 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67856.217617 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67856.217617 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -1030,17 +1030,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625
|
|||
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
||||
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -1060,18 +1060,24 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873
|
|||
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution
|
||||
|
|
@ -1087,15 +1093,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 64 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
|
|
@ -1122,9 +1128,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 407 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 12.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
sim_ticks 25816500 # Number of ticks simulated
|
||||
final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 25848500 # Number of ticks simulated
|
||||
final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 428411 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 499438 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2416370273 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308620 # Number of bytes of host memory used
|
||||
host_inst_rate 341128 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 397821 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1927554064 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 312280 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4566 # Number of instructions simulated
|
||||
sim_ops 5330 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu
|
|||
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 51633 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 51697 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4566 # Number of instructions committed
|
||||
|
|
@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu
|
|||
system.cpu.num_load_insts 1027 # Number of load instructions
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1008 # Number of branches fetched
|
||||
|
|
@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5391 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
|
||||
|
|
@ -242,14 +242,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n
|
|||
system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 141 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -270,14 +270,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016
|
|||
system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
|
|||
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
|
||||
|
|
@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n
|
|||
system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 241 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
|
||||
|
|
@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323
|
|||
system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241
|
|||
system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy
|
||||
|
|
@ -547,6 +547,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
|
|
@ -560,14 +566,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
|||
sim_ticks 22451000 # Number of ticks simulated
|
||||
final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 41665 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 41658 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 187549895 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 287968 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 76638 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 76622 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 344943613 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294148 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 4986 # Number of instructions simulated
|
||||
sim_ops 4986 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -912,6 +912,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
|
|
@ -926,15 +932,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 489 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu
|
|||
sim_ticks 30902500 # Number of ticks simulated
|
||||
final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 339265 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 338999 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1861147916 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 289452 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_inst_rate 459853 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 459290 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2521006690 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291832 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5624 # Number of instructions simulated
|
||||
sim_ops 5624 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -435,6 +435,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
|
|
@ -449,15 +455,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 445 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000020 # Number of seconds simulated
|
||||
sim_ticks 19922000 # Number of ticks simulated
|
||||
final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 19923000 # Number of ticks simulated
|
||||
final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 38523 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38518 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 132470471 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 286104 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 93968 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 93947 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 323084408 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291680 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu
|
|||
system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 444 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 444 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 19782500 # Total gap between requests
|
||||
system.physmem.totGap 19783500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # By
|
|||
system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3750750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 3746750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 11.14 # Data bus utilization in percentage
|
||||
|
|
@ -220,7 +220,7 @@ system.physmem.readRowHits 359 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 44555.18 # Average gap between requests
|
||||
system.physmem.avgGap 44557.43 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -245,7 +245,7 @@ system.physmem_1.actBackEnergy 7628310 # En
|
|||
system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 748.283278 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states
|
||||
|
|
@ -279,7 +279,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 9 # Number of system calls
|
||||
system.cpu.numCycles 39845 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 39847 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
@ -310,8 +310,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 1924 # Number of cycles decode is running
|
||||
|
|
@ -437,7 +437,7 @@ system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 8840 # Type of FU issued
|
||||
system.cpu.iq.rate 0.221860 # Inst issue rate
|
||||
system.cpu.iq.rate 0.221849 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 201 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads
|
||||
|
|
@ -481,13 +481,13 @@ system.cpu.iew.exec_nop 0 # nu
|
|||
system.cpu.iew.exec_refs 3121 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1355 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1414 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.212950 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.212939 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 8147 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 4452 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 7114 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit
|
||||
|
|
@ -559,24 +559,24 @@ system.cpu.commit.bw_lim_events 110 # nu
|
|||
system.cpu.rob.rob_reads 21420 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21108 # The number of ROB writes
|
||||
system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 5792 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 13451 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7138 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 25 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 64.587343 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 64.587343 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id
|
||||
|
|
@ -601,14 +601,14 @@ system.cpu.dcache.demand_misses::cpu.data 433 # n
|
|||
system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 433 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7902500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7902500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31812496 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31812496 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31812496 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31812496 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -625,14 +625,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.163643
|
|||
system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 73469.967667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 73469.967667 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
|
||||
|
|
@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 103
|
|||
system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4528500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4528500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8534998 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8534998 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8534998 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8534998 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -673,22 +673,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 168.966654 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 168.966654 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
|
||||
|
|
@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 433 # n
|
|||
system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 433 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32237500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32237500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32237500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32237500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32237500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32237500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses
|
||||
|
|
@ -727,12 +727,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.237651
|
|||
system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 74451.501155 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 74451.501155 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
||||
|
|
@ -753,39 +753,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350
|
|||
system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26589500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 26589500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26589500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 26589500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26589500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 26589500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75970 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75970 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 199.677803 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770664 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.907139 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses
|
||||
|
|
@ -813,16 +813,16 @@ system.cpu.l2cache.overall_misses::cpu.data 101 #
|
|||
system.cpu.l2cache.overall_misses::total 445 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26002500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 26002500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 26002500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34357500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 26002500 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34357500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -849,16 +849,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -881,16 +881,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 101
|
|||
system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -905,17 +905,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution
|
||||
|
|
@ -929,14 +935,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 27800500 # Number of ticks simulated
|
||||
final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 27803500 # Number of ticks simulated
|
||||
final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 428112 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 427631 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2229390537 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290104 # Number of bytes of host memory used
|
||||
host_inst_rate 506128 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 505504 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2635153066 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292480 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu
|
|||
system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 55601 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 55607 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5327 # Number of instructions committed
|
||||
|
|
@ -50,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu
|
|||
system.cpu.num_load_insts 723 # Number of load instructions
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1121 # Number of branches fetched
|
||||
|
|
@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5370 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
|
||||
|
|
@ -120,14 +120,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n
|
|||
system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 135 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -144,14 +144,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
|
|||
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -184,24 +184,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
|
||||
|
|
@ -220,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n
|
|||
system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 257 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
|
||||
|
|
@ -238,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850
|
|||
system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -258,33 +258,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257
|
|||
system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy
|
||||
|
|
@ -421,6 +421,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
|
||||
|
|
@ -434,14 +440,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000021 # Number of seconds simulated
|
||||
sim_ticks 20817000 # Number of ticks simulated
|
||||
final_tick 20817000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 20818000 # Number of ticks simulated
|
||||
final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31285 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 56673 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 121026192 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306568 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_inst_rate 48919 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 88616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 189245943 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313416 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu
|
|||
system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 415 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 848537253 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 427343037 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1275880290 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 848537253 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 848537253 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 848537253 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 427343037 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1275880290 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 415 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 20721000 # Total gap between requests
|
||||
system.physmem.totGap 20722000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -206,9 +206,9 @@ system.physmem.totBusLat 2075000 # To
|
|||
system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1275.88 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1275.88 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 9.97 # Data bus utilization in percentage
|
||||
|
|
@ -220,7 +220,7 @@ system.physmem.readRowHits 309 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 49930.12 # Average gap between requests
|
||||
system.physmem.avgGap 49932.53 # Average gap between requests
|
||||
system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -262,7 +262,7 @@ system.cpu.branchPred.RASInCorrect 86 # Nu
|
|||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 41635 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 41637 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
@ -293,8 +293,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.077675 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.351555 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 3206 # Number of cycles decode is running
|
||||
|
|
@ -417,7 +417,7 @@ system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 17161 # Type of FU issued
|
||||
system.cpu.iq.rate 0.412177 # Inst issue rate
|
||||
system.cpu.iq.rate 0.412157 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 212 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads
|
||||
|
|
@ -461,13 +461,13 @@ system.cpu.iew.exec_nop 0 # nu
|
|||
system.cpu.iew.exec_refs 3175 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1626 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1262 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.390657 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.390638 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 15771 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 10637 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 16589 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.378792 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit
|
||||
|
|
@ -539,13 +539,13 @@ system.cpu.commit.bw_lim_events 255 # nu
|
|||
system.cpu.rob.rob_reads 41158 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 42744 # The number of ROB writes
|
||||
system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 18910 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 5380 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 7.738848 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.738848 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.129218 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.129218 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 20871 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 12651 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
||||
|
|
@ -554,12 +554,12 @@ system.cpu.cc_regfile_writes 4880 # nu
|
|||
system.cpu.misc_regfile_reads 7277 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 81.971685 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 81.971685 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id
|
||||
|
|
@ -664,17 +664,17 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 130.298609 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 130.304167 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 130.298609 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.063622 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.063622 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 130.304167 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.063625 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.063625 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4427 # Number of data accesses
|
||||
|
|
@ -690,12 +690,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n
|
|||
system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 369 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28131500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28131500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28131500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28131500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28131500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28131500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28132500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28132500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28132500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28132500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28132500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28132500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses
|
||||
|
|
@ -708,12 +708,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.177831
|
|||
system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76237.127371 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76237.127371 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76237.127371 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76237.127371 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76239.837398 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76239.837398 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76239.837398 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76239.837398 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -734,33 +734,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 277
|
|||
system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22318000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22318000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22318000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22318000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22318000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22318000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22319000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22319000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22319000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22319000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22319000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22319000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80570.397112 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80570.397112 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80574.007220 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80574.007220 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 162.374270 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 162.380689 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.338432 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 32.035838 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.343988 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 32.036700 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy
|
||||
|
|
@ -893,6 +893,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
|
||||
|
|
@ -906,14 +912,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 416 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 28358500 # Number of ticks simulated
|
||||
final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 28359500 # Number of ticks simulated
|
||||
final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 304372 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 550952 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1601632215 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308112 # Number of bytes of host memory used
|
||||
host_inst_rate 279983 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 506758 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1473373857 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311136 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu
|
|||
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 56717 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 56719 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
|
|
@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu
|
|||
system.cpu.num_load_insts 1053 # Number of load instructions
|
||||
system.cpu.num_store_insts 935 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1208 # Number of branches fetched
|
||||
|
|
@ -93,14 +93,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 9748 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 80.791087 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.791087 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019724 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019724 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
|
||||
|
|
@ -197,14 +197,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 105.540319 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.540319 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
|
||||
|
|
@ -223,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n
|
|||
system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 228 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses
|
||||
|
|
@ -241,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217
|
|||
system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -261,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228
|
|||
system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12270500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12270500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12270500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12270500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12270500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12270500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53817.982456 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53817.982456 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 134.006917 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.536457 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.470460 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy
|
||||
|
|
@ -420,6 +420,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
|
||||
|
|
@ -433,14 +439,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
|
|||
sim_ticks 24832500 # Number of ticks simulated
|
||||
final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 45282 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45279 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 88223588 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290360 # Number of bytes of host memory used
|
||||
host_seconds 0.28 # Real time elapsed on the host
|
||||
host_inst_rate 79921 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79915 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 155707227 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297588 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 12744 # Number of instructions simulated
|
||||
sim_ops 12744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -298,59 +298,59 @@ system.cpu.numCycles 49666 # nu
|
|||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 39559 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Insts 39551 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 6978 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 10834 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 10833 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.CacheLines 5404 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.436733 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.801651 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.436442 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.801385 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 20750 75.36% 75.36% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 584 2.12% 77.48% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 20751 75.37% 75.37% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 584 2.12% 77.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 571 2.07% 83.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 571 2.07% 83.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 560 2.03% 88.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 3127 11.36% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 560 2.03% 88.65% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 3126 11.35% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.796501 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 37298 # Number of cycles decode is idle
|
||||
system.cpu.fetch.rate 0.796340 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 37297 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 5112 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 613 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.UnblockCycles 614 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 32201 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 32206 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 37873 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 37872 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 5149 # Number of cycles rename is running
|
||||
system.cpu.rename.RunCycles 5150 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 30276 # Number of instructions processed by rename
|
||||
system.cpu.rename.RenamedInsts 30281 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full
|
||||
system.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full
|
||||
system.cpu.rename.RenamedOperands 22817 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 37709 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 37691 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 22821 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 37713 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 37695 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 13677 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 60 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer
|
||||
|
|
@ -847,12 +847,12 @@ system.cpu.dcache.no_allocate_misses 0 # Nu
|
|||
system.cpu.icache.tags.replacements::0 8 # number of replacements
|
||||
system.cpu.icache.tags.replacements::1 0 # number of replacements
|
||||
system.cpu.icache.tags.replacements::total 8 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 317.015033 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 317.014953 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4463 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 634 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 7.039432 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 317.015033 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 317.014953 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.154792 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.154792 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id
|
||||
|
|
@ -873,12 +873,12 @@ system.cpu.icache.demand_misses::cpu.inst 935 # n
|
|||
system.cpu.icache.demand_misses::total 935 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 935 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 935 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 70145997 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 70145997 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 70145997 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 70145997 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 70145997 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 70145997 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 70147997 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 70147997 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 70147997 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 70147997 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 70147997 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 70147997 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5398 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5398 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5398 # number of demand (read+write) accesses
|
||||
|
|
@ -891,12 +891,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.173212
|
|||
system.cpu.icache.demand_miss_rate::total 0.173212 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.173212 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.173212 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75022.456684 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75022.456684 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75022.456684 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75022.456684 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75022.456684 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75022.456684 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75024.595722 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75024.595722 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75024.595722 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75024.595722 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 3484 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 77 # number of cycles access was blocked
|
||||
|
|
@ -917,24 +917,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 634
|
|||
system.cpu.icache.demand_mshr_misses::total 634 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 634 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51559499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 51559499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51559499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 51559499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51559499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 51559499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51561499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 51561499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51561499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 51561499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51561499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 51561499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117451 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.117451 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.117451 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81324.130915 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81324.130915 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81324.130915 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 81324.130915 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81324.130915 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 81324.130915 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81327.285489 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81327.285489 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
|
||||
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
|
||||
|
|
@ -1078,6 +1078,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 986 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
|
||||
|
|
@ -1092,14 +1098,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 62592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 986 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002028 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.045015 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 986 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 984 99.80% 99.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 986 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000027 # Number of seconds simulated
|
||||
sim_ticks 26943000 # Number of ticks simulated
|
||||
final_tick 26943000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 26944000 # Number of ticks simulated
|
||||
final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 30305 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 30304 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 56555572 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 288252 # Number of bytes of host memory used
|
||||
host_seconds 0.48 # Real time elapsed on the host
|
||||
host_inst_rate 95332 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 95323 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 177899852 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294468 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21888 # Nu
|
|||
system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 489 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 812381695 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 349181606 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1161563300 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 812381695 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 812381695 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 812381695 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 349181606 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1161563300 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 812351544 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 349168646 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1161520190 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 812351544 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 812351544 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 812351544 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 349168646 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1161520190 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 489 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 26890000 # Total gap between requests
|
||||
system.physmem.totGap 26891000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -206,9 +206,9 @@ system.physmem.totBusLat 2445000 # To
|
|||
system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1161.56 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBW 1161.52 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1161.56 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1161.52 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 9.07 # Data bus utilization in percentage
|
||||
|
|
@ -220,7 +220,7 @@ system.physmem.readRowHits 409 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 54989.78 # Average gap between requests
|
||||
system.physmem.avgGap 54991.82 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -245,7 +245,7 @@ system.physmem_1.actBackEnergy 15637950 # En
|
|||
system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 817.549616 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 2039000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::IDLE 2040000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states
|
||||
|
|
@ -261,14 +261,14 @@ system.cpu.branchPred.usedRAS 554 # Nu
|
|||
system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 53887 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 53889 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 13793 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 13792 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 15451 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 15452 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps
|
||||
|
|
@ -291,8 +291,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.148941 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.689962 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.148936 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.689937 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 6549 # Number of cycles decode is running
|
||||
|
|
@ -413,7 +413,7 @@ system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 20835 # Type of FU issued
|
||||
system.cpu.iq.rate 0.386642 # Inst issue rate
|
||||
system.cpu.iq.rate 0.386628 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads
|
||||
|
|
@ -457,13 +457,13 @@ system.cpu.iew.exec_nop 1117 # nu
|
|||
system.cpu.iew.exec_refs 5240 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 4296 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1999 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.371370 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.371356 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 19648 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 19408 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 9326 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 12017 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.360161 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.360148 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.776067 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit
|
||||
|
|
@ -535,24 +535,24 @@ system.cpu.commit.bw_lim_events 290 # nu
|
|||
system.cpu.rob.rob_reads 52271 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 49405 # The number of ROB writes
|
||||
system.cpu.timesIdled 197 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 22477 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 22479 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 14436 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 3.732821 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.732821 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.267894 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.267894 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 3.732959 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.732959 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.267884 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.267884 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 32029 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 17799 # number of integer regfile writes
|
||||
system.cpu.misc_regfile_reads 6992 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 98.068517 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 98.069813 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 4030 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.602740 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.068517 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 98.069813 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023943 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023943 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
|
|
@ -663,14 +663,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78384.353741
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 190.286110 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 190.290590 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5576 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 344 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 16.209302 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 190.286110 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.092913 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.092913 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 190.290590 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.092915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.092915 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
|
||||
|
|
@ -689,12 +689,12 @@ system.cpu.icache.demand_misses::cpu.inst 519 # n
|
|||
system.cpu.icache.demand_misses::total 519 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 519 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 519 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 36198500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 36198500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 36198500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 36198500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 36198500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 36198500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 36200500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 36200500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 36200500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 36200500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 36200500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 36200500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6095 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6095 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6095 # number of demand (read+write) accesses
|
||||
|
|
@ -707,12 +707,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.085152
|
|||
system.cpu.icache.demand_miss_rate::total 0.085152 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.085152 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.085152 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69746.628131 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69746.628131 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69746.628131 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69746.628131 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69750.481696 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 69750.481696 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 69750.481696 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 69750.481696 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -733,33 +733,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 344
|
|||
system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26530000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 26530000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26530000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 26530000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26530000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 26530000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26532000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 26532000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26532000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 26532000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26532000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 26532000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.056440 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.056440 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.056440 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77122.093023 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77122.093023 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77127.906977 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77127.906977 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 223.995330 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 224.000415 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 405 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.004938 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.659398 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.335932 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.663901 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.336514 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005788 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001048 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006836 # Average percentage of cache occupancy
|
||||
|
|
@ -892,6 +892,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 491 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
|
||||
|
|
@ -905,14 +911,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004073 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.063757 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 489 99.59% 99.59% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2 0.41% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000041 # Number of seconds simulated
|
||||
sim_ticks 41368500 # Number of ticks simulated
|
||||
final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 41370500 # Number of ticks simulated
|
||||
final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 372083 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 371955 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1014555487 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 290028 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 454115 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 453939 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1238118753 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292408 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
|||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 82737 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 82741 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 15162 # Number of instructions committed
|
||||
|
|
@ -50,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu
|
|||
system.cpu.num_load_insts 2231 # Number of load instructions
|
||||
system.cpu.num_store_insts 1452 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 3363 # Number of branches fetched
|
||||
|
|
@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 15207 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 97.989824 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.989824 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
|
||||
|
|
@ -198,12 +198,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 153.774107 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 153.774107 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
|
||||
|
|
@ -224,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n
|
|||
system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 280 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
|
||||
|
|
@ -242,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411
|
|||
system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -262,33 +262,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280
|
|||
system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15036500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15036500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15036500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15036500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15036500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15036500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53701.785714 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53701.785714 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53701.785714 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53701.785714 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.609803 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.092235 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517568 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy
|
||||
|
|
@ -421,6 +421,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561
|
|||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
|
||||
|
|
@ -434,14 +440,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000062 # Number of seconds simulated
|
||||
sim_ticks 61608000 # Number of ticks simulated
|
||||
final_tick 61608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 61610000 # Number of ticks simulated
|
||||
final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 214452 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 214360 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2049936831 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 674692 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_inst_rate 402374 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 402048 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3843418590 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 682268 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 6440 # Number of instructions simulated
|
||||
sim_ops 6440 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu
|
|||
system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.mem_ctrl.bw_read::cpu.inst 288793663 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::cpu.data 174522789 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::total 463316452 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 288793663 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_inst_read::total 288793663 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::cpu.inst 288793663 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::cpu.data 174522789 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::total 463316452 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.mem_ctrl.readReqs 446 # Number of read requests accepted
|
||||
system.mem_ctrl.writeReqs 0 # Number of write requests accepted
|
||||
system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe
|
|||
system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.mem_ctrl.totGap 61358000 # Total gap between requests
|
||||
system.mem_ctrl.totGap 61360000 # Total gap between requests
|
||||
system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -205,9 +205,9 @@ system.mem_ctrl.totBusLat 2230000 # To
|
|||
system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrl.avgRdBW 463.32 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgRdBWSys 463.32 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage
|
||||
|
|
@ -219,7 +219,7 @@ system.mem_ctrl.readRowHits 340 # Nu
|
|||
system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads
|
||||
system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.mem_ctrl.avgGap 137573.99 # Average gap between requests
|
||||
system.mem_ctrl.avgGap 137578.48 # Average gap between requests
|
||||
system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined
|
||||
system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -282,7 +282,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 61608 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 61610 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6440 # Number of instructions committed
|
||||
|
|
@ -301,7 +301,7 @@ system.cpu.num_mem_refs 2063 # nu
|
|||
system.cpu.num_load_insts 1195 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 61608 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 61610 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1054 # Number of branches fetched
|
||||
|
|
@ -341,14 +341,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6450 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 104.300595 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 104.300595 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.101856 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.101856 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
|
||||
|
|
@ -445,14 +445,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 62 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 113.923956 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 113.923956 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.445015 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.445015 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
|
||||
|
|
@ -471,12 +471,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n
|
|||
system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 281 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28179000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28179000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28179000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28179000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28179000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28179000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses
|
||||
|
|
@ -489,12 +489,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043559
|
|||
system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100281.138790 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 100281.138790 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 100281.138790 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 100281.138790 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -509,25 +509,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281
|
|||
system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27617000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 27617000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27617000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 27617000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27617000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 27617000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98281.138790 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98281.138790 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
|
||||
system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.l2bus.trans_dist::ReadResp 376 # Transaction distribution
|
||||
system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
|
|
@ -541,14 +547,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side
|
|||
system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 511 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 511 100.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 511 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks)
|
||||
|
|
@ -558,16 +564,16 @@ system.l2bus.respLayer0.utilization 1.4 # La
|
|||
system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
|
||||
system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.l2cache.tags.replacements 0 # number of replacements
|
||||
system.l2cache.tags.tagsinuse 185.387550 # Cycle average of tags in use
|
||||
system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use
|
||||
system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
|
||||
system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks.
|
||||
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2cache.tags.occ_blocks::cpu.inst 128.677366 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_blocks::cpu.data 56.710184 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_percent::cpu.inst 0.031415 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::total 0.045261 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
|
||||
system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
||||
system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000050 # Nu
|
|||
sim_ticks 49855000 # Number of ticks simulated
|
||||
final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79800 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 92294 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 797317444 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 690160 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 351391 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 406109 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3506224066 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 699088 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4988 # Number of instructions simulated
|
||||
sim_ops 5770 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -199,12 +199,12 @@ system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # B
|
|||
system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation
|
||||
system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation
|
||||
system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing
|
||||
system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing
|
||||
system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers
|
||||
system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst
|
||||
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst
|
||||
system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -226,28 +226,28 @@ system.mem_ctrl_0.preEnergy 189750 # En
|
|||
system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ)
|
||||
system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW)
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states
|
||||
system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ)
|
||||
system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW)
|
||||
system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states
|
||||
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
|
||||
system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
|
||||
system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ)
|
||||
system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ)
|
||||
system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ)
|
||||
system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW)
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states
|
||||
system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ)
|
||||
system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ)
|
||||
system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ)
|
||||
system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW)
|
||||
system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states
|
||||
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -427,14 +427,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5831 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
|
||||
|
|
@ -461,14 +461,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n
|
|||
system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 142 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -489,14 +489,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899
|
|||
system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -513,14 +513,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142
|
|||
system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -529,24 +529,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 70 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
|
||||
|
|
@ -565,12 +565,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n
|
|||
system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 249 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses
|
||||
|
|
@ -583,12 +583,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523
|
|||
system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -603,25 +603,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249
|
|||
system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter.
|
||||
system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.l2bus.trans_dist::ReadResp 348 # Transaction distribution
|
||||
system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
|
|
@ -635,14 +641,14 @@ system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side
|
|||
system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 461 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 461 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks)
|
||||
|
|
@ -652,16 +658,16 @@ system.l2bus.respLayer0.utilization 1.5 # La
|
|||
system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks)
|
||||
system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.l2cache.tags.replacements 0 # number of replacements
|
||||
system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use
|
||||
system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use
|
||||
system.l2cache.tags.total_refs 100 # Total number of references to valid blocks.
|
||||
system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks.
|
||||
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor
|
||||
system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy
|
||||
system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
|
||||
system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
||||
system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
|
||||
|
|
@ -688,17 +694,17 @@ system.l2cache.demand_misses::total 351 # nu
|
|||
system.l2cache.overall_misses::cpu.inst 225 # number of overall misses
|
||||
system.l2cache.overall_misses::cpu.data 126 # number of overall misses
|
||||
system.l2cache.overall_misses::total 351 # number of overall misses
|
||||
system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles
|
||||
system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles
|
||||
system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles
|
||||
system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles
|
||||
system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles
|
||||
system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles
|
||||
system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles
|
||||
system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles
|
||||
system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles
|
||||
system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles
|
||||
system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses)
|
||||
|
|
@ -721,17 +727,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi
|
|||
system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses
|
||||
system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses
|
||||
system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses
|
||||
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency
|
||||
system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency
|
||||
system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency
|
||||
system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency
|
||||
system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency
|
||||
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency
|
||||
system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency
|
||||
system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency
|
||||
system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
|
||||
system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
|
||||
system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency
|
||||
system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency
|
||||
system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -751,17 +757,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu
|
|||
system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
|
||||
system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses
|
||||
system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles
|
||||
system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses
|
||||
|
|
@ -773,17 +779,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 #
|
|||
system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses
|
||||
system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses
|
||||
system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency
|
||||
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
|
||||
system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency
|
||||
system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency
|
||||
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadResp 308 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue