1602 lines
190 KiB
Plaintext
1602 lines
190 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 51.811426 # Number of seconds simulated
|
|
sim_ticks 51811426272500 # Number of ticks simulated
|
|
final_tick 51811426272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 673469 # Simulator instruction rate (inst/s)
|
|
host_op_rate 791455 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 42067688868 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 720644 # Number of bytes of host memory used
|
|
host_seconds 1231.62 # Real time elapsed on the host
|
|
sim_insts 829457901 # Number of instructions simulated
|
|
sim_ops 974772546 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu.dtb.walker 136896 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.itb.walker 149440 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.inst 4672052 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 65294216 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::realview.ide 405248 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 70657852 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 4672052 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 4672052 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 61426304 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 61446884 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.dtb.walker 2139 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.itb.walker 2335 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.inst 113408 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 1020235 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::realview.ide 6332 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 1144449 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 959786 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 962359 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu.dtb.walker 2642 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.itb.walker 2884 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.inst 90174 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 1260228 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::realview.ide 7822 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 1363750 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 90174 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 90174 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 1185574 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 1185972 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 1185574 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.dtb.walker 2642 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.itb.walker 2884 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 90174 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 1260625 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::realview.ide 7822 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 2549722 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 1144449 # Number of read requests accepted
|
|
system.physmem.writeReqs 962359 # Number of write requests accepted
|
|
system.physmem.readBursts 1144449 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 962359 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 73193536 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 51200 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 61446016 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 70657852 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 61446884 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 800 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 140011 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 69107 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 74090 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 73242 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 69271 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 67156 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 73972 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 66324 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 66322 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 69640 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 111279 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 69249 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 69472 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 65127 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 68635 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 67352 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 63411 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 57809 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 62464 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 62675 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 60788 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 58616 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 63580 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 58138 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 59016 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 60306 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 62192 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 60798 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 61491 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 56659 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 60390 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 59031 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 56141 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 31 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 51811423590500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 43101 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 13 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 2 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 1101333 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 1 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 959786 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 1115953 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 21968 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 419 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 345 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 482 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 537 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 511 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 1143 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 670 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 346 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 171 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 111 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 70 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 13692 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 16531 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 54388 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 55199 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 56950 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 56683 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 57911 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 58143 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 59332 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 58934 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 59348 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 63120 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 58684 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 57432 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 58229 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 56389 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 55725 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 55034 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 972 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 787 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 470 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 482 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 427 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 346 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 338 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 341 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 291 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 285 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 226 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 210 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 257 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 240 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 272 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 177 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 172 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 104 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 451899 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 297.940982 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 172.093990 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 328.963355 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 180364 39.91% 39.91% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 110273 24.40% 64.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 39544 8.75% 73.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 23126 5.12% 78.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 15873 3.51% 81.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 11951 2.64% 84.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 9990 2.21% 86.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 8720 1.93% 88.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 52058 11.52% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 451899 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 54067 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 21.152052 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 336.366692 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-4095 54065 100.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 54067 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 54067 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 17.757486 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 17.129918 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 7.530147 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 51801 95.81% 95.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 269 0.50% 96.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 70 0.13% 96.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 325 0.60% 97.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 45 0.08% 97.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 331 0.61% 97.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 216 0.40% 98.13% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 22 0.04% 98.17% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 68 0.13% 98.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 136 0.25% 98.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 27 0.05% 98.60% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 36 0.07% 98.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 464 0.86% 99.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 28 0.05% 99.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 27 0.05% 99.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 146 0.27% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 11 0.02% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 2 0.00% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 2 0.00% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 21 0.04% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 54067 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 14370740504 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 35814159254 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 5718245000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12565.69 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31315.69 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.19 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 27.25 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 921781 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 730062 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 76.04 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 24592380.32 # Average gap between requests
|
|
system.physmem.pageHitRate 78.52 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 1754978400 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 957577500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 4363975200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 3130397280 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 3384070123200 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 1298615760765 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 29947715800500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 34640608612845 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 668.590209 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 49820119093739 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 1730097200000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 261204441261 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 1661378040 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 906505875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 4556448000 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 3091011840 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3384070123200 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 1293042304755 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 29952604797000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 34639932568710 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.577161 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 49828251258491 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1730097200000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 253077157009 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 184770 # Table walker walks requested
|
|
system.cpu.dtb.walker.walksLong 184770 # Table walker walks initiated with long descriptors
|
|
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12350 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144149 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting
|
|
system.cpu.dtb.walker.walkWaitTime::samples 184753 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::mean 0.216505 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::stdev 70.872440 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::0-2047 184751 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::total 184753 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::samples 156516 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::mean 24678.339595 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::gmean 20707.909662 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::stdev 17878.729982 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::0-65535 155309 99.23% 99.23% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::131072-196607 1041 0.67% 99.89% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::196608-262143 36 0.02% 99.92% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::327680-393215 20 0.01% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::393216-458751 39 0.02% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::total 156516 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walksPending::samples -8954848740 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::mean 1.174586 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::0 1563388704 -17.46% -17.46% # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::1 -10518237444 117.46% 100.00% # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::total -8954848740 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walkPageSizes::4K 144150 92.11% 92.11% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::2M 12350 7.89% 100.00% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::total 156500 # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 184770 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 184770 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156500 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156500 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 341270 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 156218154 # DTB read hits
|
|
system.cpu.dtb.read_misses 137197 # DTB read misses
|
|
system.cpu.dtb.write_hits 141774250 # DTB write hits
|
|
system.cpu.dtb.write_misses 47573 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 37807 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 70344 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 7209 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 18555 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 156355351 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 141821823 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 297992404 # DTB hits
|
|
system.cpu.dtb.misses 184770 # DTB misses
|
|
system.cpu.dtb.accesses 298177174 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 119016 # Table walker walks requested
|
|
system.cpu.itb.walker.walksLong 119016 # Table walker walks initiated with long descriptors
|
|
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.itb.walker.walksLongTerminationLevel::Level3 107588 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.itb.walker.walkWaitTime::samples 119016 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::0 119016 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::total 119016 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkCompletionTime::samples 108698 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::mean 28702.878618 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::gmean 24805.101383 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::stdev 21517.827982 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::0-65535 107219 98.64% 98.64% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.00% 98.64% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::131072-196607 1293 1.19% 99.83% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::196608-262143 35 0.03% 99.86% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::262144-327679 66 0.06% 99.92% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::327680-393215 33 0.03% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::393216-458751 38 0.03% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::total 108698 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walksPending::samples 1449242704 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::0 1449242704 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::total 1449242704 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walkPageSizes::4K 107588 98.98% 98.98% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::2M 1110 1.02% 100.00% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::total 108698 # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119016 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 119016 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108698 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 108698 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 227714 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 829969192 # ITB inst hits
|
|
system.cpu.itb.inst_misses 119016 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 37807 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 50385 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 830088208 # ITB inst accesses
|
|
system.cpu.itb.hits 829969192 # DTB hits
|
|
system.cpu.itb.misses 119016 # DTB misses
|
|
system.cpu.itb.accesses 830088208 # DTB accesses
|
|
system.cpu.numCycles 103622852545 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 829457901 # Number of instructions committed
|
|
system.cpu.committedOps 974772546 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 896189211 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 901491 # Number of float alu accesses
|
|
system.cpu.num_func_calls 49868985 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 125722281 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 896189211 # number of integer instructions
|
|
system.cpu.num_fp_insts 901491 # number of float instructions
|
|
system.cpu.num_int_register_reads 1296374406 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 710181687 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 1455753 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 759888 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 214623564 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 214015228 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 297970911 # number of memory refs
|
|
system.cpu.num_load_insts 156208355 # Number of load instructions
|
|
system.cpu.num_store_insts 141762556 # Number of store instructions
|
|
system.cpu.num_idle_cycles 100538268245.312057 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 3084584299.687941 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.029767 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.970233 # Percentage of idle cycles
|
|
system.cpu.Branches 185080610 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 675027682 69.21% 69.21% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 2118642 0.22% 69.43% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 97301 0.01% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 156208355 16.02% 85.47% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 141762556 14.53% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 975326961 # Class of executed instruction
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 18851 # number of quiesce instructions executed
|
|
system.cpu.dcache.tags.replacements 9274254 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 288519025 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9274766 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 31.107957 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 5829979500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.942797 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1200910515 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1200910515 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 146286950 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 146286950 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 134627740 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 134627740 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 371143 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 371143 # number of SoftPFReq hits
|
|
system.cpu.dcache.WriteLineReq_hits::cpu.data 331538 # number of WriteLineReq hits
|
|
system.cpu.dcache.WriteLineReq_hits::total 331538 # number of WriteLineReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3288519 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3288519 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3571476 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 3571476 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 280914690 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 280914690 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 281285833 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 281285833 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 4843075 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 4843075 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1971266 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1971266 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 1110209 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 1110209 # number of SoftPFReq misses
|
|
system.cpu.dcache.WriteLineReq_misses::cpu.data 1222439 # number of WriteLineReq misses
|
|
system.cpu.dcache.WriteLineReq_misses::total 1222439 # number of WriteLineReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 284576 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 284576 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 6814341 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 6814341 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 7924550 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 7924550 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 83223241000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 83223241000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 66964103500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 66964103500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73311177500 # number of WriteLineReq miss cycles
|
|
system.cpu.dcache.WriteLineReq_miss_latency::total 73311177500 # number of WriteLineReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4361265000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 4361265000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 247000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 247000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 150187344500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 150187344500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 150187344500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 150187344500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 151130025 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 151130025 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 136599006 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 136599006 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481352 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 1481352 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1553977 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteLineReq_accesses::total 1553977 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3573095 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3573095 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3571479 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3571479 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 287729031 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 287729031 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 289210383 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 289210383 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032046 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.032046 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014431 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.014431 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.749457 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.749457 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786652 # miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.WriteLineReq_miss_rate::total 0.786652 # miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079644 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079644 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.023683 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.023683 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.027401 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.027401 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17183.967004 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 17183.967004 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33970.100179 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 33970.100179 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 59971.235784 # average WriteLineReq miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 59971.235784 # average WriteLineReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15325.484229 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15325.484229 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82333.333333 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82333.333333 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22039.892706 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 22039.892706 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18952.160627 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 18952.160627 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 7273356 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 7273356 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23715 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 23715 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21271 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 21271 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68399 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 68399 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 44986 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 44986 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 44986 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 44986 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4819360 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 4819360 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1949995 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1949995 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1108464 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1108464 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1222439 # number of WriteLineReq MSHR misses
|
|
system.cpu.dcache.WriteLineReq_mshr_misses::total 1222439 # number of WriteLineReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 216177 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 216177 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 6769355 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 6769355 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 7877819 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 7877819 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 77027858500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 77027858500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 64047484500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 64047484500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21144827000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21144827000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72088738500 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72088738500 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2970895000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2970895000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 244000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 244000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 141075343000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 141075343000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162220170000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 162220170000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5832027500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5832027500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5823842500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5823842500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11655870000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11655870000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031889 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031889 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014275 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014275 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.748279 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.748279 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786652 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786652 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060501 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060501 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023527 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.023527 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027239 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.027239 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15983.005731 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15983.005731 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32844.948064 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32844.948064 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19075.790463 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19075.790463 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 58971.235784 # average WriteLineReq mshr miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 58971.235784 # average WriteLineReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13742.881990 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13742.881990 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81333.333333 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81333.333333 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20840.293204 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20840.293204 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20592.015379 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20592.015379 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173046.925998 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173046.925998 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172773.303073 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172773.303073 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172910.102359 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172910.102359 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 13424392 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 511.782428 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 816544283 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 13424904 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 60.823100 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 61690343500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.782428 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 843394101 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 843394101 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 816544283 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 816544283 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 816544283 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 816544283 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 816544283 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 816544283 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 13424909 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 13424909 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 13424909 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 13424909 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 13424909 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 13424909 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 183122611500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 183122611500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 183122611500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 183122611500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 183122611500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 183122611500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 829969192 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 829969192 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 829969192 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 829969192 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 829969192 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 829969192 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016175 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.016175 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.016175 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.016175 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.016175 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.016175 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13640.510450 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13640.510450 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13640.510450 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13640.510450 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13640.510450 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13640.510450 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13424909 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 13424909 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 13424909 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 13424909 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 13424909 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 13424909 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
|
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169697702500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 169697702500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169697702500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 169697702500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169697702500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 169697702500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436505000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436505000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436505000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 5436505000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016175 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016175 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016175 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.016175 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016175 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.016175 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12640.510450 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12640.510450 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12640.510450 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12640.510450 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12640.510450 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12640.510450 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126063.884058 # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126063.884058 # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126063.884058 # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126063.884058 # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 1005896 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65240.839104 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 41644910 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 1067543 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 39.010054 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 56084638500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 37646.783176 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 207.132082 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 316.131551 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8682.647548 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 18388.144746 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.574444 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003161 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004824 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.132487 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.280581 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.995496 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 202 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61445 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 202 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2441 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5535 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53023 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003082 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.937576 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 372207477 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 372207477 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 308614 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 243101 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 551715 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 7273356 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 7273356 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 8877 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 8877 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1590071 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1590071 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13354589 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 13354589 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5920438 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 5920438 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.InvalidateReq_hits::cpu.data 742839 # number of InvalidateReq hits
|
|
system.cpu.l2cache.InvalidateReq_hits::total 742839 # number of InvalidateReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 308614 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 243101 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 13354589 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7510509 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 21416813 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 308614 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 243101 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 13354589 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7510509 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 21416813 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2139 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2335 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4474 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 32779 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 32779 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 318268 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 318268 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 70320 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 70320 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 223563 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 223563 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.InvalidateReq_misses::cpu.data 479600 # number of InvalidateReq misses
|
|
system.cpu.l2cache.InvalidateReq_misses::total 479600 # number of InvalidateReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 2139 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2335 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 70320 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 541831 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 616625 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 2139 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2335 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 70320 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 541831 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 616625 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 289617500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 321977500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 611595000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1371735500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 1371735500 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 239500 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 239500 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41689304500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 41689304500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9293160000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 9293160000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29760175000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 29760175000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 62455265000 # number of InvalidateReq miss cycles
|
|
system.cpu.l2cache.InvalidateReq_miss_latency::total 62455265000 # number of InvalidateReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 289617500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 321977500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 9293160000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 71449479500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 81354234500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 289617500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 321977500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 9293160000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 71449479500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 81354234500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 310753 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 245436 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 556189 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 7273356 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 7273356 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 41656 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 41656 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1908339 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1908339 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13424909 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 13424909 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6144001 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 6144001 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1222439 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu.l2cache.InvalidateReq_accesses::total 1222439 # number of InvalidateReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 310753 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 245436 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 13424909 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 8052340 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 22033438 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 310753 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 245436 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 13424909 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 8052340 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 22033438 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006883 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009514 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.008044 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.786897 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.786897 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.166777 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.166777 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005238 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005238 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036387 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036387 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.392330 # miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.392330 # miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006883 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009514 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005238 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.027986 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006883 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009514 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005238 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.027986 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 135398.550725 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137891.862955 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 136699.821189 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41847.997193 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41847.997193 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79833.333333 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79833.333333 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130988.049380 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130988.049380 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132155.290102 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132155.290102 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133117.622326 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133117.622326 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130223.655129 # average InvalidateReq miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130223.655129 # average InvalidateReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 135398.550725 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137891.862955 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132155.290102 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131866.725049 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 131934.700182 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 135398.550725 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137891.862955 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132155.290102 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131866.725049 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 131934.700182 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 853156 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 853156 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2139 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2335 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4474 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1011 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 1011 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 32779 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 32779 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 318268 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 318268 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 70320 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 70320 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 223563 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 223563 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 479600 # number of InvalidateReq MSHR misses
|
|
system.cpu.l2cache.InvalidateReq_mshr_misses::total 479600 # number of InvalidateReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2139 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2335 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 70320 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 541831 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 616625 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2139 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2335 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 70320 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 541831 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 616625 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 268227500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 298627500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 566855000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2316135000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2316135000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 209500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 209500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38506624500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38506624500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8589960000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8589960000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27524545000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27524545000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 57659265000 # number of InvalidateReq MSHR miss cycles
|
|
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 57659265000 # number of InvalidateReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 268227500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 298627500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8589960000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66031169500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 75187984500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 268227500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 298627500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8589960000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66031169500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 75187984500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897442500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5410752500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10308195000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5436200500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5436200500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897442500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10846953000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 15744395500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006883 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009514 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008044 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786897 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786897 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166777 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166777 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005238 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005238 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036387 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036387 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.392330 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.392330 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006883 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009514 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005238 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.027986 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006883 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009514 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005238 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.027986 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127891.862955 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126699.821189 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70659.111016 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70659.111016 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120988.049380 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120988.049380 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122155.290102 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122155.290102 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123117.622326 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123117.622326 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120223.655129 # average InvalidateReq mshr miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120223.655129 # average InvalidateReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127891.862955 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122155.290102 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121866.725049 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121934.700182 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125398.550725 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127891.862955 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122155.290102 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121866.725049 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121934.700182 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113563.884058 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160546.925998 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134174.118474 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161273.303073 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161273.303073 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113563.884058 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160910.146862 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 142438.101054 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 45918929 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 23219248 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1752 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 973260 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 20543031 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 8233173 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 15585132 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 41659 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 41662 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1908339 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1908339 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 13424909 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6152877 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateReq 1329103 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateResp 1222439 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40358865 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28042657 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601098 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 851524 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 69854144 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 859366676 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 981090094 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1963488 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2486024 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 1844906282 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 1578062 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 47683915 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.010174 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.100353 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 47198764 98.98% 98.98% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 485151 1.02% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 47683915 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 30513690500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1602380 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 20180488500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 12761129471 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 355662000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 540771000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 40324 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40324 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 565894582 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 115484 # number of replacements
|
|
system.iocache.tags.tagsinuse 10.446961 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 13183666451000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.511449 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 6.935511 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.433469 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.652935 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1039884 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1039884 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 8879 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 8839 # number of overall misses
|
|
system.iocache.overall_misses::total 8879 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::realview.ide 1643284102 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 1648353102 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 13826197480 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 13826197480 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 1643284102 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 1648704102 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 1643284102 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 1648704102 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 185912.897613 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 185709.002028 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129623.841971 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 129623.841971 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 185912.897613 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 185685.786913 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 185912.897613 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 185685.786913 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 32536 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 9.637441 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 106630 # number of writebacks
|
|
system.iocache.writebacks::total 106630 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1201334102 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 1204553102 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8492997480 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 8492997480 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 1201334102 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 1204754102 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 1201334102 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 1204754102 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135912.897613 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 135709.002028 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79623.841971 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79623.841971 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 135912.897613 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 135685.786913 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 135912.897613 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 135685.786913 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 76827 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 384060 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 33708 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 33708 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 959786 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 158940 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 33352 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 33355 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 797298 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 797298 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 307233 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3354625 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3484317 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341373 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 341373 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 3825690 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124875168 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 125044994 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7229568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7229568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 132274562 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 3206 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 2476492 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 2476492 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 2476492 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 107338500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 5425000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 6302386470 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 6068941451 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 228333558 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
|
|
|
---------- End Simulation Statistics ----------
|