stats: update references
This commit is contained in:
Curtis Dunham
parent
a288c94387
commit
84f138ba96
601 changed files with 86548 additions and 58309 deletions
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@ -15,10 +15,12 @@ boot_cpu_frequency=500
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boot_osflags=root=/dev/hda1 console=ttyS0
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cache_line_size=64
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clk_domain=system.clk_domain
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console=/work/gem5/dist/binaries/console
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console=/arm/projectscratch/randd/systems/dist/binaries/console
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default_p_state=UNDEFINED
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eventq_index=0
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exit_on_work_items=false
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init_param=0
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kernel=/work/gem5/dist/binaries/vmlinux
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kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
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kernel_addr_check=true
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load_addr_mask=1099511627775
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load_offset=0
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@ -28,11 +30,17 @@ memories=system.physmem
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mmap_using_noreserve=false
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multi_thread=false
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num_work_ids=16
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pal=/work/gem5/dist/binaries/ts_osfpal
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readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
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power_model=Null
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readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
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symbolfile=
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system_rev=1024
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system_type=34
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thermal_components=
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thermal_model=Null
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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@ -45,8 +53,13 @@ system_port=system.membus.slave[0]
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[system.bridge]
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type=Bridge
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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delay=50000
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eventq_index=0
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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ranges=8796093022208:18446744073709551615
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req_size=16
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resp_size=16
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@ -72,6 +85,7 @@ decodeCycleInput=true
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decodeInputBufferSize=3
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decodeInputWidth=2
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decodeToExecuteForwardDelay=1
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default_p_state=UNDEFINED
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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@ -114,12 +128,17 @@ max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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profile=0
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progress_interval=0
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simpoint_start_insts=
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socket_id=0
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switched_out=false
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system=system
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threadPolicy=RoundRobin
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tracer=system.cpu.tracer
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workload=
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dcache_port=system.cpu.dcache.cpu_side
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@ -135,11 +154,18 @@ choicePredictorSize=8192
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eventq_index=0
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globalCtrBits=2
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globalPredictorSize=8192
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indirectHashGHR=true
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indirectHashTargets=true
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indirectPathLength=3
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indirectSets=256
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indirectTagSize=16
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indirectWays=2
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instShiftAmt=2
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localCtrBits=2
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localHistoryTableSize=2048
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localPredictorSize=2048
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numThreads=1
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useIndirect=true
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[system.cpu.dcache]
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type=Cache
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@ -148,13 +174,17 @@ addr_ranges=0:18446744073709551615
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assoc=4
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clk_domain=system.cpu_clk_domain
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clusivity=mostly_incl
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default_p_state=UNDEFINED
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_read_only=false
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max_miss_count=0
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mshrs=4
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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@ -173,8 +203,13 @@ type=LRU
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assoc=4
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block_size=64
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clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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hit_latency=2
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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sequential_access=false
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size=32768
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@ -573,13 +608,17 @@ addr_ranges=0:18446744073709551615
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assoc=1
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clk_domain=system.cpu_clk_domain
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clusivity=mostly_incl
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default_p_state=UNDEFINED
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=2
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is_read_only=true
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max_miss_count=0
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mshrs=4
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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@ -598,8 +637,13 @@ type=LRU
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assoc=1
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block_size=64
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clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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hit_latency=2
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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sequential_access=false
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size=32768
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@ -624,13 +668,17 @@ addr_ranges=0:18446744073709551615
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assoc=8
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clk_domain=system.cpu_clk_domain
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clusivity=mostly_incl
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default_p_state=UNDEFINED
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=true
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hit_latency=20
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is_read_only=false
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max_miss_count=0
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mshrs=20
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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prefetch_on_access=false
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prefetcher=Null
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response_latency=20
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@ -649,8 +697,13 @@ type=LRU
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assoc=8
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block_size=64
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clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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hit_latency=20
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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sequential_access=false
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size=4194304
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@ -658,9 +711,15 @@ size=4194304
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type=CoherentXBar
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children=snoop_filter
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clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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forward_latency=0
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frontend_latency=1
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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point_of_coherency=false
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power_model=Null
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response_latency=1
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snoop_filter=system.cpu.toL2Bus.snoop_filter
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snoop_response_latency=1
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@ -709,7 +768,7 @@ table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/work/gem5/dist/disks/linux-latest.img
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image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
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read_only=true
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[system.disk2]
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@ -732,7 +791,7 @@ table_size=65536
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[system.disk2.image.child]
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type=RawDiskImage
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eventq_index=0
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image_file=/work/gem5/dist/disks/linux-bigswap2.img
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image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
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read_only=true
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[system.dvfs_handler]
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@ -751,9 +810,14 @@ sys=system
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[system.iobus]
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type=NoncoherentXBar
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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forward_latency=1
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frontend_latency=2
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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response_latency=2
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use_default_range=false
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width=16
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@ -767,13 +831,17 @@ addr_ranges=0:134217727
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assoc=8
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clk_domain=system.clk_domain
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clusivity=mostly_incl
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default_p_state=UNDEFINED
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demand_mshr_reserve=1
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eventq_index=0
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forward_snoops=false
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hit_latency=50
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is_read_only=false
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max_miss_count=0
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mshrs=20
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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prefetch_on_access=false
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prefetcher=Null
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response_latency=50
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@ -792,8 +860,13 @@ type=LRU
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assoc=8
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block_size=64
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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hit_latency=50
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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power_model=Null
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sequential_access=false
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size=1024
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@ -801,9 +874,15 @@ size=1024
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type=CoherentXBar
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children=badaddr_responder
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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forward_latency=4
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frontend_latency=3
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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point_of_coherency=true
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power_model=Null
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response_latency=2
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snoop_filter=Null
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snoop_response_latency=4
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@ -817,11 +896,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
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[system.membus.badaddr_responder]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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pio_addr=0
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pio_latency=100000
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pio_size=8
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power_model=Null
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ret_bad_addr=true
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ret_data16=65535
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ret_data32=4294967295
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@ -866,6 +950,7 @@ burst_length=8
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channels=1
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clk_domain=system.clk_domain
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conf_table_reported=true
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default_p_state=UNDEFINED
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device_bus_width=8
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device_rowbuffer_size=1024
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device_size=536870912
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@ -877,7 +962,11 @@ max_accesses_per_row=16
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mem_sched_policy=frfcfs
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min_writes_per_switch=16
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null=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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page_policy=open_adaptive
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power_model=Null
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range=0:134217727
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ranks_per_channel=2
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read_buffer_size=32
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@ -919,7 +1008,7 @@ system=system
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[system.simple_disk.disk]
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type=RawDiskImage
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eventq_index=0
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image_file=/work/gem5/dist/disks/linux-latest.img
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image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
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read_only=true
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[system.terminal]
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@ -941,11 +1030,16 @@ system=system
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type=AlphaBackdoor
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clk_domain=system.clk_domain
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cpu=system.cpu
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default_p_state=UNDEFINED
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disk=system.simple_disk
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eventq_index=0
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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pio_addr=8804682956800
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pio_latency=100000
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platform=system.tsunami
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power_model=Null
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system=system
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terminal=system.terminal
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pio=system.iobus.master[24]
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@ -953,9 +1047,14 @@ pio=system.iobus.master[24]
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[system.tsunami.cchip]
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type=TsunamiCChip
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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pio_addr=8803072344064
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pio_latency=100000
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power_model=Null
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system=system
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tsunami=system.tsunami
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pio=system.iobus.master[0]
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@ -1036,6 +1135,7 @@ SubsystemVendorID=0
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VendorID=4107
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clk_domain=system.clk_domain
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config_latency=20000
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default_p_state=UNDEFINED
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dma_data_free=false
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dma_desc_free=false
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dma_no_allocate=true
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@ -1047,10 +1147,14 @@ eventq_index=0
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hardware_address=00:90:00:00:00:01
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host=system.tsunami.pchip
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intr_delay=10000000
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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pci_bus=0
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pci_dev=1
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pci_func=0
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pio_latency=30000
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power_model=Null
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rss=false
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rx_delay=1000000
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rx_fifo_size=524288
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@ -1066,11 +1170,16 @@ pio=system.iobus.master[26]
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[system.tsunami.fake_OROM]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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pio_addr=8796093677568
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pio_latency=100000
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pio_size=393216
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power_model=Null
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ret_bad_addr=false
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ret_data16=65535
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ret_data32=4294967295
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@ -1084,11 +1193,16 @@ pio=system.iobus.master[8]
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[system.tsunami.fake_ata0]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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pio_addr=8804615848432
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pio_latency=100000
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pio_size=8
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power_model=Null
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ret_bad_addr=false
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ret_data16=65535
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ret_data32=4294967295
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@ -1102,11 +1216,16 @@ pio=system.iobus.master[19]
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[system.tsunami.fake_ata1]
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type=IsaFake
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clk_domain=system.clk_domain
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default_p_state=UNDEFINED
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eventq_index=0
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fake_mem=false
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p_state_clk_gate_bins=20
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p_state_clk_gate_max=1000000000000
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p_state_clk_gate_min=1000
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pio_addr=8804615848304
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pio_latency=100000
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pio_size=8
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power_model=Null
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ret_bad_addr=false
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ret_data16=65535
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ret_data32=4294967295
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@ -1120,11 +1239,16 @@ pio=system.iobus.master[20]
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[system.tsunami.fake_pnp_addr]
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type=IsaFake
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clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1138,11 +1262,16 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1156,11 +1285,16 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1174,11 +1308,16 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1192,11 +1331,16 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1210,11 +1354,16 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1228,11 +1377,16 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1246,11 +1400,16 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1264,11 +1423,16 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1282,11 +1446,16 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1300,11 +1469,16 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1318,11 +1492,16 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1336,11 +1515,16 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1354,11 +1538,16 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1372,11 +1561,16 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1390,11 +1584,16 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1408,10 +1607,15 @@ pio=system.iobus.master[6]
|
|||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1492,14 +1696,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
host=system.tsunami.pchip
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
|
@ -1507,10 +1716,15 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
|
|
@ -1523,13 +1737,18 @@ clk_domain=system.clk_domain
|
|||
conf_base=8804649402368
|
||||
conf_device_bits=8
|
||||
conf_size=16777216
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=8796093022208
|
||||
pci_pio_base=8804615847936
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
|
@ -1537,10 +1756,15 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
|
|
|
|||
|
|
@ -1,13 +1,15 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 10:28:58
|
||||
gem5 started Dec 4 2015 10:29:11
|
||||
gem5 executing on e104799-lin, pid 21295
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
|
||||
gem5 compiled Jul 19 2016 12:23:51
|
||||
gem5 started Jul 19 2016 12:24:23
|
||||
gem5 executing on e108600-lin, pid 39539
|
||||
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-minor
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1906048606500 because m5_exit instruction encountered
|
||||
Exiting @ tick 1909061460000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -15,10 +15,12 @@ boot_cpu_frequency=500
|
|||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/work/gem5/dist/binaries/console
|
||||
console=/arm/projectscratch/randd/systems/dist/binaries/console
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
|
|
@ -28,11 +30,17 @@ memories=system.physmem
|
|||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
pal=/work/gem5/dist/binaries/ts_osfpal
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -45,8 +53,13 @@ system_port=system.membus.slave[0]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -85,6 +98,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -121,6 +135,10 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -160,11 +178,18 @@ choicePredictorSize=8192
|
|||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu0.dcache]
|
||||
type=Cache
|
||||
|
|
@ -173,13 +198,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -198,8 +227,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -522,13 +556,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -547,8 +585,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -594,6 +637,7 @@ cpu_id=1
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -630,6 +674,10 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -669,11 +717,18 @@ choicePredictorSize=8192
|
|||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu1.dcache]
|
||||
type=Cache
|
||||
|
|
@ -682,13 +737,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -707,8 +766,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -1031,13 +1095,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -1056,8 +1124,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -1107,7 +1180,7 @@ table_size=65536
|
|||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-latest.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -1130,7 +1203,7 @@ table_size=65536
|
|||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-bigswap2.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.dvfs_handler]
|
||||
|
|
@ -1149,9 +1222,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -1165,13 +1243,17 @@ addr_ranges=0:134217727
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -1190,8 +1272,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -1202,13 +1289,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -1227,20 +1318,31 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
children=badaddr_responder snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -1252,11 +1354,16 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1267,6 +1374,13 @@ update_data=false
|
|||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
|
|
@ -1301,6 +1415,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -1312,7 +1427,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -1354,7 +1473,7 @@ system=system
|
|||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-latest.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
@ -1369,9 +1488,15 @@ port=3456
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -1399,11 +1524,16 @@ system=system
|
|||
type=AlphaBackdoor
|
||||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu0
|
||||
default_p_state=UNDEFINED
|
||||
disk=system.simple_disk
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804682956800
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
|
@ -1411,9 +1541,14 @@ pio=system.iobus.master[24]
|
|||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1494,6 +1629,7 @@ SubsystemVendorID=0
|
|||
VendorID=4107
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
|
|
@ -1505,10 +1641,14 @@ eventq_index=0
|
|||
hardware_address=00:90:00:00:00:01
|
||||
host=system.tsunami.pchip
|
||||
intr_delay=10000000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
|
|
@ -1524,11 +1664,16 @@ pio=system.iobus.master[26]
|
|||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
pio_size=393216
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1542,11 +1687,16 @@ pio=system.iobus.master[8]
|
|||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1560,11 +1710,16 @@ pio=system.iobus.master[19]
|
|||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1578,11 +1733,16 @@ pio=system.iobus.master[20]
|
|||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1596,11 +1756,16 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1614,11 +1779,16 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1632,11 +1802,16 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1650,11 +1825,16 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1668,11 +1848,16 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1686,11 +1871,16 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1704,11 +1894,16 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1722,11 +1917,16 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1740,11 +1940,16 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1758,11 +1963,16 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1776,11 +1986,16 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1794,11 +2009,16 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1812,11 +2032,16 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1830,11 +2055,16 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1848,11 +2078,16 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1866,10 +2101,15 @@ pio=system.iobus.master[6]
|
|||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1950,14 +2190,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
host=system.tsunami.pchip
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
|
@ -1965,10 +2210,15 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
|
|
@ -1981,13 +2231,18 @@ clk_domain=system.clk_domain
|
|||
conf_base=8804649402368
|
||||
conf_device_bits=8
|
||||
conf_size=16777216
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=8796093022208
|
||||
pci_pio_base=8804615847936
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
|
@ -1995,10 +2250,15 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
|
|
|
|||
|
|
@ -1,14 +1,16 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 10:28:58
|
||||
gem5 started Dec 4 2015 10:42:11
|
||||
gem5 executing on e104799-lin, pid 22878
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
gem5 compiled Jul 19 2016 12:23:51
|
||||
gem5 started Jul 19 2016 12:24:23
|
||||
gem5 executing on e108600-lin, pid 39569
|
||||
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Launching CPU 1 @ 179187500
|
||||
Exiting @ tick 1922761887500 because m5_exit instruction encountered
|
||||
info: Launching CPU 1 @ 127844500
|
||||
Exiting @ tick 1907672102500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
memcluster 1, usage 0, start 392, end 16384
|
||||
freeing pages 1069:16384
|
||||
reserving pages 1069:1070
|
||||
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
|
||||
4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
|
||||
SMP: 2 CPUs probed -- cpu_present_mask = 3
|
||||
Built 1 zonelists
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
|
|
|||
|
|
@ -15,10 +15,12 @@ boot_cpu_frequency=500
|
|||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/work/gem5/dist/binaries/console
|
||||
console=/arm/projectscratch/randd/systems/dist/binaries/console
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
|
|
@ -28,11 +30,17 @@ memories=system.physmem
|
|||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
pal=/work/gem5/dist/binaries/ts_osfpal
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -45,8 +53,13 @@ system_port=system.membus.slave[0]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -85,6 +98,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -121,6 +135,10 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -160,11 +178,18 @@ choicePredictorSize=8192
|
|||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
|
|
@ -173,13 +198,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -198,8 +227,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -522,13 +556,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -547,8 +585,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -573,13 +616,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -598,8 +645,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -607,9 +659,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -658,7 +716,7 @@ table_size=65536
|
|||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-latest.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -681,7 +739,7 @@ table_size=65536
|
|||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-bigswap2.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.dvfs_handler]
|
||||
|
|
@ -700,9 +758,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -716,13 +779,17 @@ addr_ranges=0:134217727
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -741,8 +808,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -750,9 +822,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -766,11 +844,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -815,6 +898,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -826,7 +910,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -868,7 +956,7 @@ system=system
|
|||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-latest.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
@ -890,11 +978,16 @@ system=system
|
|||
type=AlphaBackdoor
|
||||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu
|
||||
default_p_state=UNDEFINED
|
||||
disk=system.simple_disk
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804682956800
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
|
@ -902,9 +995,14 @@ pio=system.iobus.master[24]
|
|||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -985,6 +1083,7 @@ SubsystemVendorID=0
|
|||
VendorID=4107
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
|
|
@ -996,10 +1095,14 @@ eventq_index=0
|
|||
hardware_address=00:90:00:00:00:01
|
||||
host=system.tsunami.pchip
|
||||
intr_delay=10000000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
|
|
@ -1015,11 +1118,16 @@ pio=system.iobus.master[26]
|
|||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
pio_size=393216
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1033,11 +1141,16 @@ pio=system.iobus.master[8]
|
|||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1051,11 +1164,16 @@ pio=system.iobus.master[19]
|
|||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1069,11 +1187,16 @@ pio=system.iobus.master[20]
|
|||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1087,11 +1210,16 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1105,11 +1233,16 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1123,11 +1256,16 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1141,11 +1279,16 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1159,11 +1302,16 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1177,11 +1325,16 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1195,11 +1348,16 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1213,11 +1371,16 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1231,11 +1394,16 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1249,11 +1417,16 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1267,11 +1440,16 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1285,11 +1463,16 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1303,11 +1486,16 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1321,11 +1509,16 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1339,11 +1532,16 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1357,10 +1555,15 @@ pio=system.iobus.master[6]
|
|||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1441,14 +1644,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
host=system.tsunami.pchip
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
|
@ -1456,10 +1664,15 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
|
|
@ -1472,13 +1685,18 @@ clk_domain=system.clk_domain
|
|||
conf_base=8804649402368
|
||||
conf_device_bits=8
|
||||
conf_size=16777216
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=8796093022208
|
||||
pci_pio_base=8804615847936
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
|
@ -1486,10 +1704,15 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
|
|
|
|||
|
|
@ -1,13 +1,15 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 10:28:58
|
||||
gem5 started Dec 4 2015 10:48:09
|
||||
gem5 executing on e104799-lin, pid 23716
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
|
||||
gem5 compiled Jul 19 2016 12:23:51
|
||||
gem5 started Jul 19 2016 12:24:28
|
||||
gem5 executing on e108600-lin, pid 39623
|
||||
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 1875760362000 because m5_exit instruction encountered
|
||||
Exiting @ tick 1876794488000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.876794 # Nu
|
|||
sim_ticks 1876794488000 # Number of ticks simulated
|
||||
final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 191271 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 191271 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6775305946 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 377772 # Number of bytes of host memory used
|
||||
host_seconds 277.01 # Real time elapsed on the host
|
||||
host_inst_rate 152079 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 152079 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5387044029 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 330796 # Number of bytes of host memory used
|
||||
host_seconds 348.39 # Real time elapsed on the host
|
||||
sim_insts 52982943 # Number of instructions simulated
|
||||
sim_ops 52982943 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -1159,6 +1159,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144052988 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 281576892 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 422541 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 7562240 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2920171 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001264 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.035530 # Request fanout histogram
|
||||
|
|
@ -1370,6 +1371,7 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728
|
|||
system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 33414972 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 438 # Total snoops (count)
|
||||
system.membus.snoopTraffic 27840 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 842137 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -15,10 +15,12 @@ boot_cpu_frequency=500
|
|||
boot_osflags=root=/dev/hda1 console=ttyS0
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
console=/work/gem5/dist/binaries/console
|
||||
console=/arm/projectscratch/randd/systems/dist/binaries/console
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=1099511627775
|
||||
load_offset=0
|
||||
|
|
@ -28,11 +30,17 @@ memories=system.physmem
|
|||
mmap_using_noreserve=false
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
pal=/work/gem5/dist/binaries/ts_osfpal
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
symbolfile=
|
||||
system_rev=1024
|
||||
system_type=34
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -45,8 +53,13 @@ system_port=system.membus.slave[0]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=8796093022208:18446744073709551615
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -68,6 +81,7 @@ branchPred=Null
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -84,6 +98,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -105,13 +123,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -130,8 +152,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -147,13 +174,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -172,8 +203,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -202,6 +238,7 @@ branchPred=Null
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -217,6 +254,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -269,6 +310,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -305,6 +347,10 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -342,11 +388,18 @@ choicePredictorSize=8192
|
|||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu2.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -702,7 +755,7 @@ table_size=65536
|
|||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-latest.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.disk2]
|
||||
|
|
@ -725,7 +778,7 @@ table_size=65536
|
|||
[system.disk2.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-bigswap2.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
|
||||
read_only=true
|
||||
|
||||
[system.dvfs_handler]
|
||||
|
|
@ -744,9 +797,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -760,13 +818,17 @@ addr_ranges=0:134217727
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -785,8 +847,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -797,13 +864,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -822,20 +893,31 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
children=badaddr_responder snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -847,11 +929,16 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -862,6 +949,13 @@ update_data=false
|
|||
warn_access=
|
||||
pio=system.membus.default
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=DRAMCtrl
|
||||
IDD0=0.075000
|
||||
|
|
@ -896,6 +990,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -907,7 +1002,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=0:134217727
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -949,7 +1048,7 @@ system=system
|
|||
[system.simple_disk.disk]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-latest.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
|
||||
read_only=true
|
||||
|
||||
[system.terminal]
|
||||
|
|
@ -964,9 +1063,15 @@ port=3456
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -994,11 +1099,16 @@ system=system
|
|||
type=AlphaBackdoor
|
||||
clk_domain=system.clk_domain
|
||||
cpu=system.cpu0
|
||||
default_p_state=UNDEFINED
|
||||
disk=system.simple_disk
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804682956800
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[24]
|
||||
|
|
@ -1006,9 +1116,14 @@ pio=system.iobus.master[24]
|
|||
[system.tsunami.cchip]
|
||||
type=TsunamiCChip
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8803072344064
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1089,6 +1204,7 @@ SubsystemVendorID=0
|
|||
VendorID=4107
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
dma_data_free=false
|
||||
dma_desc_free=false
|
||||
dma_no_allocate=true
|
||||
|
|
@ -1100,10 +1216,14 @@ eventq_index=0
|
|||
hardware_address=00:90:00:00:00:01
|
||||
host=system.tsunami.pchip
|
||||
intr_delay=10000000
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rss=false
|
||||
rx_delay=1000000
|
||||
rx_fifo_size=524288
|
||||
|
|
@ -1119,11 +1239,16 @@ pio=system.iobus.master[26]
|
|||
[system.tsunami.fake_OROM]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8796093677568
|
||||
pio_latency=100000
|
||||
pio_size=393216
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1137,11 +1262,16 @@ pio=system.iobus.master[8]
|
|||
[system.tsunami.fake_ata0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848432
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1155,11 +1285,16 @@ pio=system.iobus.master[19]
|
|||
[system.tsunami.fake_ata1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848304
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1173,11 +1308,16 @@ pio=system.iobus.master[20]
|
|||
[system.tsunami.fake_pnp_addr]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848569
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1191,11 +1331,16 @@ pio=system.iobus.master[9]
|
|||
[system.tsunami.fake_pnp_read0]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848451
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1209,11 +1354,16 @@ pio=system.iobus.master[11]
|
|||
[system.tsunami.fake_pnp_read1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848515
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1227,11 +1377,16 @@ pio=system.iobus.master[12]
|
|||
[system.tsunami.fake_pnp_read2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848579
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1245,11 +1400,16 @@ pio=system.iobus.master[13]
|
|||
[system.tsunami.fake_pnp_read3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848643
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1263,11 +1423,16 @@ pio=system.iobus.master[14]
|
|||
[system.tsunami.fake_pnp_read4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848707
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1281,11 +1446,16 @@ pio=system.iobus.master[15]
|
|||
[system.tsunami.fake_pnp_read5]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848771
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1299,11 +1469,16 @@ pio=system.iobus.master[16]
|
|||
[system.tsunami.fake_pnp_read6]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848835
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1317,11 +1492,16 @@ pio=system.iobus.master[17]
|
|||
[system.tsunami.fake_pnp_read7]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848899
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1335,11 +1515,16 @@ pio=system.iobus.master[18]
|
|||
[system.tsunami.fake_pnp_write]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615850617
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1353,11 +1538,16 @@ pio=system.iobus.master[10]
|
|||
[system.tsunami.fake_ppc]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848891
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1371,11 +1561,16 @@ pio=system.iobus.master[7]
|
|||
[system.tsunami.fake_sm_chip]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848816
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1389,11 +1584,16 @@ pio=system.iobus.master[2]
|
|||
[system.tsunami.fake_uart1]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848696
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1407,11 +1607,16 @@ pio=system.iobus.master[3]
|
|||
[system.tsunami.fake_uart2]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848936
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1425,11 +1630,16 @@ pio=system.iobus.master[4]
|
|||
[system.tsunami.fake_uart3]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848680
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1443,11 +1653,16 @@ pio=system.iobus.master[5]
|
|||
[system.tsunami.fake_uart4]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848944
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1461,10 +1676,15 @@ pio=system.iobus.master[6]
|
|||
[system.tsunami.fb]
|
||||
type=BadDevice
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
devicename=FrameBuffer
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848912
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1545,14 +1765,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.disk0 system.disk2
|
||||
eventq_index=0
|
||||
host=system.tsunami.pchip
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[1]
|
||||
pio=system.iobus.master[25]
|
||||
|
|
@ -1560,10 +1785,15 @@ pio=system.iobus.master[25]
|
|||
[system.tsunami.io]
|
||||
type=TsunamiIO
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
frequency=976562500
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615847936
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
tsunami=system.tsunami
|
||||
|
|
@ -1576,13 +1806,18 @@ clk_domain=system.clk_domain
|
|||
conf_base=8804649402368
|
||||
conf_device_bits=8
|
||||
conf_size=16777216
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=8796093022208
|
||||
pci_pio_base=8804615847936
|
||||
pio_addr=8802535473152
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
tsunami=system.tsunami
|
||||
pio=system.iobus.master[1]
|
||||
|
|
@ -1590,10 +1825,15 @@ pio=system.iobus.master[1]
|
|||
[system.tsunami.uart]
|
||||
type=Uart8250
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=8804615848952
|
||||
pio_latency=100000
|
||||
platform=system.tsunami
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[23]
|
||||
|
|
|
|||
|
|
@ -1,6 +1,12 @@
|
|||
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: ClockedObject: Already in the requested power state, request ignored
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: Prefetch instructions in Alpha do not do anything
|
||||
|
|
@ -15,8 +21,18 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
|
|||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 10194, Bank: 5
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 7524, Bank: 7
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 11199, Bank: 6
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 11377, Bank: 4
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
|
||||
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 10:28:58
|
||||
gem5 started Dec 4 2015 10:29:24
|
||||
gem5 executing on e104799-lin, pid 21387
|
||||
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
|
||||
gem5 compiled Jul 19 2016 12:23:51
|
||||
gem5 started Jul 19 2016 12:24:24
|
||||
gem5 executing on e108600-lin, pid 39575
|
||||
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.841599 # Nu
|
|||
sim_ticks 1841599161000 # Number of ticks simulated
|
||||
final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 307539 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 307539 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8488565495 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 380848 # Number of bytes of host memory used
|
||||
host_seconds 216.95 # Real time elapsed on the host
|
||||
host_inst_rate 220916 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 220916 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6097623299 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332848 # Number of bytes of host memory used
|
||||
host_seconds 302.02 # Real time elapsed on the host
|
||||
sim_insts 66720805 # Number of instructions simulated
|
||||
sim_ops 66720805 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -1910,6 +1910,7 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320
|
|||
system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 33343552 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 157 # Total snoops (count)
|
||||
system.membus.snoopTraffic 9856 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 742227 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.001296 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.035978 # Request fanout histogram
|
||||
|
|
@ -1962,6 +1963,7 @@ system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1241
|
|||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142881728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 267065664 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 338688 # Total snoops (count)
|
||||
system.toL2Bus.snoopTraffic 4852416 # Total snoop traffic (bytes)
|
||||
system.toL2Bus.snoop_fanout::samples 4114055 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.000998 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.031568 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
|
|||
memcluster 1, usage 0, start 392, end 16384
|
||||
freeing pages 1069:16384
|
||||
reserving pages 1069:1070
|
||||
4096K Bcache detected; load hit latency 6 cycles, load miss latency 30 cycles
|
||||
4096K Bcache detected; load hit latency 6 cycles, load miss latency 32 cycles
|
||||
SMP: 1 CPUs probed -- cpu_present_mask = 1
|
||||
Built 1 zonelists
|
||||
Kernel command line: root=/dev/hda1 console=ttyS0
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
|
|
|
|||
|
|
@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:42
|
||||
gem5 started Mar 15 2016 21:34:30
|
||||
gem5 executing on phenom, pid 15961
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:42:06
|
||||
gem5 executing on e108600-lin, pid 23137
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor-dual
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
|
|
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
|||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2649116242500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2647778082500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -158,8 +158,8 @@ ata1.00: 1048320 sectors, multi 0: LBA
|
|||
ata1.00: configured for UDMA/33
|
||||
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
|
||||
sd 0:0:0:0: [sda] Write Protect is off
|
||||
sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
sd 0:0:0:0: [sda] Write Protect is off
|
||||
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
sda: sda1
|
||||
|
|
|
|||
|
|
@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/work/gem5/dist/binaries/boot_emm.arm
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
flags_addr=469827632
|
||||
gic_cpu_addr=738205696
|
||||
have_large_asid_64=false
|
||||
have_lpae=false
|
||||
have_lpae=true
|
||||
have_security=false
|
||||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -40,12 +42,18 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -86,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linux-aarch32-ael.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -108,6 +121,7 @@ decodeCycleInput=true
|
|||
decodeInputBufferSize=3
|
||||
decodeInputWidth=2
|
||||
decodeToExecuteForwardDelay=1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -152,12 +166,17 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
threadPolicy=RoundRobin
|
||||
tracer=system.cpu.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -173,11 +192,18 @@ choicePredictorSize=8192
|
|||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
|
|
@ -186,13 +212,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -211,8 +241,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -235,9 +270,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -251,9 +291,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -647,13 +692,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -672,8 +721,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -731,9 +785,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -747,9 +806,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -760,13 +824,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -785,8 +853,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -794,9 +867,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -841,9 +920,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -857,13 +941,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -882,8 +970,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -891,9 +984,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -907,11 +1006,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -956,6 +1060,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -967,7 +1072,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -1010,10 +1119,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -1094,14 +1208,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -1110,13 +1229,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -1126,6 +1250,7 @@ pio=system.iobus.master[5]
|
|||
type=SubSystem
|
||||
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.dcc.osc_cpu]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1196,10 +1321,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -1279,17 +1409,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -1315,12 +1450,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -1328,14 +1469,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -1421,14 +1567,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1437,13 +1588,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1452,13 +1608,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1466,11 +1627,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1484,11 +1650,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1502,19 +1673,25 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.mcc]
|
||||
type=SubSystem
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.mcc.osc_clcd]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1560,14 +1737,29 @@ position=0
|
|||
site=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.realview.mcc.temp_crtl]
|
||||
type=RealViewTemperatureSensor
|
||||
dcc=0
|
||||
device=0
|
||||
eventq_index=0
|
||||
parent=system.realview.realview_io
|
||||
position=0
|
||||
site=0
|
||||
system=system
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1576,11 +1768,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1590,21 +1787,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=16
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=0
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1614,12 +1821,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1628,10 +1840,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1641,12 +1858,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1656,26 +1878,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1684,10 +1916,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1695,10 +1932,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1706,21 +1948,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1734,11 +1986,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1749,11 +2006,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1761,10 +2023,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 12:02:21
|
||||
gem5 executing on e104799-lin, pid 1517
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:38:21
|
||||
gem5 executing on e108600-lin, pid 23070
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-minor
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
|
|
@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
|||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2858558607500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2858997339500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
|
|
@ -29,7 +30,7 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -41,10 +42,14 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
|
|
@ -61,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -89,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -124,6 +134,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -162,6 +173,10 @@ numPhysIntRegs=128
|
|||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -217,6 +232,7 @@ children=dstage2_mmu dtb isa istage2_mmu itb tracer
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -235,6 +251,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -265,9 +285,14 @@ walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.checker.dtb]
|
||||
|
|
@ -281,9 +306,14 @@ walker=system.cpu.checker.dtb.walker
|
|||
[system.cpu.checker.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
|
|
@ -337,9 +367,14 @@ walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.checker.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.checker.itb]
|
||||
|
|
@ -353,9 +388,14 @@ walker=system.cpu.checker.itb.walker
|
|||
[system.cpu.checker.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
|
|
@ -370,12 +410,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -394,8 +439,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -418,9 +468,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -434,9 +489,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -712,12 +772,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -736,8 +801,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -795,9 +865,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -811,9 +886,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -824,12 +904,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -848,8 +933,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -857,10 +947,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -905,9 +1000,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -921,12 +1021,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -945,8 +1050,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -954,10 +1064,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -971,11 +1086,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1020,6 +1140,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -1031,7 +1152,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -1074,10 +1199,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -1158,14 +1288,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -1174,13 +1309,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -1261,10 +1401,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -1344,17 +1489,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -1380,13 +1530,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -1394,14 +1549,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -1487,14 +1647,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1503,13 +1668,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1518,13 +1688,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1532,11 +1707,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1550,11 +1730,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1568,12 +1753,17 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
|
|
@ -1641,10 +1831,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1653,11 +1848,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1667,21 +1867,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=16
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=0
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1691,12 +1901,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1705,10 +1920,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1718,12 +1938,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1733,26 +1958,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1761,10 +1996,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1772,10 +2012,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1783,21 +2028,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1811,11 +2066,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1826,11 +2086,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1838,10 +2103,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
|
|
@ -42,6 +44,5 @@ warn: Ignoring write to miscreg pmovsr
|
|||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: 409343110000: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
|
||||
warn: instruction 'mcr dcisw' unimplemented
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
|
|
|
|||
|
|
@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:42
|
||||
gem5 started Mar 15 2016 21:34:31
|
||||
gem5 executing on phenom, pid 15958
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:38:23
|
||||
gem5 executing on e108600-lin, pid 23084
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-checker
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
|
|
@ -44,4 +44,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
|||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2832862976500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2832894126500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
|
|
|
|||
|
|
@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:42
|
||||
gem5 started Mar 15 2016 21:34:31
|
||||
gem5 executing on phenom, pid 15964
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:39:51
|
||||
gem5 executing on e108600-lin, pid 23108
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
|
|
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
|||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2825959731500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2825947406000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
|
|
@ -29,7 +30,7 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -41,10 +42,14 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
|
|
@ -61,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -89,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -124,6 +134,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -162,6 +173,10 @@ numPhysIntRegs=128
|
|||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -218,12 +233,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -242,8 +262,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -266,9 +291,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -282,9 +312,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -560,12 +595,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -584,8 +624,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -643,9 +688,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -659,9 +709,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -672,12 +727,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -696,8 +756,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -705,10 +770,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -753,9 +823,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -769,12 +844,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -793,8 +873,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -802,10 +887,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -819,11 +909,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -868,6 +963,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -879,7 +975,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -922,10 +1022,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -1006,14 +1111,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -1022,13 +1132,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -1109,10 +1224,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -1192,17 +1312,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -1228,13 +1353,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -1242,14 +1372,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -1335,14 +1470,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1351,13 +1491,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1366,13 +1511,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1380,11 +1530,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1398,11 +1553,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1416,12 +1576,17 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
|
|
@ -1489,10 +1654,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1501,11 +1671,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1515,21 +1690,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=16
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=0
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1539,12 +1724,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1553,10 +1743,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1566,12 +1761,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1581,26 +1781,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1609,10 +1819,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1620,10 +1835,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1631,21 +1851,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1659,11 +1889,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1674,11 +1909,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1686,10 +1926,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
|
|
|
|||
|
|
@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:42
|
||||
gem5 started Mar 15 2016 21:34:35
|
||||
gem5 executing on phenom, pid 15973
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:38:25
|
||||
gem5 executing on e108600-lin, pid 23094
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80008000
|
||||
info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
|
|
@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
|||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
|
||||
Exiting @ tick 2832862976500 because m5_exit instruction encountered
|
||||
Exiting @ tick 2832894126500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -2,6 +2,10 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
|
|
@ -31,6 +35,9 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
|
|||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: ClockedObject: Already in the requested power state, request ignored
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
|
||||
|
|
@ -38,22 +45,22 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
|
|||
warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
|
||||
warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
|
||||
warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 10945, Bank: 2
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 10462, Bank: 2
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
|
||||
Command: 0, Timestamp: 11030, Bank: 2
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 10621, Bank: 7
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 11318, Bank: 7
|
||||
warn: Returning zero for read from miscreg pmcr
|
||||
warn: Ignoring write to miscreg pmcntenclr
|
||||
warn: Ignoring write to miscreg pmintenclr
|
||||
|
|
@ -65,8 +72,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
|
|||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: Bank is already active!
|
||||
Command: 0, Timestamp: 8588, Bank: 0
|
||||
warn: CP14 unimplemented crn[10], opc1[0], crm[4], opc2[3]
|
||||
warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
|
|
@ -86,22 +93,11 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
|
|||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
|
||||
warn: instruction 'mcr bpiall' unimplemented
|
||||
warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0]
|
||||
warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7]
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: User mode does not have SPSR
|
||||
|
|
@ -112,8 +108,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
|
|||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: User mode does not have SPSR
|
||||
|
|
@ -124,3 +126,11 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
|
|||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
WARNING: One or more banks are active! REF requires all banks to be precharged.
|
||||
Command: 4, Timestamp: 12458, Bank: 0
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:42
|
||||
gem5 started Mar 15 2016 21:52:46
|
||||
gem5 executing on phenom, pid 15993
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:38:25
|
||||
gem5 executing on e108600-lin, pid 23095
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
|
|
@ -29,7 +30,7 @@ have_security=false
|
|||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -41,10 +42,14 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
|
|
@ -61,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -89,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -124,6 +134,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -162,6 +173,10 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -221,12 +236,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -245,8 +265,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -269,9 +294,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu0.dtb]
|
||||
|
|
@ -285,9 +315,14 @@ walker=system.cpu0.dtb.walker
|
|||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -605,12 +640,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -629,8 +669,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -688,9 +733,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu0.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu0.itb]
|
||||
|
|
@ -704,9 +754,14 @@ walker=system.cpu0.itb.walker
|
|||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -738,6 +793,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=8
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -776,6 +832,10 @@ numPhysIntRegs=256
|
|||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -845,9 +905,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.dtb]
|
||||
|
|
@ -861,9 +926,14 @@ walker=system.cpu1.dtb.walker
|
|||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.fuPool]
|
||||
|
|
@ -1223,9 +1293,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu1.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.itb]
|
||||
|
|
@ -1239,9 +1314,14 @@ walker=system.cpu1.itb.walker
|
|||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
|
|
@ -1272,9 +1352,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -1288,12 +1373,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -1312,8 +1402,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -1324,12 +1419,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -1348,8 +1448,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -1357,10 +1462,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
|
|
@ -1374,11 +1484,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1430,6 +1545,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -1441,7 +1557,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -1484,10 +1604,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -1568,14 +1693,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -1584,13 +1714,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -1671,10 +1806,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -1754,17 +1894,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -1790,13 +1935,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -1804,14 +1954,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -1897,14 +2052,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1913,13 +2073,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1928,13 +2093,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1942,11 +2112,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1960,11 +2135,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1978,12 +2158,17 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
|
|
@ -2051,10 +2236,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -2063,11 +2253,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -2077,21 +2272,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=16
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=0
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -2101,12 +2306,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -2115,10 +2325,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -2128,12 +2343,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -2143,26 +2363,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -2171,10 +2401,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -2182,10 +2417,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -2193,21 +2433,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -2221,11 +2471,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -2236,11 +2491,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -2248,10 +2508,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
@ -2267,10 +2532,15 @@ port=3456
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: Not doing anything for miscreg ACTLR
|
||||
warn: Not doing anything for write of miscreg ACTLR
|
||||
|
|
@ -40,19 +42,15 @@ warn: Ignoring write to miscreg pmintenclr
|
|||
warn: Ignoring write to miscreg pmovsr
|
||||
warn: Ignoring write to miscreg pmcr
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[2]
|
||||
warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[2]
|
||||
warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
|
||||
warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
|
||||
warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3]
|
||||
warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3]
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[0]
|
||||
warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[3]
|
||||
warn: instruction 'mcr dcisw' unimplemented
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0]
|
||||
warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7]
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
@ -62,3 +60,7 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:42
|
||||
gem5 started Mar 15 2016 21:34:31
|
||||
gem5 executing on phenom, pid 15967
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 15:03:28
|
||||
gem5 executing on e108600-lin, pid 24169
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
|
||||
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
|
|
|
|||
|
|
@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:42
|
||||
gem5 started Mar 15 2016 21:34:31
|
||||
gem5 executing on phenom, pid 15970
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 15:03:52
|
||||
gem5 executing on e108600-lin, pid 24173
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor-dual
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 47454492026000 because m5_exit instruction encountered
|
||||
Exiting @ tick 47445489241000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -32,135 +32,135 @@
|
|||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000028] Console: colour dummy device 80x25
|
||||
[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000032] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000199] hw perfevents: no hardware support available
|
||||
[ 0.060051] CPU1: Booted secondary processor
|
||||
[ 1.080085] CPU2: failed to come online
|
||||
[ 2.100161] CPU3: failed to come online
|
||||
[ 2.100164] Brought up 2 CPUs
|
||||
[ 2.100165] SMP: Total of 2 processors activated.
|
||||
[ 2.100234] devtmpfs: initialized
|
||||
[ 2.100742] atomic64_test: passed
|
||||
[ 2.100794] regulator-dummy: no parameters
|
||||
[ 2.101157] NET: Registered protocol family 16
|
||||
[ 2.101296] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.101304] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.102113] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.102117] Serial: AMBA PL011 UART driver
|
||||
[ 2.102318] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.102358] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.102933] console [ttyAMA0] enabled
|
||||
[ 2.103072] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.103132] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.103192] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.103250] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.140336] 3V3: 3300 mV
|
||||
[ 2.140383] vgaarb: loaded
|
||||
[ 2.140429] SCSI subsystem initialized
|
||||
[ 2.140466] libata version 3.00 loaded.
|
||||
[ 2.140524] usbcore: registered new interface driver usbfs
|
||||
[ 2.140543] usbcore: registered new interface driver hub
|
||||
[ 2.140567] usbcore: registered new device driver usb
|
||||
[ 2.140593] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.140602] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.140621] PTP clock support registered
|
||||
[ 2.140762] Switched to clocksource arch_sys_counter
|
||||
[ 2.141783] NET: Registered protocol family 2
|
||||
[ 2.141863] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.141880] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.141897] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.141925] TCP: reno registered
|
||||
[ 2.141932] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141945] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141981] NET: Registered protocol family 1
|
||||
[ 2.142034] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.142044] RPC: Registered udp transport module.
|
||||
[ 2.142052] RPC: Registered tcp transport module.
|
||||
[ 2.142061] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.142073] PCI: CLS 0 bytes, default 64
|
||||
[ 2.142235] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.142334] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.144468] fuse init (API version 7.23)
|
||||
[ 2.144588] msgmni has been set to 469
|
||||
[ 2.144697] io scheduler noop registered
|
||||
[ 2.144749] io scheduler cfq registered (default)
|
||||
[ 2.145214] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.145228] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.145239] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.145252] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.145262] pci_bus 0000:00: scanning bus
|
||||
[ 2.145274] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.145288] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.145302] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.145340] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.145352] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.145363] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.145373] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.145384] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.145395] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.145406] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.145441] pci_bus 0000:00: fixups for bus
|
||||
[ 2.145450] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.145462] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.145483] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.145492] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.145502] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.145511] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.145524] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.145538] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.145551] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.145564] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.145576] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.145587] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.145599] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.145610] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.146274] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.146553] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.146565] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.146593] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.146864] scsi0 : ata_piix
|
||||
[ 2.146948] scsi1 : ata_piix
|
||||
[ 2.146979] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.146991] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.147095] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.147108] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.147123] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.147134] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.290805] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.290816] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.290846] ata1.00: configured for UDMA/33
|
||||
[ 2.290909] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.291028] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.291029] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.291056] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.291067] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.291092] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.291248] sda: sda1
|
||||
[ 2.291370] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.411068] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.411082] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.411104] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.411115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.411135] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.411147] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.411217] usbcore: registered new interface driver usb-storage
|
||||
[ 2.411286] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.411453] usbcore: registered new interface driver usbhid
|
||||
[ 2.411463] usbhid: USB HID core driver
|
||||
[ 2.411495] TCP: cubic registered
|
||||
[ 2.411502] NET: Registered protocol family 17
|
||||
[ 2.411926] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.411975] devtmpfs: mounted
|
||||
[ 2.412025] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
[ 0.000023] Console: colour dummy device 80x25
|
||||
[ 0.000025] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000027] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000038] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000039] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000155] hw perfevents: no hardware support available
|
||||
[ 0.060041] CPU1: Booted secondary processor
|
||||
[ 1.080079] CPU2: failed to come online
|
||||
[ 2.100151] CPU3: failed to come online
|
||||
[ 2.100154] Brought up 2 CPUs
|
||||
[ 2.100155] SMP: Total of 2 processors activated.
|
||||
[ 2.100226] devtmpfs: initialized
|
||||
[ 2.100722] atomic64_test: passed
|
||||
[ 2.100767] regulator-dummy: no parameters
|
||||
[ 2.101110] NET: Registered protocol family 16
|
||||
[ 2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.101651] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.101655] Serial: AMBA PL011 UART driver
|
||||
[ 2.101841] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.101878] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.102452] console [ttyAMA0] enabled
|
||||
[ 2.102605] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.102668] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.102733] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.102790] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.140329] 3V3: 3300 mV
|
||||
[ 2.140389] vgaarb: loaded
|
||||
[ 2.140455] SCSI subsystem initialized
|
||||
[ 2.140504] libata version 3.00 loaded.
|
||||
[ 2.140588] usbcore: registered new interface driver usbfs
|
||||
[ 2.140613] usbcore: registered new interface driver hub
|
||||
[ 2.140641] usbcore: registered new device driver usb
|
||||
[ 2.140687] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.140698] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.140722] PTP clock support registered
|
||||
[ 2.140900] Switched to clocksource arch_sys_counter
|
||||
[ 2.142431] NET: Registered protocol family 2
|
||||
[ 2.142518] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.142535] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.142552] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.142574] TCP: reno registered
|
||||
[ 2.142581] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.142593] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.142627] NET: Registered protocol family 1
|
||||
[ 2.142670] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.142681] RPC: Registered udp transport module.
|
||||
[ 2.142689] RPC: Registered tcp transport module.
|
||||
[ 2.142698] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.142710] PCI: CLS 0 bytes, default 64
|
||||
[ 2.142942] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.143052] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.145204] fuse init (API version 7.23)
|
||||
[ 2.145320] msgmni has been set to 469
|
||||
[ 2.145427] io scheduler noop registered
|
||||
[ 2.145479] io scheduler cfq registered (default)
|
||||
[ 2.145859] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.145872] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.145883] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.145896] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.145906] pci_bus 0000:00: scanning bus
|
||||
[ 2.145917] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.145930] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.145945] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.145979] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.145991] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.146002] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.146013] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.146024] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.146035] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.146046] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.146081] pci_bus 0000:00: fixups for bus
|
||||
[ 2.146089] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.146101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.146121] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.146129] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.146140] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.146149] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.146160] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.146173] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.146186] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.146199] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.146211] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.146222] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.146234] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.146245] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.146902] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.147174] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.147184] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.147208] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.147469] scsi0 : ata_piix
|
||||
[ 2.147563] scsi1 : ata_piix
|
||||
[ 2.147592] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.147605] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.147706] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.147719] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.147733] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.147745] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.290935] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.290946] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.290974] ata1.00: configured for UDMA/33
|
||||
[ 2.291028] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.291135] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.291142] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.291184] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.291194] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.291214] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.291351] sda: sda1
|
||||
[ 2.291468] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.411201] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.411215] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.411238] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.411249] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.411270] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.411282] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.411355] usbcore: registered new interface driver usb-storage
|
||||
[ 2.411408] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.411558] usbcore: registered new interface driver usbhid
|
||||
[ 2.411568] usbhid: USB HID core driver
|
||||
[ 2.411600] TCP: cubic registered
|
||||
[ 2.411608] NET: Registered protocol family 17
|
||||
[ 2.411950] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.411985] devtmpfs: mounted
|
||||
[ 2.412018] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 2.460540] udevd[609]: starting version 182
|
||||
[ 2.450547] udevd[609]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 2.553667] random: dd urandom read with 18 bits of entropy available
|
||||
[ 2.513635] random: dd urandom read with 17 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
|
|||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
INIT: Entering runlevel: 5
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
[ 2.680995] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
[ 2.641130] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
|
|
|
|||
|
|
@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
flags_addr=469827632
|
||||
gic_cpu_addr=738205696
|
||||
have_large_asid_64=false
|
||||
have_lpae=false
|
||||
have_lpae=true
|
||||
have_security=false
|
||||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -40,12 +42,18 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -86,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -108,6 +121,7 @@ decodeCycleInput=true
|
|||
decodeInputBufferSize=3
|
||||
decodeInputWidth=2
|
||||
decodeToExecuteForwardDelay=1
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -152,12 +166,17 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
socket_id=0
|
||||
switched_out=false
|
||||
system=system
|
||||
threadPolicy=RoundRobin
|
||||
tracer=system.cpu.tracer
|
||||
workload=
|
||||
dcache_port=system.cpu.dcache.cpu_side
|
||||
|
|
@ -173,11 +192,18 @@ choicePredictorSize=8192
|
|||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
|
|
@ -186,13 +212,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -211,8 +241,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -235,9 +270,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -251,9 +291,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -647,13 +692,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -672,8 +721,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -731,9 +785,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -747,9 +806,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -760,13 +824,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -785,8 +853,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -794,9 +867,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -841,9 +920,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -857,13 +941,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -882,8 +970,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -891,9 +984,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -907,11 +1006,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -956,6 +1060,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -967,7 +1072,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -1010,10 +1119,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -1094,14 +1208,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -1110,13 +1229,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -1126,6 +1250,7 @@ pio=system.iobus.master[5]
|
|||
type=SubSystem
|
||||
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.dcc.osc_cpu]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1196,10 +1321,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -1279,17 +1409,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -1315,12 +1450,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -1328,14 +1469,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -1421,14 +1567,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1437,13 +1588,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1452,13 +1608,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1466,11 +1627,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1484,11 +1650,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1502,19 +1673,25 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.mcc]
|
||||
type=SubSystem
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.mcc.osc_clcd]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1560,14 +1737,29 @@ position=0
|
|||
site=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.realview.mcc.temp_crtl]
|
||||
type=RealViewTemperatureSensor
|
||||
dcc=0
|
||||
device=0
|
||||
eventq_index=0
|
||||
parent=system.realview.realview_io
|
||||
position=0
|
||||
site=0
|
||||
system=system
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1576,11 +1768,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1590,21 +1787,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=12
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=788529152
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1614,12 +1821,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1628,10 +1840,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1641,12 +1858,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1656,26 +1878,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1684,10 +1916,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1695,10 +1932,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1706,21 +1948,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1734,11 +1986,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1749,11 +2006,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1761,10 +2023,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 13:24:25
|
||||
gem5 executing on e104799-lin, pid 9941
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:41:22
|
||||
gem5 executing on e108600-lin, pid 23124
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-minor
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51667481628000 because m5_exit instruction encountered
|
||||
Exiting @ tick 51660717372000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -32,135 +32,135 @@
|
|||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000032] Console: colour dummy device 80x25
|
||||
[ 0.000035] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000037] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000053] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000054] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000248] hw perfevents: no hardware support available
|
||||
[ 0.000031] Console: colour dummy device 80x25
|
||||
[ 0.000034] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000036] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000052] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000053] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000228] hw perfevents: no hardware support available
|
||||
[ 1.060097] CPU1: failed to come online
|
||||
[ 2.080186] CPU2: failed to come online
|
||||
[ 3.100276] CPU3: failed to come online
|
||||
[ 3.100280] Brought up 1 CPUs
|
||||
[ 3.100282] SMP: Total of 1 processors activated.
|
||||
[ 2.080187] CPU2: failed to come online
|
||||
[ 3.100278] CPU3: failed to come online
|
||||
[ 3.100282] Brought up 1 CPUs
|
||||
[ 3.100283] SMP: Total of 1 processors activated.
|
||||
[ 3.100367] devtmpfs: initialized
|
||||
[ 3.101026] atomic64_test: passed
|
||||
[ 3.101090] regulator-dummy: no parameters
|
||||
[ 3.101671] NET: Registered protocol family 16
|
||||
[ 3.101853] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.101865] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.103085] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.103092] Serial: AMBA PL011 UART driver
|
||||
[ 3.103368] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.103418] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.103982] console [ttyAMA0] enabled
|
||||
[ 3.104097] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.104134] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.104172] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.104207] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130720] 3V3: 3300 mV
|
||||
[ 3.101019] atomic64_test: passed
|
||||
[ 3.101081] regulator-dummy: no parameters
|
||||
[ 3.101652] NET: Registered protocol family 16
|
||||
[ 3.101829] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.101840] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.102554] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.102561] Serial: AMBA PL011 UART driver
|
||||
[ 3.102830] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.102879] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.103440] console [ttyAMA0] enabled
|
||||
[ 3.103555] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.103592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.103630] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.103665] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130723] 3V3: 3300 mV
|
||||
[ 3.130781] vgaarb: loaded
|
||||
[ 3.130844] SCSI subsystem initialized
|
||||
[ 3.130897] libata version 3.00 loaded.
|
||||
[ 3.130958] usbcore: registered new interface driver usbfs
|
||||
[ 3.130980] usbcore: registered new interface driver hub
|
||||
[ 3.131022] usbcore: registered new device driver usb
|
||||
[ 3.131056] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.131065] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.131086] PTP clock support registered
|
||||
[ 3.131251] Switched to clocksource arch_sys_counter
|
||||
[ 3.132743] NET: Registered protocol family 2
|
||||
[ 3.132852] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.132877] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.132908] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.132927] TCP: reno registered
|
||||
[ 3.132934] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132951] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.133006] NET: Registered protocol family 1
|
||||
[ 3.133062] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.133072] RPC: Registered udp transport module.
|
||||
[ 3.133081] RPC: Registered tcp transport module.
|
||||
[ 3.133089] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.133102] PCI: CLS 0 bytes, default 64
|
||||
[ 3.133312] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.133481] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.135738] fuse init (API version 7.23)
|
||||
[ 3.135850] msgmni has been set to 469
|
||||
[ 3.139064] io scheduler noop registered
|
||||
[ 3.139133] io scheduler cfq registered (default)
|
||||
[ 3.139792] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.139806] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.139818] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.139830] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.139841] pci_bus 0000:00: scanning bus
|
||||
[ 3.139853] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.139868] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.139883] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.139931] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.139944] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.139955] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.139966] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.139978] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.139989] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.140001] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.140044] pci_bus 0000:00: fixups for bus
|
||||
[ 3.140052] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.140066] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.140089] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.140098] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.140110] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.140119] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.140132] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.140146] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.140159] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.140173] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.140185] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.140197] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.140209] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.140221] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.140886] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.141268] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.141280] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.141313] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.141940] scsi0 : ata_piix
|
||||
[ 3.142073] scsi1 : ata_piix
|
||||
[ 3.142110] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.142123] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.142257] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.142269] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.142286] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.142298] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.301286] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.301296] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.301328] ata1.00: configured for UDMA/33
|
||||
[ 3.301395] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.301536] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.301567] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.301615] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.301625] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.301650] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.301813] sda: sda1
|
||||
[ 3.301968] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.421575] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.421589] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.421613] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.421623] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.421648] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.421660] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.421747] usbcore: registered new interface driver usb-storage
|
||||
[ 3.421815] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.422009] usbcore: registered new interface driver usbhid
|
||||
[ 3.422020] usbhid: USB HID core driver
|
||||
[ 3.422060] TCP: cubic registered
|
||||
[ 3.422068] NET: Registered protocol family 17
|
||||
[ 3.422528] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.422570] devtmpfs: mounted
|
||||
[ 3.422641] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
[ 3.130956] usbcore: registered new interface driver usbfs
|
||||
[ 3.130977] usbcore: registered new interface driver hub
|
||||
[ 3.131019] usbcore: registered new device driver usb
|
||||
[ 3.131051] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.131061] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.131081] PTP clock support registered
|
||||
[ 3.131243] Switched to clocksource arch_sys_counter
|
||||
[ 3.132709] NET: Registered protocol family 2
|
||||
[ 3.132818] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.132843] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.132874] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.132892] TCP: reno registered
|
||||
[ 3.132900] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132916] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132971] NET: Registered protocol family 1
|
||||
[ 3.133024] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.133035] RPC: Registered udp transport module.
|
||||
[ 3.133043] RPC: Registered tcp transport module.
|
||||
[ 3.133051] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.133064] PCI: CLS 0 bytes, default 64
|
||||
[ 3.133270] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.133439] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.135679] fuse init (API version 7.23)
|
||||
[ 3.135790] msgmni has been set to 469
|
||||
[ 3.138999] io scheduler noop registered
|
||||
[ 3.139069] io scheduler cfq registered (default)
|
||||
[ 3.139634] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.139648] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.139659] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.139672] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.139682] pci_bus 0000:00: scanning bus
|
||||
[ 3.139694] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.139709] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.139724] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.139771] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.139784] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.139795] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.139806] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.139818] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.139829] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.139841] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.139883] pci_bus 0000:00: fixups for bus
|
||||
[ 3.139892] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.139905] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.139929] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.139938] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.139949] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.139958] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.139971] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.139985] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.139998] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.140011] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.140023] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.140035] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.140047] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.140059] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.140718] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.141064] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.141076] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.141104] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.141758] scsi0 : ata_piix
|
||||
[ 3.141889] scsi1 : ata_piix
|
||||
[ 3.141926] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.141938] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.142070] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.142082] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.142099] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.142111] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.301279] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.301289] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.301320] ata1.00: configured for UDMA/33
|
||||
[ 3.301387] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.301528] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.301559] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.301607] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.301617] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.301642] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.301803] sda: sda1
|
||||
[ 3.301959] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.421568] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.421582] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.421605] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.421616] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.421640] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.421652] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.421739] usbcore: registered new interface driver usb-storage
|
||||
[ 3.421808] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.422005] usbcore: registered new interface driver usbhid
|
||||
[ 3.422015] usbhid: USB HID core driver
|
||||
[ 3.422054] TCP: cubic registered
|
||||
[ 3.422062] NET: Registered protocol family 17
|
||||
[ 3.422515] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.422556] devtmpfs: mounted
|
||||
[ 3.422604] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 3.464661] udevd[607]: starting version 182
|
||||
[ 3.464675] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 3.594831] random: dd urandom read with 20 bits of entropy available
|
||||
[ 3.594846] random: dd urandom read with 20 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
|
|||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
INIT: Entering runlevel: 5
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
[ 3.761486] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
[ 3.761479] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
|
|
|
|||
|
|
@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
flags_addr=469827632
|
||||
gic_cpu_addr=738205696
|
||||
have_large_asid_64=false
|
||||
have_lpae=false
|
||||
have_lpae=true
|
||||
have_security=false
|
||||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -40,12 +42,18 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -86,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -121,6 +134,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -159,6 +173,10 @@ numPhysIntRegs=128
|
|||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -198,8 +216,15 @@ choicePredictorSize=8192
|
|||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.checker]
|
||||
type=O3Checker
|
||||
|
|
@ -207,6 +232,7 @@ children=dstage2_mmu dtb isa istage2_mmu itb tracer
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -225,6 +251,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -255,9 +285,14 @@ walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.checker.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.checker.dtb]
|
||||
|
|
@ -271,9 +306,14 @@ walker=system.cpu.checker.dtb.walker
|
|||
[system.cpu.checker.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[5]
|
||||
|
||||
|
|
@ -327,9 +367,14 @@ walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.checker.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.checker.itb]
|
||||
|
|
@ -343,9 +388,14 @@ walker=system.cpu.checker.itb.walker
|
|||
[system.cpu.checker.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[4]
|
||||
|
||||
|
|
@ -360,13 +410,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -385,8 +439,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -409,9 +468,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -425,9 +489,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -703,13 +772,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -728,8 +801,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -787,9 +865,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -803,9 +886,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -816,13 +904,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -841,8 +933,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -850,9 +947,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -897,9 +1000,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -913,13 +1021,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -938,8 +1050,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -947,9 +1064,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -963,11 +1086,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1012,6 +1140,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -1023,7 +1152,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -1066,10 +1199,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -1150,14 +1288,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -1166,13 +1309,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -1182,6 +1330,7 @@ pio=system.iobus.master[5]
|
|||
type=SubSystem
|
||||
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.dcc.osc_cpu]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1252,10 +1401,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -1335,17 +1489,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -1371,12 +1530,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -1384,14 +1549,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -1477,14 +1647,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1493,13 +1668,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1508,13 +1688,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1522,11 +1707,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1540,11 +1730,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1558,19 +1753,25 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.mcc]
|
||||
type=SubSystem
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.mcc.osc_clcd]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1616,14 +1817,29 @@ position=0
|
|||
site=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.realview.mcc.temp_crtl]
|
||||
type=RealViewTemperatureSensor
|
||||
dcc=0
|
||||
device=0
|
||||
eventq_index=0
|
||||
parent=system.realview.realview_io
|
||||
position=0
|
||||
site=0
|
||||
system=system
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1632,11 +1848,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1646,21 +1867,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=12
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=788529152
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1670,12 +1901,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1684,10 +1920,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1697,12 +1938,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1712,26 +1958,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1740,10 +1996,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1751,10 +2012,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1762,21 +2028,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1790,11 +2066,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1805,11 +2086,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1817,10 +2103,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
|
|
@ -3,101 +3,90 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: 12469689449500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0
|
||||
warn: 12469692907500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
|
||||
warn: 12465253480500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0
|
||||
warn: 12465256875500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: 13859656146500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13859950489500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13860549714500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13861141715500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13861425606000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13887655302500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13887984972000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13888175197500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13888527468000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13926855654000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13927074222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13927622636000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13927831908000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13928069949000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13928309196000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13944831907000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13960769373500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 14182895786500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14182896036500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14182896282500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14191041595500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14198847599000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14198848114500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14198848578500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14206625430000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14206625664000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14206625894000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14211939480000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14211939710000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14218406091500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14218406321500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14228222612500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14228222857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14228223366500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14228223600500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14228223830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14228224037000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14239432062500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14239432572000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14239432806000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14239433036000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14239433242500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14249200202500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14249200432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14264670876000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14264671403500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14264671637500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14264671867500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14264672074000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14269733190000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14276719950000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14276720459500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14276720693500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14276720923500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14276721130000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14286856693000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14349944433000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14349944681500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14349944897000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14407864195500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14407864763000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14407865015500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14407865264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14407865479500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14533528504500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14533619061000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
|
||||
warn: 14533620387500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14533622455000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14533622773500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534367031000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534367292000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
|
||||
warn: 14534367496500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534438304500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
|
||||
warn: 14534438514500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534438785500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
|
||||
warn: 14534439356000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534439611500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
|
||||
warn: 14534439835000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534440124000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534440633000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534441696000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534442194000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14534442496000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14583340343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 14583519554000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
|
||||
warn: 14583519838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14583520090000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14583520334500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14583520596500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14583520826000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
|
||||
warn: 13848743916500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13856080320500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13856660917500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13856932644000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13891365050500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13914492463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13915494038500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13915724569500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13929415957500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 13975739128500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
|
||||
warn: 14218303751000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14218304352000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14218304616500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14218304863000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14218305076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14234303193500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14242116775500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14242117552500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14242117792000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14242117998500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14247408751000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14247409260500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14247409494500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14247409734000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14247409931000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14253842696500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14253843672000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14253843878500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14263637803000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14263638037500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14263638268000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14263638474500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14274868668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14274868899000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14274869105500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14284684734000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14284685479000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14284685709500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14300304682500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14300304916500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14300305146500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14305416988000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14305417218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14305417424500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14312475874500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14312476114000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14322624432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14322624672000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14337182893000: Instruction results do not match! (Values may not actually be integers) Inst: 0x48, checker: 0x49
|
||||
warn: 14386098021000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14444180838500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14444181087000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14568925614000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569017181500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569017437000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
|
||||
warn: 14569020030500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569020349000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569750354000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569750626000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
|
||||
warn: 14569750836000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569821557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
|
||||
warn: 14569821767500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569822044000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
|
||||
warn: 14569822614500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569822870000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
|
||||
warn: 14569823093500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569823382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569823891500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569824954500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569825452500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14569825754500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
|
||||
warn: 14618889380500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
|
||||
warn: 14618889688000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14618889945500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14618890194000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14618890463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
|
||||
warn: 14618890702500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 14:35:47
|
||||
gem5 executing on e104799-lin, pid 16996
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:39:11
|
||||
gem5 executing on e108600-lin, pid 23099
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-checker
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51291805611000 because m5_exit instruction encountered
|
||||
Exiting @ tick 51327142820000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -31,136 +31,136 @@
|
|||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000022] Console: colour dummy device 80x25
|
||||
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000021] Console: colour dummy device 80x25
|
||||
[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000025] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000160] hw perfevents: no hardware support available
|
||||
[ 1.060067] CPU1: failed to come online
|
||||
[ 2.080129] CPU2: failed to come online
|
||||
[ 3.100191] CPU3: failed to come online
|
||||
[ 3.100194] Brought up 1 CPUs
|
||||
[ 3.100195] SMP: Total of 1 processors activated.
|
||||
[ 3.100251] devtmpfs: initialized
|
||||
[ 3.100700] atomic64_test: passed
|
||||
[ 3.100743] regulator-dummy: no parameters
|
||||
[ 3.101166] NET: Registered protocol family 16
|
||||
[ 3.101292] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.101301] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.102003] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.102008] Serial: AMBA PL011 UART driver
|
||||
[ 3.102194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.102227] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.102794] console [ttyAMA0] enabled
|
||||
[ 3.102873] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.102904] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.102936] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.102965] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130500] 3V3: 3300 mV
|
||||
[ 3.130542] vgaarb: loaded
|
||||
[ 3.130589] SCSI subsystem initialized
|
||||
[ 3.130626] libata version 3.00 loaded.
|
||||
[ 3.130670] usbcore: registered new interface driver usbfs
|
||||
[ 3.130688] usbcore: registered new interface driver hub
|
||||
[ 3.130719] usbcore: registered new device driver usb
|
||||
[ 3.130744] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.130753] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.130772] PTP clock support registered
|
||||
[ 3.130888] Switched to clocksource arch_sys_counter
|
||||
[ 3.131885] NET: Registered protocol family 2
|
||||
[ 3.131959] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.131977] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.131999] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.132014] TCP: reno registered
|
||||
[ 3.132021] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132036] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132076] NET: Registered protocol family 1
|
||||
[ 3.132127] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.132137] RPC: Registered udp transport module.
|
||||
[ 3.132145] RPC: Registered tcp transport module.
|
||||
[ 3.132153] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.132165] PCI: CLS 0 bytes, default 64
|
||||
[ 3.132312] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.132411] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.133969] fuse init (API version 7.23)
|
||||
[ 3.134047] msgmni has been set to 469
|
||||
[ 3.136178] io scheduler noop registered
|
||||
[ 3.136228] io scheduler cfq registered (default)
|
||||
[ 3.136665] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.136678] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.136689] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.136702] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.136712] pci_bus 0000:00: scanning bus
|
||||
[ 3.136722] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.136735] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.136749] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136786] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.136798] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.136809] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.136819] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.136830] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.136841] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136885] pci_bus 0000:00: fixups for bus
|
||||
[ 3.136893] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.136925] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.136933] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.136944] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.136952] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.137002] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.137014] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.137025] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.137036] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.137048] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.137735] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.137770] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.138035] scsi0 : ata_piix
|
||||
[ 3.138128] scsi1 : ata_piix
|
||||
[ 3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.138306] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.290924] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.290951] ata1.00: configured for UDMA/33
|
||||
[ 3.291001] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.291104] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.291128] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.291165] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.291174] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.291193] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.291307] sda: sda1
|
||||
[ 3.291413] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.411182] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.411195] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.411215] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.411225] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.411245] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.411257] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.411320] usbcore: registered new interface driver usb-storage
|
||||
[ 3.411372] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.411510] usbcore: registered new interface driver usbhid
|
||||
[ 3.411519] usbhid: USB HID core driver
|
||||
[ 3.411550] TCP: cubic registered
|
||||
[ 3.411558] NET: Registered protocol family 17
|
||||
[ 3.411890] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.411924] devtmpfs: mounted
|
||||
[ 3.411972] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
[ 0.000147] hw perfevents: no hardware support available
|
||||
[ 1.060066] CPU1: failed to come online
|
||||
[ 2.080127] CPU2: failed to come online
|
||||
[ 3.100188] CPU3: failed to come online
|
||||
[ 3.100191] Brought up 1 CPUs
|
||||
[ 3.100192] SMP: Total of 1 processors activated.
|
||||
[ 3.100247] devtmpfs: initialized
|
||||
[ 3.100685] atomic64_test: passed
|
||||
[ 3.100727] regulator-dummy: no parameters
|
||||
[ 3.101141] NET: Registered protocol family 16
|
||||
[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.101638] Serial: AMBA PL011 UART driver
|
||||
[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.102416] console [ttyAMA0] enabled
|
||||
[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130494] 3V3: 3300 mV
|
||||
[ 3.130534] vgaarb: loaded
|
||||
[ 3.130580] SCSI subsystem initialized
|
||||
[ 3.130617] libata version 3.00 loaded.
|
||||
[ 3.130659] usbcore: registered new interface driver usbfs
|
||||
[ 3.130676] usbcore: registered new interface driver hub
|
||||
[ 3.130707] usbcore: registered new device driver usb
|
||||
[ 3.130732] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.130759] PTP clock support registered
|
||||
[ 3.130873] Switched to clocksource arch_sys_counter
|
||||
[ 3.131846] NET: Registered protocol family 2
|
||||
[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.131975] TCP: reno registered
|
||||
[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132036] NET: Registered protocol family 1
|
||||
[ 3.132085] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.132095] RPC: Registered udp transport module.
|
||||
[ 3.132103] RPC: Registered tcp transport module.
|
||||
[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.132123] PCI: CLS 0 bytes, default 64
|
||||
[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.133901] fuse init (API version 7.23)
|
||||
[ 3.133978] msgmni has been set to 469
|
||||
[ 3.136097] io scheduler noop registered
|
||||
[ 3.136147] io scheduler cfq registered (default)
|
||||
[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.136562] pci_bus 0000:00: scanning bus
|
||||
[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136734] pci_bus 0000:00: fixups for bus
|
||||
[ 3.136742] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.136774] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.136782] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.136793] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.136801] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.137572] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.137866] scsi0 : ata_piix
|
||||
[ 3.137956] scsi1 : ata_piix
|
||||
[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.138131] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.290935] ata1.00: configured for UDMA/33
|
||||
[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.291287] sda: sda1
|
||||
[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.411304] usbcore: registered new interface driver usb-storage
|
||||
[ 3.411354] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.411491] usbcore: registered new interface driver usbhid
|
||||
[ 3.411501] usbhid: USB HID core driver
|
||||
[ 3.411531] TCP: cubic registered
|
||||
[ 3.411538] NET: Registered protocol family 17
|
||||
[ 3.411866] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.411900] devtmpfs: mounted
|
||||
[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 3.450398] udevd[607]: starting version 182
|
||||
[ 3.450359] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 3.533417] random: dd urandom read with 19 bits of entropy available
|
||||
[ 3.543431] random: dd urandom read with 19 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
|
|||
Mon Jan 27 08:00:00 UTC 2014
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
INIT: Entering runlevel: 5
|
||||
Configuring network interfaces... [ 3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
udhcpc (v1.21.1) started
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
|
|
@ -11,3 +13,4 @@ warn: allocating bonus target for snoop
|
|||
warn: allocating bonus target for snoop
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: allocating bonus target for snoop
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 13:59:02
|
||||
gem5 executing on e104799-lin, pid 13304
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:49:48
|
||||
gem5 executing on e108600-lin, pid 23303
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-dual
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 47393980707000 because m5_exit instruction encountered
|
||||
Exiting @ tick 47384351300000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -32,135 +32,135 @@
|
|||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000018] Console: colour dummy device 80x25
|
||||
[ 0.000020] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000021] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000029] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000030] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000132] hw perfevents: no hardware support available
|
||||
[ 0.060034] CPU1: Booted secondary processor
|
||||
[ 1.080058] CPU2: failed to come online
|
||||
[ 2.100109] CPU3: failed to come online
|
||||
[ 2.100111] Brought up 2 CPUs
|
||||
[ 2.100112] SMP: Total of 2 processors activated.
|
||||
[ 2.100158] devtmpfs: initialized
|
||||
[ 2.100486] atomic64_test: passed
|
||||
[ 2.100520] regulator-dummy: no parameters
|
||||
[ 2.100764] NET: Registered protocol family 16
|
||||
[ 2.100855] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.100862] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.101406] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.101409] Serial: AMBA PL011 UART driver
|
||||
[ 2.101542] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.101569] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.102150] console [ttyAMA0] enabled
|
||||
[ 2.102255] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.102304] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.102356] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.102402] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.140243] 3V3: 3300 mV
|
||||
[ 2.140289] vgaarb: loaded
|
||||
[ 2.140336] SCSI subsystem initialized
|
||||
[ 2.140372] libata version 3.00 loaded.
|
||||
[ 2.140432] usbcore: registered new interface driver usbfs
|
||||
[ 2.140452] usbcore: registered new interface driver hub
|
||||
[ 2.140475] usbcore: registered new device driver usb
|
||||
[ 2.140509] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.140519] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.140540] PTP clock support registered
|
||||
[ 2.140668] Switched to clocksource arch_sys_counter
|
||||
[ 2.141701] NET: Registered protocol family 2
|
||||
[ 2.141770] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.141785] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.141801] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.141824] TCP: reno registered
|
||||
[ 2.141831] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141842] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141872] NET: Registered protocol family 1
|
||||
[ 2.141906] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.141917] RPC: Registered udp transport module.
|
||||
[ 2.141925] RPC: Registered tcp transport module.
|
||||
[ 2.141933] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.141946] PCI: CLS 0 bytes, default 64
|
||||
[ 2.142111] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.142194] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.143636] fuse init (API version 7.23)
|
||||
[ 2.143718] msgmni has been set to 469
|
||||
[ 2.143799] io scheduler noop registered
|
||||
[ 2.143835] io scheduler cfq registered (default)
|
||||
[ 2.144137] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.144150] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.144161] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.144173] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.144183] pci_bus 0000:00: scanning bus
|
||||
[ 2.144193] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.144206] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.144220] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.144247] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.144259] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.144269] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.144280] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.144290] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.144301] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.144312] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.144339] pci_bus 0000:00: fixups for bus
|
||||
[ 2.144347] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.144358] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.144376] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.144384] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.144394] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.144402] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.144413] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.144426] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.144438] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.144451] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.144462] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.144473] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.144485] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.144496] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.144948] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.145137] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.145148] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.145169] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.145354] scsi0 : ata_piix
|
||||
[ 2.145413] scsi1 : ata_piix
|
||||
[ 2.145434] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.145446] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.145522] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.145534] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.145547] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.145559] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.290714] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.290739] ata1.00: configured for UDMA/33
|
||||
[ 2.290784] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.290883] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.290917] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.290926] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.290943] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.290996] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.291064] sda: sda1
|
||||
[ 2.291152] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.410949] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.410962] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.410980] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.410990] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.411008] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.411020] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.411070] usbcore: registered new interface driver usb-storage
|
||||
[ 2.411118] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.411225] usbcore: registered new interface driver usbhid
|
||||
[ 2.411235] usbhid: USB HID core driver
|
||||
[ 2.411260] TCP: cubic registered
|
||||
[ 2.411267] NET: Registered protocol family 17
|
||||
[ 2.411579] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.411619] devtmpfs: mounted
|
||||
[ 2.411656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
[ 0.000015] Console: colour dummy device 80x25
|
||||
[ 0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000017] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000024] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000025] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000098] hw perfevents: no hardware support available
|
||||
[ 0.060026] CPU1: Booted secondary processor
|
||||
[ 1.080051] CPU2: failed to come online
|
||||
[ 2.100096] CPU3: failed to come online
|
||||
[ 2.100099] Brought up 2 CPUs
|
||||
[ 2.100099] SMP: Total of 2 processors activated.
|
||||
[ 2.100138] devtmpfs: initialized
|
||||
[ 2.100443] atomic64_test: passed
|
||||
[ 2.100470] regulator-dummy: no parameters
|
||||
[ 2.100693] NET: Registered protocol family 16
|
||||
[ 2.100775] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.100781] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.100925] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.100928] Serial: AMBA PL011 UART driver
|
||||
[ 2.101044] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.101067] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.101650] console [ttyAMA0] enabled
|
||||
[ 2.101714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.101743] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.101771] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.101798] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.140207] 3V3: 3300 mV
|
||||
[ 2.140239] vgaarb: loaded
|
||||
[ 2.140270] SCSI subsystem initialized
|
||||
[ 2.140299] libata version 3.00 loaded.
|
||||
[ 2.140331] usbcore: registered new interface driver usbfs
|
||||
[ 2.140346] usbcore: registered new interface driver hub
|
||||
[ 2.140370] usbcore: registered new device driver usb
|
||||
[ 2.140390] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.140399] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.140417] PTP clock support registered
|
||||
[ 2.140503] Switched to clocksource arch_sys_counter
|
||||
[ 2.141444] NET: Registered protocol family 2
|
||||
[ 2.141497] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.141512] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.141527] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.141543] TCP: reno registered
|
||||
[ 2.141550] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141561] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.141588] NET: Registered protocol family 1
|
||||
[ 2.141628] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.141638] RPC: Registered udp transport module.
|
||||
[ 2.141647] RPC: Registered tcp transport module.
|
||||
[ 2.141655] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.141667] PCI: CLS 0 bytes, default 64
|
||||
[ 2.141771] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.141835] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.142859] fuse init (API version 7.23)
|
||||
[ 2.142916] msgmni has been set to 469
|
||||
[ 2.143149] io scheduler noop registered
|
||||
[ 2.143186] io scheduler cfq registered (default)
|
||||
[ 2.143405] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.143418] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.143429] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.143442] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.143451] pci_bus 0000:00: scanning bus
|
||||
[ 2.143461] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.143473] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.143487] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.143514] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.143526] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.143536] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.143547] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.143557] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.143567] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.143578] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.143604] pci_bus 0000:00: fixups for bus
|
||||
[ 2.143612] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.143623] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.143640] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.143648] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.143658] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.143666] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.143676] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.143689] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.143702] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.143715] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.143726] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.143737] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.143748] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.143759] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.144053] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.144214] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.144224] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.144241] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.144410] scsi0 : ata_piix
|
||||
[ 2.144458] scsi1 : ata_piix
|
||||
[ 2.144479] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.144492] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.144562] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.144575] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.144587] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.144599] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.290528] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.290538] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.290562] ata1.00: configured for UDMA/33
|
||||
[ 2.290599] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.290672] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.290676] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.290693] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.290693] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.290701] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.290789] sda: sda1
|
||||
[ 2.290864] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.410776] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.410789] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.410807] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.410817] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.410834] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.410846] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.410894] usbcore: registered new interface driver usb-storage
|
||||
[ 2.410940] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.411046] usbcore: registered new interface driver usbhid
|
||||
[ 2.411056] usbhid: USB HID core driver
|
||||
[ 2.411079] TCP: cubic registered
|
||||
[ 2.411086] NET: Registered protocol family 17
|
||||
[ 2.411358] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.411396] devtmpfs: mounted
|
||||
[ 2.411414] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 2.447817] udevd[609]: starting version 182
|
||||
[ 2.447448] udevd[609]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 2.532679] random: dd urandom read with 18 bits of entropy available
|
||||
[ 2.532422] random: dd urandom read with 18 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
|
|||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
INIT: Entering runlevel: 5
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
[ 2.640899] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
[ 2.640730] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
|
|
|
|||
|
|
@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
flags_addr=469827632
|
||||
gic_cpu_addr=738205696
|
||||
have_large_asid_64=false
|
||||
have_lpae=false
|
||||
have_lpae=true
|
||||
have_security=false
|
||||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -40,12 +42,18 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -86,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -121,6 +134,7 @@ cpu_id=0
|
|||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=2
|
||||
decodeWidth=3
|
||||
default_p_state=UNDEFINED
|
||||
dispatchWidth=6
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
|
|
@ -159,6 +173,10 @@ numPhysIntRegs=128
|
|||
numROBEntries=40
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
renameToDecodeDelay=1
|
||||
|
|
@ -198,8 +216,15 @@ choicePredictorSize=8192
|
|||
eventq_index=0
|
||||
globalCtrBits=2
|
||||
globalPredictorSize=8192
|
||||
indirectHashGHR=true
|
||||
indirectHashTargets=true
|
||||
indirectPathLength=3
|
||||
indirectSets=256
|
||||
indirectTagSize=16
|
||||
indirectWays=2
|
||||
instShiftAmt=2
|
||||
numThreads=1
|
||||
useIndirect=true
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=Cache
|
||||
|
|
@ -208,13 +233,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -233,8 +262,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -257,9 +291,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -273,9 +312,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -551,13 +595,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -576,8 +624,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -635,9 +688,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -651,9 +709,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -664,13 +727,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -689,8 +756,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -698,9 +770,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -745,9 +823,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -761,13 +844,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -786,8 +873,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -795,9 +887,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -811,11 +909,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -860,6 +963,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -871,7 +975,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -914,10 +1022,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -998,14 +1111,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -1014,13 +1132,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -1030,6 +1153,7 @@ pio=system.iobus.master[5]
|
|||
type=SubSystem
|
||||
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.dcc.osc_cpu]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1100,10 +1224,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -1183,17 +1312,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -1219,12 +1353,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -1232,14 +1372,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -1325,14 +1470,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1341,13 +1491,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1356,13 +1511,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1370,11 +1530,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1388,11 +1553,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1406,19 +1576,25 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.mcc]
|
||||
type=SubSystem
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.mcc.osc_clcd]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1464,14 +1640,29 @@ position=0
|
|||
site=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.realview.mcc.temp_crtl]
|
||||
type=RealViewTemperatureSensor
|
||||
dcc=0
|
||||
device=0
|
||||
eventq_index=0
|
||||
parent=system.realview.realview_io
|
||||
position=0
|
||||
site=0
|
||||
system=system
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1480,11 +1671,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1494,21 +1690,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=12
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=788529152
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1518,12 +1724,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1532,10 +1743,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1545,12 +1761,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1560,26 +1781,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1588,10 +1819,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1599,10 +1835,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1610,21 +1851,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1638,11 +1889,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1653,11 +1909,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1665,10 +1926,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 11:54:11
|
||||
gem5 executing on e104799-lin, pid 641
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:40:47
|
||||
gem5 executing on e108600-lin, pid 23116
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51291805611000 because m5_exit instruction encountered
|
||||
Exiting @ tick 51327142820000 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -31,136 +31,136 @@
|
|||
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
|
||||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000022] Console: colour dummy device 80x25
|
||||
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000021] Console: colour dummy device 80x25
|
||||
[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000025] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000160] hw perfevents: no hardware support available
|
||||
[ 1.060067] CPU1: failed to come online
|
||||
[ 2.080129] CPU2: failed to come online
|
||||
[ 3.100191] CPU3: failed to come online
|
||||
[ 3.100194] Brought up 1 CPUs
|
||||
[ 3.100195] SMP: Total of 1 processors activated.
|
||||
[ 3.100251] devtmpfs: initialized
|
||||
[ 3.100700] atomic64_test: passed
|
||||
[ 3.100743] regulator-dummy: no parameters
|
||||
[ 3.101166] NET: Registered protocol family 16
|
||||
[ 3.101292] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.101301] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.102003] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.102008] Serial: AMBA PL011 UART driver
|
||||
[ 3.102194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.102227] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.102794] console [ttyAMA0] enabled
|
||||
[ 3.102873] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.102904] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.102936] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.102965] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130500] 3V3: 3300 mV
|
||||
[ 3.130542] vgaarb: loaded
|
||||
[ 3.130589] SCSI subsystem initialized
|
||||
[ 3.130626] libata version 3.00 loaded.
|
||||
[ 3.130670] usbcore: registered new interface driver usbfs
|
||||
[ 3.130688] usbcore: registered new interface driver hub
|
||||
[ 3.130719] usbcore: registered new device driver usb
|
||||
[ 3.130744] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.130753] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.130772] PTP clock support registered
|
||||
[ 3.130888] Switched to clocksource arch_sys_counter
|
||||
[ 3.131885] NET: Registered protocol family 2
|
||||
[ 3.131959] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.131977] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.131999] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.132014] TCP: reno registered
|
||||
[ 3.132021] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132036] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132076] NET: Registered protocol family 1
|
||||
[ 3.132127] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.132137] RPC: Registered udp transport module.
|
||||
[ 3.132145] RPC: Registered tcp transport module.
|
||||
[ 3.132153] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.132165] PCI: CLS 0 bytes, default 64
|
||||
[ 3.132312] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.132411] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.133969] fuse init (API version 7.23)
|
||||
[ 3.134047] msgmni has been set to 469
|
||||
[ 3.136178] io scheduler noop registered
|
||||
[ 3.136228] io scheduler cfq registered (default)
|
||||
[ 3.136665] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.136678] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.136689] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.136702] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.136712] pci_bus 0000:00: scanning bus
|
||||
[ 3.136722] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.136735] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.136749] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136786] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.136798] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.136809] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.136819] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.136830] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.136841] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136885] pci_bus 0000:00: fixups for bus
|
||||
[ 3.136893] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.136925] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.136933] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.136944] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.136952] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.137002] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.137014] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.137025] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.137036] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.137048] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.137735] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.137770] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.138035] scsi0 : ata_piix
|
||||
[ 3.138128] scsi1 : ata_piix
|
||||
[ 3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.138306] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.290924] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.290951] ata1.00: configured for UDMA/33
|
||||
[ 3.291001] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.291104] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.291128] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.291165] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.291174] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.291193] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.291307] sda: sda1
|
||||
[ 3.291413] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.411182] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.411195] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.411215] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.411225] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.411245] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.411257] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.411320] usbcore: registered new interface driver usb-storage
|
||||
[ 3.411372] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.411510] usbcore: registered new interface driver usbhid
|
||||
[ 3.411519] usbhid: USB HID core driver
|
||||
[ 3.411550] TCP: cubic registered
|
||||
[ 3.411558] NET: Registered protocol family 17
|
||||
[ 3.411890] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.411924] devtmpfs: mounted
|
||||
[ 3.411972] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
[ 0.000147] hw perfevents: no hardware support available
|
||||
[ 1.060066] CPU1: failed to come online
|
||||
[ 2.080127] CPU2: failed to come online
|
||||
[ 3.100188] CPU3: failed to come online
|
||||
[ 3.100191] Brought up 1 CPUs
|
||||
[ 3.100192] SMP: Total of 1 processors activated.
|
||||
[ 3.100247] devtmpfs: initialized
|
||||
[ 3.100685] atomic64_test: passed
|
||||
[ 3.100727] regulator-dummy: no parameters
|
||||
[ 3.101141] NET: Registered protocol family 16
|
||||
[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.101638] Serial: AMBA PL011 UART driver
|
||||
[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.102416] console [ttyAMA0] enabled
|
||||
[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130494] 3V3: 3300 mV
|
||||
[ 3.130534] vgaarb: loaded
|
||||
[ 3.130580] SCSI subsystem initialized
|
||||
[ 3.130617] libata version 3.00 loaded.
|
||||
[ 3.130659] usbcore: registered new interface driver usbfs
|
||||
[ 3.130676] usbcore: registered new interface driver hub
|
||||
[ 3.130707] usbcore: registered new device driver usb
|
||||
[ 3.130732] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.130759] PTP clock support registered
|
||||
[ 3.130873] Switched to clocksource arch_sys_counter
|
||||
[ 3.131846] NET: Registered protocol family 2
|
||||
[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.131975] TCP: reno registered
|
||||
[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.132036] NET: Registered protocol family 1
|
||||
[ 3.132085] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.132095] RPC: Registered udp transport module.
|
||||
[ 3.132103] RPC: Registered tcp transport module.
|
||||
[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.132123] PCI: CLS 0 bytes, default 64
|
||||
[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.133901] fuse init (API version 7.23)
|
||||
[ 3.133978] msgmni has been set to 469
|
||||
[ 3.136097] io scheduler noop registered
|
||||
[ 3.136147] io scheduler cfq registered (default)
|
||||
[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.136562] pci_bus 0000:00: scanning bus
|
||||
[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.136734] pci_bus 0000:00: fixups for bus
|
||||
[ 3.136742] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.136774] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.136782] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.136793] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.136801] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.137572] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.137866] scsi0 : ata_piix
|
||||
[ 3.137956] scsi1 : ata_piix
|
||||
[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.138131] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.290935] ata1.00: configured for UDMA/33
|
||||
[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.291287] sda: sda1
|
||||
[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.411304] usbcore: registered new interface driver usb-storage
|
||||
[ 3.411354] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.411491] usbcore: registered new interface driver usbhid
|
||||
[ 3.411501] usbhid: USB HID core driver
|
||||
[ 3.411531] TCP: cubic registered
|
||||
[ 3.411538] NET: Registered protocol family 17
|
||||
[ 3.411866] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.411900] devtmpfs: mounted
|
||||
[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 3.450398] udevd[607]: starting version 182
|
||||
[ 3.450359] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 3.533417] random: dd urandom read with 19 bits of entropy available
|
||||
[ 3.543431] random: dd urandom read with 19 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
|
|||
Mon Jan 27 08:00:00 UTC 2014
|
||||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
INIT: Entering runlevel: 5
|
||||
Configuring network interfaces... [ 3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
udhcpc (v1.21.1) started
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
|
|
|
|||
|
|
@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
flags_addr=469827632
|
||||
gic_cpu_addr=738205696
|
||||
have_large_asid_64=false
|
||||
have_lpae=false
|
||||
have_lpae=true
|
||||
have_security=false
|
||||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -40,12 +42,18 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -86,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -104,6 +117,7 @@ branchPred=Null
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -122,6 +136,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -168,8 +190,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -192,9 +219,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -208,9 +240,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -246,8 +287,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -305,9 +351,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -321,9 +372,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -334,13 +390,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -359,8 +419,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -368,9 +433,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -415,9 +486,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -431,13 +507,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -456,8 +536,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -465,9 +550,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -481,11 +572,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -501,11 +597,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
port=system.membus.master[5]
|
||||
|
||||
|
|
@ -520,10 +621,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -604,14 +710,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -620,13 +731,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -636,6 +752,7 @@ pio=system.iobus.master[5]
|
|||
type=SubSystem
|
||||
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.dcc.osc_cpu]
|
||||
type=RealViewOsc
|
||||
|
|
@ -706,10 +823,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -789,17 +911,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -825,12 +952,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -838,14 +971,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -931,14 +1069,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -947,13 +1090,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -962,13 +1110,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -976,11 +1129,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -994,11 +1152,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1012,19 +1175,25 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.mcc]
|
||||
type=SubSystem
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.mcc.osc_clcd]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1070,14 +1239,29 @@ position=0
|
|||
site=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.realview.mcc.temp_crtl]
|
||||
type=RealViewTemperatureSensor
|
||||
dcc=0
|
||||
device=0
|
||||
eventq_index=0
|
||||
parent=system.realview.realview_io
|
||||
position=0
|
||||
site=0
|
||||
system=system
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1086,11 +1270,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1100,21 +1289,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=12
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=788529152
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1124,12 +1323,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1138,10 +1342,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1151,12 +1360,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1166,26 +1380,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1194,10 +1418,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1205,10 +1434,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1216,21 +1450,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1244,11 +1488,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1259,11 +1508,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1271,10 +1525,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,58 +1,58 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 51.111167 # Number of seconds simulated
|
||||
sim_ticks 51111167216500 # Number of ticks simulated
|
||||
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 51111167192000 # Number of ticks simulated
|
||||
final_tick 51111167192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 974606 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1145373 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50715816566 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 678940 # Number of bytes of host memory used
|
||||
host_seconds 1007.80 # Real time elapsed on the host
|
||||
sim_insts 982203438 # Number of instructions simulated
|
||||
sim_ops 1154301153 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 942442 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1107573 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 49042304128 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 674172 # Number of bytes of host memory used
|
||||
host_seconds 1042.19 # Real time elapsed on the host
|
||||
sim_insts 982198638 # Number of instructions simulated
|
||||
sim_ops 1154296340 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 5484148 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 74913608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::total 81622588 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5484148 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5484148 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 103278016 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 103298596 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1170515 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 126097 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1170538 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1315747 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 1315773 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1613719 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1616292 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1465671 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 107298 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1465699 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1596929 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1596962 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107298 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107298 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2020655 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2021057 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2020655 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107298 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1466102 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_total::total 3618019 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
||||
|
|
@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I
|
|||
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu
|
|||
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -109,7 +109,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 266586 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency
|
||||
|
|
@ -118,8 +118,8 @@ system.cpu.dtb.walker.walkWaitTime::total 266586 # T
|
|||
system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::2M 24416 10.65% 100.00% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -130,10 +130,10 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190
|
|||
system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 183545125 # DTB read hits
|
||||
system.cpu.dtb.read_misses 195347 # DTB read misses
|
||||
system.cpu.dtb.write_hits 167774776 # DTB write hits
|
||||
system.cpu.dtb.write_misses 71239 # DTB write misses
|
||||
system.cpu.dtb.read_hits 183544097 # DTB read hits
|
||||
system.cpu.dtb.read_misses 195348 # DTB read misses
|
||||
system.cpu.dtb.write_hits 167774773 # DTB write hits
|
||||
system.cpu.dtb.write_misses 71238 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
|
||||
|
|
@ -143,13 +143,13 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 183740472 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 167846015 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 183739445 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 167846011 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 351319901 # DTB hits
|
||||
system.cpu.dtb.hits 351318870 # DTB hits
|
||||
system.cpu.dtb.misses 266586 # DTB misses
|
||||
system.cpu.dtb.accesses 351586487 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.accesses 351585456 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -179,7 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 126834 # Table walker walks requested
|
||||
system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors
|
||||
system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency
|
||||
|
|
@ -198,7 +198,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
|||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 982680284 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 982675484 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 126834 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -215,14 +215,14 @@ system.cpu.itb.domain_faults 0 # Nu
|
|||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 982807118 # ITB inst accesses
|
||||
system.cpu.itb.hits 982680284 # DTB hits
|
||||
system.cpu.itb.inst_accesses 982802318 # ITB inst accesses
|
||||
system.cpu.itb.hits 982675484 # DTB hits
|
||||
system.cpu.itb.misses 126834 # DTB misses
|
||||
system.cpu.itb.accesses 982807118 # DTB accesses
|
||||
system.cpu.itb.accesses 982802318 # DTB accesses
|
||||
system.cpu.numPwrStateTransitions 33550 # Number of power state transitions
|
||||
system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 3012440883.104620 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 59942517995.825706 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
|
||||
|
|
@ -234,41 +234,41 @@ system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88%
|
|||
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 102222351209 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 577471377920 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 102222351160 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 982203438 # Number of instructions committed
|
||||
system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 982198638 # Number of instructions committed
|
||||
system.cpu.committedOps 1154296340 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1057877800 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 56834581 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1057882257 # number of integer instructions
|
||||
system.cpu.num_func_calls 56833909 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 151622723 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1057877800 # number of integer instructions
|
||||
system.cpu.num_fp_insts 881349 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 1560754548 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 840513636 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 351539335 # number of memory refs
|
||||
system.cpu.num_load_insts 183712430 # Number of load instructions
|
||||
system.cpu.num_store_insts 167826905 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 264017562 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 263439787 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 351538306 # number of memory refs
|
||||
system.cpu.num_load_insts 183711405 # Number of load instructions
|
||||
system.cpu.num_store_insts 167826901 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 101067408214.617065 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1154942945.382940 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.988702 # Percentage of idle cycles
|
||||
system.cpu.Branches 219534054 # Number of branches fetched
|
||||
system.cpu.Branches 219532347 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 800829907 69.34% 69.34% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2354386 0.20% 69.54% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction
|
||||
|
|
@ -296,17 +296,17 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 183711405 15.91% 85.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 167826901 14.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1154935820 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 11606642 # number of replacements
|
||||
system.cpu.op_class::total 1154931007 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 11605970 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 339855114 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 11606482 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 29.281492 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
|
|
@ -316,88 +316,88 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 199
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 1417452931 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1417452931 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 171110382 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 171110382 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 159073547 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 159073547 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 424481 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 424481 # number of SoftPFReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303643 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 4303643 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 330945053 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 330520212 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 330520212 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 330944693 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 330944693 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 6002738 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 6002738 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2568126 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2568126 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1586184 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1586184 # number of SoftPFReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 253806 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 253806 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11404487 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 9817636 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9817636 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11403820 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11403820 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 177113120 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 177113120 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 161641673 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 161641673 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010665 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2010665 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557449 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 4557449 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 340337848 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 340337848 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 342348513 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 342348513 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033892 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.033892 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788885 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.788885 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.028847 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.028847 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.033311 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8917390 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 14265253 # number of replacements
|
||||
system.cpu.dcache.writebacks::writebacks 8916642 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8916642 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 14265273 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.total_refs 968524390 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 14265785 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 67.891419 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
|
||||
|
|
@ -406,27 +406,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 184
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 968529210 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 14265770 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 14265770 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 14265770 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 14265770 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 982794980 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 982794980 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 982794980 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 997055970 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 997055970 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 968524390 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 968524390 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 968524390 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 968524390 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 968524390 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 968524390 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 14265790 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 14265790 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 14265790 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 14265790 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 14265790 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 14265790 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 982790180 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 982790180 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 982790180 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 982790180 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 982790180 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 982790180 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses
|
||||
|
|
@ -439,199 +439,200 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 14265253 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1725806 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks.
|
||||
system.cpu.icache.writebacks::writebacks 14265273 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 14265273 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1725823 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65319.568119 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46895862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1788839 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 26.215809 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 447.819467 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.912411 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 21282.908549 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.567632 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.625793 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.901085 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.914096 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.567636 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006833 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006865 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.324751 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.324715 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 320 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 317 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 320 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 317 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004837 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.tag_accesses 425623617 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 425623617 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509088 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 11205 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1689414 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1689414 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182764 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 14182764 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7499286 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 7499286 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::cpu.data 694547 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::total 694547 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 509091 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 765041 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 8916642 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 8916642 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 14263696 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 14263696 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11204 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 11204 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1689386 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1689386 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182781 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 14182781 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498617 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 7498617 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::cpu.data 694560 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::total 694560 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 509088 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14182764 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 9188700 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 24136508 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 509091 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14182781 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 9188003 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 24135825 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 509088 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14182764 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 9188700 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 24136508 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14182781 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 9188003 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 24135825 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 39924 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 39924 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 39927 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 39927 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 827599 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 827599 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83006 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 83006 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344098 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 344098 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 552223 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::total 552223 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 827609 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 827609 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83009 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 83009 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344111 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 344111 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 552212 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::total 552212 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 83006 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1171697 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1267016 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 83009 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1171720 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1267042 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 83006 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1171697 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1267016 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 83009 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1171720 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1267042 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 777357 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 8917390 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 8917390 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 14263676 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 14263676 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51129 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 51129 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 777354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 8916642 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 8916642 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 14263696 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 14263696 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51131 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 51131 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2517013 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2517013 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265770 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 14265770 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7843384 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246770 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515567 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516995 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2516995 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265790 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 14265790 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842728 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7842728 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515564 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 14265770 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 10360397 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 25403524 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515567 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 14265790 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 10359723 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 25402867 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515564 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 14265770 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 10360397 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 25403524 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 14265790 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 10359723 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 25402867 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780848 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780848 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780877 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780877 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328802 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328808 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328808 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043871 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442923 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442923 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043876 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043876 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442913 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.049878 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.049878 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1507080 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.l2cache.writebacks::writebacks 1507088 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1507088 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 52384615 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512337 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1229989 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 23338507 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 8916642 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 14265273 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2689328 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 51131 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 51132 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2516995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2516995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265790 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842728 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883103 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35055544 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548412 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 80245267 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826160532 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233877030 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1957577 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 3069264042 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1957594 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 103278016 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55015054 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.010836 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103531 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54418911 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 596143 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55015054 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.trans_dist::ReadReq 40242 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 40242 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
||||
|
|
@ -674,13 +675,13 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248
|
|||
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.replacements 115459 # number of replacements
|
||||
system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.warmup_cycle 13082113306009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
|
||||
|
|
@ -691,7 +692,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16
|
|||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 1039650 # Number of data accesses
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
|
||||
|
|
@ -739,64 +740,65 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
|
|||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524946 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524962 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 226320 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1613719 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 226329 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 827042 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 827042 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 658880 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 658880 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 827052 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 827052 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448283 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534331 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663523 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6010016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177699616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177868666 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177870842 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 185259450 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 185261626 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3924997 # Request fanout histogram
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 3925032 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3925032 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3924997 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_fanout::total 3925032 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||
|
|
@ -839,28 +841,28 @@ system.realview.ethernet.totalRxOrn 0 # to
|
|||
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@
|
|||
[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131281] NET: Registered protocol family 1
|
||||
[ 3.131310] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.131311] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.131311] RPC: Registered udp transport module.
|
||||
[ 3.131312] RPC: Registered tcp transport module.
|
||||
[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
|
|
@ -87,7 +87,7 @@
|
|||
[ 3.132687] fuse init (API version 7.23)
|
||||
[ 3.132738] msgmni has been set to 469
|
||||
[ 3.133992] io scheduler noop registered
|
||||
[ 3.134024] io scheduler cfq registered (default)
|
||||
[ 3.134025] io scheduler cfq registered (default)
|
||||
[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
|
|
@ -98,24 +98,24 @@
|
|||
[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.134354] pci_bus 0000:00: fixups for bus
|
||||
[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.134362] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.134366] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
|
|
@ -158,9 +158,9 @@
|
|||
[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 3.446951] udevd[607]: starting version 182
|
||||
[ 3.446950] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 3.532266] random: dd urandom read with 19 bits of entropy available
|
||||
[ 3.532262] random: dd urandom read with 19 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -2,9 +2,12 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 13:36:23
|
||||
gem5 executing on e104799-lin, pid 11118
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:49:27
|
||||
gem5 executing on e108600-lin, pid 23294
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 47216814145000 because m5_exit instruction encountered
|
||||
Exiting @ tick 47296281748500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -91,7 +91,7 @@
|
|||
[ 2.143447] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.143448] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.143450] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.143451] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.143452] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.143453] pci_bus 0000:00: scanning bus
|
||||
[ 2.143455] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.143457] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
|
|
@ -100,7 +100,7 @@
|
|||
[ 2.143477] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.143479] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.143481] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.143482] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.143483] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.143484] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.143486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.143503] pci_bus 0000:00: fixups for bus
|
||||
|
|
@ -130,17 +130,17 @@
|
|||
[ 2.144377] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.144381] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.144382] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.290388] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.290389] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.290387] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.290388] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.290395] ata1.00: configured for UDMA/33
|
||||
[ 2.290412] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.290466] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.290469] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.290411] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.290465] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.290468] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.290484] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.290486] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.290493] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.290548] sda: sda1
|
||||
[ 2.290610] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.290485] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.290492] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.290547] sda: sda1
|
||||
[ 2.290609] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.410644] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.410646] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.410652] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
|
|
@ -158,9 +158,9 @@
|
|||
[ 2.411057] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 2.446371] udevd[609]: starting version 182
|
||||
[ 2.446370] udevd[609]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 2.521978] random: dd urandom read with 17 bits of entropy available
|
||||
[ 2.521984] random: dd urandom read with 17 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
|
|||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
INIT: Entering runlevel: 5
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
[ 2.620600] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
[ 2.620646] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
|
|
|
|||
|
|
@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
flags_addr=469827632
|
||||
gic_cpu_addr=738205696
|
||||
have_large_asid_64=false
|
||||
have_lpae=false
|
||||
have_lpae=true
|
||||
have_security=false
|
||||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -40,12 +42,18 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -86,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -104,6 +117,7 @@ branchPred=Null
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -122,6 +136,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -168,8 +190,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -192,9 +219,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -208,9 +240,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -246,8 +287,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -305,9 +351,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -321,9 +372,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -334,13 +390,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -359,8 +419,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -368,9 +433,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -415,9 +486,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -431,13 +507,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -456,8 +536,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -465,9 +550,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -481,11 +572,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -501,11 +597,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
port=system.membus.master[5]
|
||||
|
||||
|
|
@ -520,10 +621,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -604,14 +710,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -620,13 +731,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -636,6 +752,7 @@ pio=system.iobus.master[5]
|
|||
type=SubSystem
|
||||
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.dcc.osc_cpu]
|
||||
type=RealViewOsc
|
||||
|
|
@ -706,10 +823,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -789,17 +911,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -825,12 +952,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -838,14 +971,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -931,14 +1069,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -947,13 +1090,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -962,13 +1110,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -976,11 +1129,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -994,11 +1152,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1012,19 +1175,25 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.mcc]
|
||||
type=SubSystem
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.mcc.osc_clcd]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1070,14 +1239,29 @@ position=0
|
|||
site=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.realview.mcc.temp_crtl]
|
||||
type=RealViewTemperatureSensor
|
||||
dcc=0
|
||||
device=0
|
||||
eventq_index=0
|
||||
parent=system.realview.realview_io
|
||||
position=0
|
||||
site=0
|
||||
system=system
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1086,11 +1270,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1100,21 +1289,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=12
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=788529152
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1124,12 +1323,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1138,10 +1342,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1151,12 +1360,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1166,26 +1380,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1194,10 +1418,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1205,10 +1434,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1216,21 +1450,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1244,11 +1488,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1259,11 +1508,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1271,10 +1525,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 14:02:50
|
||||
gem5 executing on e104799-lin, pid 13724
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:53:59
|
||||
gem5 executing on e108600-lin, pid 23916
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51111152682000 because m5_exit instruction encountered
|
||||
Exiting @ tick 51111167192000 because m5_exit instruction encountered
|
||||
|
|
|
|||
|
|
@ -1,58 +1,58 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 51.111167 # Number of seconds simulated
|
||||
sim_ticks 51111167216500 # Number of ticks simulated
|
||||
final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 51111167192000 # Number of ticks simulated
|
||||
final_tick 51111167192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 967952 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1137552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50369548013 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 676592 # Number of bytes of host memory used
|
||||
host_seconds 1014.72 # Real time elapsed on the host
|
||||
sim_insts 982203438 # Number of instructions simulated
|
||||
sim_ops 1154301153 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 779536 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 916124 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 40565130498 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 670816 # Number of bytes of host memory used
|
||||
host_seconds 1259.98 # Real time elapsed on the host
|
||||
sim_insts 982198638 # Number of instructions simulated
|
||||
sim_ops 1154296340 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 74912136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 5484148 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 74913608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 81620924 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::total 81622588 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5484148 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5484148 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 103278016 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 103298596 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1170515 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 126097 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1170538 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1315747 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 1315773 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1613719 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1616292 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1465671 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 107298 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1465699 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1596929 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1596962 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107298 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107298 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2020655 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2021057 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2020655 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107298 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1466102 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_total::total 3618019 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
||||
|
|
@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I
|
|||
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu
|
|||
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -109,7 +109,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 266586 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency
|
||||
|
|
@ -118,8 +118,8 @@ system.cpu.dtb.walker.walkWaitTime::total 266586 # T
|
|||
system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::2M 24416 10.65% 100.00% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -130,10 +130,10 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190
|
|||
system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 183545125 # DTB read hits
|
||||
system.cpu.dtb.read_misses 195347 # DTB read misses
|
||||
system.cpu.dtb.write_hits 167774776 # DTB write hits
|
||||
system.cpu.dtb.write_misses 71239 # DTB write misses
|
||||
system.cpu.dtb.read_hits 183544097 # DTB read hits
|
||||
system.cpu.dtb.read_misses 195348 # DTB read misses
|
||||
system.cpu.dtb.write_hits 167774773 # DTB write hits
|
||||
system.cpu.dtb.write_misses 71238 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
|
||||
|
|
@ -143,13 +143,13 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 183740472 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 167846015 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 183739445 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 167846011 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 351319901 # DTB hits
|
||||
system.cpu.dtb.hits 351318870 # DTB hits
|
||||
system.cpu.dtb.misses 266586 # DTB misses
|
||||
system.cpu.dtb.accesses 351586487 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.accesses 351585456 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -179,7 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 126834 # Table walker walks requested
|
||||
system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors
|
||||
system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency
|
||||
|
|
@ -198,7 +198,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
|||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 982680284 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 982675484 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 126834 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -215,14 +215,14 @@ system.cpu.itb.domain_faults 0 # Nu
|
|||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 982807118 # ITB inst accesses
|
||||
system.cpu.itb.hits 982680284 # DTB hits
|
||||
system.cpu.itb.inst_accesses 982802318 # ITB inst accesses
|
||||
system.cpu.itb.hits 982675484 # DTB hits
|
||||
system.cpu.itb.misses 126834 # DTB misses
|
||||
system.cpu.itb.accesses 982807118 # DTB accesses
|
||||
system.cpu.itb.accesses 982802318 # DTB accesses
|
||||
system.cpu.numPwrStateTransitions 33550 # Number of power state transitions
|
||||
system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 3012440883.104620 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 59942517995.825706 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state
|
||||
|
|
@ -234,41 +234,41 @@ system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88%
|
|||
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 102222351209 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 577471377920 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 102222351160 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 982203438 # Number of instructions committed
|
||||
system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 982198638 # Number of instructions committed
|
||||
system.cpu.committedOps 1154296340 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1057877800 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 56834581 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1057882257 # number of integer instructions
|
||||
system.cpu.num_func_calls 56833909 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 151622723 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1057877800 # number of integer instructions
|
||||
system.cpu.num_fp_insts 881349 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 1560754548 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 840513636 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 351539335 # number of memory refs
|
||||
system.cpu.num_load_insts 183712430 # Number of load instructions
|
||||
system.cpu.num_store_insts 167826905 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 264017562 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 263439787 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 351538306 # number of memory refs
|
||||
system.cpu.num_load_insts 183711405 # Number of load instructions
|
||||
system.cpu.num_store_insts 167826901 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 101067408214.617065 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1154942945.382940 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.988702 # Percentage of idle cycles
|
||||
system.cpu.Branches 219534054 # Number of branches fetched
|
||||
system.cpu.Branches 219532347 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 800829907 69.34% 69.34% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2354386 0.20% 69.54% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction
|
||||
|
|
@ -296,17 +296,17 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 183711405 15.91% 85.47% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 167826901 14.53% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1154935820 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 11606642 # number of replacements
|
||||
system.cpu.op_class::total 1154931007 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 11605970 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 339855114 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 11606482 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 29.281492 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
|
|
@ -316,88 +316,88 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 199
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 1417452931 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1417452931 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 171110382 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 171110382 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 159073547 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 159073547 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 424481 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 424481 # number of SoftPFReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits
|
||||
system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303643 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 4303643 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 330520588 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 330520588 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 330945053 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 330945053 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 330520212 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 330520212 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 330944693 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 330944693 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 6002738 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 6002738 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2568126 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2568126 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1586184 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1586184 # number of SoftPFReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses
|
||||
system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 253806 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 253806 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9818285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9818285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11404487 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11404487 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 9817636 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9817636 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11403820 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11403820 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 177113120 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 177113120 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 161641673 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 161641673 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010665 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2010665 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557449 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 4557449 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 340338873 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 340338873 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 342349540 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 342349540 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 340337848 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 340337848 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 342348513 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 342348513 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033892 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.033892 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788885 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.788885 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.028849 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.028849 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.033312 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.033312 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.028847 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.028847 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.033311 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8917390 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 14265253 # number of replacements
|
||||
system.cpu.dcache.writebacks::writebacks 8916642 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8916642 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 14265273 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.total_refs 968524390 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 14265785 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 67.891419 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
|
||||
|
|
@ -406,27 +406,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 184
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 968529210 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 14265770 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 14265770 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 14265770 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 14265770 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 982794980 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 982794980 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 982794980 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 997055970 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 997055970 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 968524390 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 968524390 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 968524390 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 968524390 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 968524390 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 968524390 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 14265790 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 14265790 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 14265790 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 14265790 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 14265790 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 14265790 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 982790180 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 982790180 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 982790180 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 982790180 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 982790180 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 982790180 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses
|
||||
|
|
@ -439,199 +439,200 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 14265253 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1725806 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks.
|
||||
system.cpu.icache.writebacks::writebacks 14265273 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 14265273 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1725823 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65319.568119 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46895862 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1788839 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 26.215809 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 447.819467 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.912411 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 21282.908549 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.567632 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.625793 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.901085 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.914096 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.567636 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006833 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006865 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.324751 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.324715 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 320 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 317 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 320 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 317 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004837 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.tag_accesses 425623617 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 425623617 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509088 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 11205 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1689414 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1689414 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182764 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 14182764 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7499286 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 7499286 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::cpu.data 694547 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::total 694547 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 509091 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 765041 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 8916642 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 8916642 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 14263696 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 14263696 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11204 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 11204 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1689386 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1689386 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182781 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 14182781 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498617 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 7498617 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::cpu.data 694560 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::total 694560 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 509088 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14182764 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 9188700 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 24136508 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 509091 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14182781 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 9188003 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 24135825 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 509088 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14182764 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 9188700 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 24136508 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14182781 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 9188003 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 24135825 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 39924 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 39924 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 39927 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 39927 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 827599 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 827599 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83006 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 83006 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344098 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 344098 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 552223 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::total 552223 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 827609 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 827609 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83009 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 83009 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344111 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 344111 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 552212 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::total 552212 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 83006 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1171697 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1267016 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 83009 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1171720 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1267042 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 83006 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1171697 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1267016 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 83009 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1171720 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1267042 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 777357 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 8917390 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 8917390 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 14263676 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 14263676 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51129 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 51129 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 777354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 8916642 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 8916642 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 14263696 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 14263696 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51131 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 51131 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2517013 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2517013 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265770 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 14265770 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7843384 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246770 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515567 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516995 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2516995 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265790 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 14265790 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842728 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 7842728 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515564 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 14265770 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 10360397 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 25403524 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515567 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 14265790 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 10359723 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 25402867 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515564 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 14265770 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 10360397 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 25403524 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 14265790 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 10359723 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 25402867 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780848 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780848 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780877 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780877 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328802 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328808 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328808 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043871 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442923 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442923 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043876 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043876 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442913 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.049878 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.049878 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1507080 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.l2cache.writebacks::writebacks 1507088 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1507088 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 52384615 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512337 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1229989 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 23338507 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 8916642 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 14265273 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2689328 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 51131 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 51132 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2516995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2516995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265790 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842728 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883103 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35055544 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548412 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 80245267 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826160532 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233877030 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1957577 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 3069264042 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1957594 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 103278016 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55015054 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.010836 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103531 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54418911 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 596143 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55015054 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.trans_dist::ReadReq 40242 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 40242 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
||||
|
|
@ -674,13 +675,13 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248
|
|||
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.replacements 115459 # number of replacements
|
||||
system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.warmup_cycle 13082113306009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
|
||||
|
|
@ -691,7 +692,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16
|
|||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 1039650 # Number of data accesses
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
|
||||
|
|
@ -739,64 +740,65 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
|
|||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524946 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524962 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 226320 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1613719 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 226329 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 827042 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 827042 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 658880 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 658880 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 827052 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 827052 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448283 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534331 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663523 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6010016 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177699616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177868666 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177870842 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 185259450 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 185261626 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3924997 # Request fanout histogram
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 3925032 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3925032 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3924997 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_fanout::total 3925032 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||
|
|
@ -839,28 +841,28 @@ system.realview.ethernet.totalRxOrn 0 # to
|
|||
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@
|
|||
[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.131281] NET: Registered protocol family 1
|
||||
[ 3.131310] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.131311] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.131311] RPC: Registered udp transport module.
|
||||
[ 3.131312] RPC: Registered tcp transport module.
|
||||
[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
|
|
@ -87,7 +87,7 @@
|
|||
[ 3.132687] fuse init (API version 7.23)
|
||||
[ 3.132738] msgmni has been set to 469
|
||||
[ 3.133992] io scheduler noop registered
|
||||
[ 3.134024] io scheduler cfq registered (default)
|
||||
[ 3.134025] io scheduler cfq registered (default)
|
||||
[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
|
|
@ -98,24 +98,24 @@
|
|||
[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.134329] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.134336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.134354] pci_bus 0000:00: fixups for bus
|
||||
[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.134361] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.134362] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.134365] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.134366] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.134372] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.134377] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
|
|
@ -158,9 +158,9 @@
|
|||
[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 3.446951] udevd[607]: starting version 182
|
||||
[ 3.446950] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 3.532266] random: dd urandom read with 19 bits of entropy available
|
||||
[ 3.532262] random: dd urandom read with 19 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -3,6 +3,8 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
|
|
|
|||
|
|
@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
|
|||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Mar 15 2016 21:26:42
|
||||
gem5 started Mar 15 2016 21:52:28
|
||||
gem5 executing on phenom, pid 15986
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:41:50
|
||||
gem5 executing on e108600-lin, pid 23131
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 47460623015500 because m5_exit instruction encountered
|
||||
Exiting @ tick 47403574916500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -32,135 +32,135 @@
|
|||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000032] Console: colour dummy device 80x25
|
||||
[ 0.000036] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000037] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000053] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000054] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000245] hw perfevents: no hardware support available
|
||||
[ 0.060065] CPU1: Booted secondary processor
|
||||
[ 1.080104] CPU2: failed to come online
|
||||
[ 2.100199] CPU3: failed to come online
|
||||
[ 2.100203] Brought up 2 CPUs
|
||||
[ 2.100204] SMP: Total of 2 processors activated.
|
||||
[ 2.100286] devtmpfs: initialized
|
||||
[ 2.100949] atomic64_test: passed
|
||||
[ 2.101011] regulator-dummy: no parameters
|
||||
[ 2.101476] NET: Registered protocol family 16
|
||||
[ 2.101658] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.101666] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.103275] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.103279] Serial: AMBA PL011 UART driver
|
||||
[ 2.103525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.103576] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.104152] console [ttyAMA0] enabled
|
||||
[ 2.104323] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.104394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.104465] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.104535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.150406] 3V3: 3300 mV
|
||||
[ 2.150465] vgaarb: loaded
|
||||
[ 2.150535] SCSI subsystem initialized
|
||||
[ 2.150576] libata version 3.00 loaded.
|
||||
[ 2.150646] usbcore: registered new interface driver usbfs
|
||||
[ 2.150667] usbcore: registered new interface driver hub
|
||||
[ 2.150693] usbcore: registered new device driver usb
|
||||
[ 2.150726] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.150736] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.150757] PTP clock support registered
|
||||
[ 2.150931] Switched to clocksource arch_sys_counter
|
||||
[ 2.152285] NET: Registered protocol family 2
|
||||
[ 2.152391] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.152411] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.152431] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.152471] TCP: reno registered
|
||||
[ 2.152479] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.152493] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.152538] NET: Registered protocol family 1
|
||||
[ 2.152603] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.152613] RPC: Registered udp transport module.
|
||||
[ 2.152622] RPC: Registered tcp transport module.
|
||||
[ 2.152630] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.152643] PCI: CLS 0 bytes, default 64
|
||||
[ 2.152855] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.152973] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.155121] fuse init (API version 7.23)
|
||||
[ 2.155231] msgmni has been set to 469
|
||||
[ 2.157249] io scheduler noop registered
|
||||
[ 2.157315] io scheduler cfq registered (default)
|
||||
[ 2.158049] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.158063] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.158075] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.158088] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.158099] pci_bus 0000:00: scanning bus
|
||||
[ 2.158111] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.158125] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.158141] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.158181] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.158194] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.158205] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.158216] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.158227] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.158239] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.158251] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.158291] pci_bus 0000:00: fixups for bus
|
||||
[ 2.158300] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.158312] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.158334] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.158343] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.158355] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.158364] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.158377] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.158390] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.158404] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.158417] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.158429] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.158441] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.158453] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.158465] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.159060] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.159386] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.159397] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.159432] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.159775] scsi0 : ata_piix
|
||||
[ 2.159868] scsi1 : ata_piix
|
||||
[ 2.159904] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.159917] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.160058] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.160070] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.160086] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.160098] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.300957] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.300967] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.300998] ata1.00: configured for UDMA/33
|
||||
[ 2.301069] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.301206] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.301211] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.301241] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.301251] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.301279] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.301443] sda: sda1
|
||||
[ 2.301585] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.421256] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.421269] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.421295] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.421306] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.421330] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.421342] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.421439] usbcore: registered new interface driver usb-storage
|
||||
[ 2.421506] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.421699] usbcore: registered new interface driver usbhid
|
||||
[ 2.421709] usbhid: USB HID core driver
|
||||
[ 2.421746] TCP: cubic registered
|
||||
[ 2.421755] NET: Registered protocol family 17
|
||||
[ 2.422224] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.422264] devtmpfs: mounted
|
||||
[ 2.422355] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
[ 0.000027] Console: colour dummy device 80x25
|
||||
[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000032] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000186] hw perfevents: no hardware support available
|
||||
[ 0.060051] CPU1: Booted secondary processor
|
||||
[ 1.080095] CPU2: failed to come online
|
||||
[ 2.100183] CPU3: failed to come online
|
||||
[ 2.100186] Brought up 2 CPUs
|
||||
[ 2.100188] SMP: Total of 2 processors activated.
|
||||
[ 2.100259] devtmpfs: initialized
|
||||
[ 2.100898] atomic64_test: passed
|
||||
[ 2.100952] regulator-dummy: no parameters
|
||||
[ 2.101389] NET: Registered protocol family 16
|
||||
[ 2.101557] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 2.101563] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 2.102363] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 2.102366] Serial: AMBA PL011 UART driver
|
||||
[ 2.102592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 2.102637] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 2.103214] console [ttyAMA0] enabled
|
||||
[ 2.103383] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 2.103459] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 2.103535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 2.103603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 2.130362] 3V3: 3300 mV
|
||||
[ 2.130420] vgaarb: loaded
|
||||
[ 2.130477] SCSI subsystem initialized
|
||||
[ 2.130513] libata version 3.00 loaded.
|
||||
[ 2.130567] usbcore: registered new interface driver usbfs
|
||||
[ 2.130587] usbcore: registered new interface driver hub
|
||||
[ 2.130614] usbcore: registered new device driver usb
|
||||
[ 2.130645] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 2.130654] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 2.130674] PTP clock support registered
|
||||
[ 2.130822] Switched to clocksource arch_sys_counter
|
||||
[ 2.132478] NET: Registered protocol family 2
|
||||
[ 2.132574] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 2.132642] TCP: reno registered
|
||||
[ 2.132649] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.132663] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 2.132704] NET: Registered protocol family 1
|
||||
[ 2.132763] RPC: Registered named UNIX socket transport module.
|
||||
[ 2.132774] RPC: Registered udp transport module.
|
||||
[ 2.132782] RPC: Registered tcp transport module.
|
||||
[ 2.132791] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 2.132804] PCI: CLS 0 bytes, default 64
|
||||
[ 2.133012] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 2.133128] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 2.135205] fuse init (API version 7.23)
|
||||
[ 2.135350] msgmni has been set to 469
|
||||
[ 2.135656] io scheduler noop registered
|
||||
[ 2.135718] io scheduler cfq registered (default)
|
||||
[ 2.136286] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 2.136300] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 2.136311] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 2.136324] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 2.136335] pci_bus 0000:00: scanning bus
|
||||
[ 2.136346] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 2.136360] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 2.136375] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.136416] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 2.136429] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 2.136440] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 2.136452] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 2.136463] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 2.136474] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 2.136486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 2.136527] pci_bus 0000:00: fixups for bus
|
||||
[ 2.136536] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 2.136548] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 2.136569] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 2.136578] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 2.136589] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 2.136598] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 2.136609] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 2.136623] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 2.136636] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 2.136650] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 2.136662] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 2.136674] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 2.136686] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 2.136698] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 2.137491] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 2.137826] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 2.137837] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 2.137864] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 2.138204] scsi0 : ata_piix
|
||||
[ 2.138329] scsi1 : ata_piix
|
||||
[ 2.138380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 2.138393] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 2.138543] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 2.138556] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 2.138573] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 2.138585] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 2.280852] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 2.280862] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 2.280892] ata1.00: configured for UDMA/33
|
||||
[ 2.280951] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 2.281082] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 2.281116] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 2.281160] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 2.281170] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 2.281192] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 2.281337] sda: sda1
|
||||
[ 2.281470] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 2.401164] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 2.401177] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 2.401211] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 2.401224] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 2.401253] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 2.401268] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 2.401414] usbcore: registered new interface driver usb-storage
|
||||
[ 2.401486] mousedev: PS/2 mouse device common for all mice
|
||||
[ 2.401677] usbcore: registered new interface driver usbhid
|
||||
[ 2.401687] usbhid: USB HID core driver
|
||||
[ 2.401726] TCP: cubic registered
|
||||
[ 2.401734] NET: Registered protocol family 17
|
||||
[ 2.402177] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 2.402215] devtmpfs: mounted
|
||||
[ 2.402270] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 2.462786] udevd[609]: starting version 182
|
||||
[ 2.442337] udevd[608]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 2.544201] random: dd urandom read with 18 bits of entropy available
|
||||
[ 2.533997] random: dd urandom read with 18 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
|
|||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
INIT: Entering runlevel: 5
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
[ 2.681165] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
[ 2.671053] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
|
|
|
|||
|
|
@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
flags_addr=469827632
|
||||
gic_cpu_addr=738205696
|
||||
have_large_asid_64=false
|
||||
have_lpae=false
|
||||
have_lpae=true
|
||||
have_security=false
|
||||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -40,12 +42,18 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -86,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -104,6 +117,7 @@ branchPred=Null
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -121,6 +135,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -139,13 +157,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -164,8 +186,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -188,9 +215,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.dtb]
|
||||
|
|
@ -204,9 +236,14 @@ walker=system.cpu.dtb.walker
|
|||
[system.cpu.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -217,13 +254,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -242,8 +283,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -301,9 +347,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu.itb]
|
||||
|
|
@ -317,9 +368,14 @@ walker=system.cpu.itb.walker
|
|||
[system.cpu.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.cpu.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -330,13 +386,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -355,8 +415,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
|
|
@ -364,9 +429,15 @@ size=4194304
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.cpu.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
@ -411,9 +482,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -427,13 +503,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -452,8 +532,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -461,9 +546,15 @@ size=1024
|
|||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_response_latency=4
|
||||
|
|
@ -477,11 +568,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -526,6 +622,7 @@ burst_length=8
|
|||
channels=1
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
device_bus_width=8
|
||||
device_rowbuffer_size=1024
|
||||
device_size=536870912
|
||||
|
|
@ -537,7 +634,11 @@ max_accesses_per_row=16
|
|||
mem_sched_policy=frfcfs
|
||||
min_writes_per_switch=16
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
page_policy=open_adaptive
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
ranks_per_channel=2
|
||||
read_buffer_size=32
|
||||
|
|
@ -580,10 +681,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -664,14 +770,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -680,13 +791,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -696,6 +812,7 @@ pio=system.iobus.master[5]
|
|||
type=SubSystem
|
||||
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.dcc.osc_cpu]
|
||||
type=RealViewOsc
|
||||
|
|
@ -766,10 +883,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -849,17 +971,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -885,12 +1012,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -898,14 +1031,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -991,14 +1129,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1007,13 +1150,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1022,13 +1170,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1036,11 +1189,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1054,11 +1212,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1072,19 +1235,25 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.mcc]
|
||||
type=SubSystem
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.mcc.osc_clcd]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1130,14 +1299,29 @@ position=0
|
|||
site=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.realview.mcc.temp_crtl]
|
||||
type=RealViewTemperatureSensor
|
||||
dcc=0
|
||||
device=0
|
||||
eventq_index=0
|
||||
parent=system.realview.realview_io
|
||||
position=0
|
||||
site=0
|
||||
system=system
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1146,11 +1330,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1160,21 +1349,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=12
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=788529152
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1184,12 +1383,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1198,10 +1402,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1211,12 +1420,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1226,26 +1440,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1254,10 +1478,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1265,10 +1494,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1276,21 +1510,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1304,11 +1548,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1319,11 +1568,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1331,10 +1585,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
|
|
|
|||
|
|
@ -1,16 +1,18 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 14:13:19
|
||||
gem5 executing on e104799-lin, pid 14780
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 15:07:38
|
||||
gem5 executing on e108600-lin, pid 24412
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
info: Using bootloader at address 0x10
|
||||
info: Using kernel entry physical address at 0x80080000
|
||||
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 51811415265500 because m5_exit instruction encountered
|
||||
Exiting @ tick 51759347706500 because m5_exit instruction encountered
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -32,135 +32,135 @@
|
|||
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
|
||||
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
|
||||
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
|
||||
[ 0.000045] Console: colour dummy device 80x25
|
||||
[ 0.000049] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000051] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000075] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000077] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000352] hw perfevents: no hardware support available
|
||||
[ 0.000044] Console: colour dummy device 80x25
|
||||
[ 0.000048] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
|
||||
[ 0.000050] pid_max: default: 32768 minimum: 301
|
||||
[ 0.000073] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000075] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
|
||||
[ 0.000316] hw perfevents: no hardware support available
|
||||
[ 1.060136] CPU1: failed to come online
|
||||
[ 2.080266] CPU2: failed to come online
|
||||
[ 2.080267] CPU2: failed to come online
|
||||
[ 3.100398] CPU3: failed to come online
|
||||
[ 3.100403] Brought up 1 CPUs
|
||||
[ 3.100405] SMP: Total of 1 processors activated.
|
||||
[ 3.100521] devtmpfs: initialized
|
||||
[ 3.101636] atomic64_test: passed
|
||||
[ 3.101724] regulator-dummy: no parameters
|
||||
[ 3.102567] NET: Registered protocol family 16
|
||||
[ 3.102857] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.102869] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.105189] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.105197] Serial: AMBA PL011 UART driver
|
||||
[ 3.105593] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.105667] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.106251] console [ttyAMA0] enabled
|
||||
[ 3.106398] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.106448] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.106498] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.106544] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130846] 3V3: 3300 mV
|
||||
[ 3.130933] vgaarb: loaded
|
||||
[ 3.131030] SCSI subsystem initialized
|
||||
[ 3.131104] libata version 3.00 loaded.
|
||||
[ 3.131195] usbcore: registered new interface driver usbfs
|
||||
[ 3.131222] usbcore: registered new interface driver hub
|
||||
[ 3.131280] usbcore: registered new device driver usb
|
||||
[ 3.131327] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.131337] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.131361] PTP clock support registered
|
||||
[ 3.131603] Switched to clocksource arch_sys_counter
|
||||
[ 3.133813] NET: Registered protocol family 2
|
||||
[ 3.133980] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.134012] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.134052] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.134106] TCP: reno registered
|
||||
[ 3.134114] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.134134] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.134210] NET: Registered protocol family 1
|
||||
[ 3.134289] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.134300] RPC: Registered udp transport module.
|
||||
[ 3.134309] RPC: Registered tcp transport module.
|
||||
[ 3.134318] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.134332] PCI: CLS 0 bytes, default 64
|
||||
[ 3.134677] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.134913] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.138682] fuse init (API version 7.23)
|
||||
[ 3.138854] msgmni has been set to 469
|
||||
[ 3.143616] io scheduler noop registered
|
||||
[ 3.143713] io scheduler cfq registered (default)
|
||||
[ 3.144776] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.144790] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.144803] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.144817] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.144829] pci_bus 0000:00: scanning bus
|
||||
[ 3.144843] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.144859] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.144876] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.144939] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.144953] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.144966] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.144978] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.144991] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.145004] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.145017] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.145077] pci_bus 0000:00: fixups for bus
|
||||
[ 3.145087] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.145101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.145130] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.145140] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.145154] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.145164] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.145178] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.145193] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.145208] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.145222] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.145236] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.145249] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.145262] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.145276] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.146194] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.146724] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.146736] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.146781] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.147384] scsi0 : ata_piix
|
||||
[ 3.147568] scsi1 : ata_piix
|
||||
[ 3.147622] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.147635] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.147840] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.147853] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.147876] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.147889] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.301640] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.301651] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.301686] ata1.00: configured for UDMA/33
|
||||
[ 3.301774] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.301972] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.302008] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.302066] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.302077] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.302106] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.302309] sda: sda1
|
||||
[ 3.302514] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.421965] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.421980] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.422010] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.422021] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.422052] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.422065] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.422197] usbcore: registered new interface driver usb-storage
|
||||
[ 3.422291] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.422584] usbcore: registered new interface driver usbhid
|
||||
[ 3.422595] usbhid: USB HID core driver
|
||||
[ 3.422651] TCP: cubic registered
|
||||
[ 3.422660] NET: Registered protocol family 17
|
||||
[ 3.423292] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.423338] devtmpfs: mounted
|
||||
[ 3.423462] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
[ 3.100517] devtmpfs: initialized
|
||||
[ 3.101614] atomic64_test: passed
|
||||
[ 3.101697] regulator-dummy: no parameters
|
||||
[ 3.102519] NET: Registered protocol family 16
|
||||
[ 3.102798] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
|
||||
[ 3.102809] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
|
||||
[ 3.104232] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
|
||||
[ 3.104240] Serial: AMBA PL011 UART driver
|
||||
[ 3.104622] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
|
||||
[ 3.104693] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
|
||||
[ 3.105277] console [ttyAMA0] enabled
|
||||
[ 3.105422] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
|
||||
[ 3.105471] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
|
||||
[ 3.105522] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
|
||||
[ 3.105568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
|
||||
[ 3.130937] 3V3: 3300 mV
|
||||
[ 3.131019] vgaarb: loaded
|
||||
[ 3.131116] SCSI subsystem initialized
|
||||
[ 3.131186] libata version 3.00 loaded.
|
||||
[ 3.131272] usbcore: registered new interface driver usbfs
|
||||
[ 3.131299] usbcore: registered new interface driver hub
|
||||
[ 3.131354] usbcore: registered new device driver usb
|
||||
[ 3.131399] pps_core: LinuxPPS API ver. 1 registered
|
||||
[ 3.131409] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
|
||||
[ 3.131433] PTP clock support registered
|
||||
[ 3.131670] Switched to clocksource arch_sys_counter
|
||||
[ 3.133769] NET: Registered protocol family 2
|
||||
[ 3.133932] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
|
||||
[ 3.133964] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
|
||||
[ 3.134004] TCP: Hash tables configured (established 2048 bind 2048)
|
||||
[ 3.134042] TCP: reno registered
|
||||
[ 3.134050] UDP hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.134070] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
|
||||
[ 3.134144] NET: Registered protocol family 1
|
||||
[ 3.134216] RPC: Registered named UNIX socket transport module.
|
||||
[ 3.134227] RPC: Registered udp transport module.
|
||||
[ 3.134236] RPC: Registered tcp transport module.
|
||||
[ 3.134245] RPC: Registered tcp NFSv4.1 backchannel transport module.
|
||||
[ 3.134259] PCI: CLS 0 bytes, default 64
|
||||
[ 3.134575] futex hash table entries: 1024 (order: 4, 65536 bytes)
|
||||
[ 3.134796] HugeTLB registered 2 MB page size, pre-allocated 0 pages
|
||||
[ 3.138336] fuse init (API version 7.23)
|
||||
[ 3.138502] msgmni has been set to 469
|
||||
[ 3.143073] io scheduler noop registered
|
||||
[ 3.143173] io scheduler cfq registered (default)
|
||||
[ 3.144095] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
|
||||
[ 3.144109] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
|
||||
[ 3.144122] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
|
||||
[ 3.144136] pci_bus 0000:00: root bus resource [bus 00-ff]
|
||||
[ 3.144147] pci_bus 0000:00: scanning bus
|
||||
[ 3.144161] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
|
||||
[ 3.144177] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
|
||||
[ 3.144195] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.144258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
|
||||
[ 3.144272] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
|
||||
[ 3.144285] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
|
||||
[ 3.144297] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
|
||||
[ 3.144310] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
|
||||
[ 3.144322] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
|
||||
[ 3.144336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
|
||||
[ 3.144395] pci_bus 0000:00: fixups for bus
|
||||
[ 3.144405] pci_bus 0000:00: bus scan returning with max=00
|
||||
[ 3.144419] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
|
||||
[ 3.144446] pci 0000:00:00.0: fixup irq: got 33
|
||||
[ 3.144456] pci 0000:00:00.0: assigning IRQ 33
|
||||
[ 3.144470] pci 0000:00:01.0: fixup irq: got 34
|
||||
[ 3.144480] pci 0000:00:01.0: assigning IRQ 34
|
||||
[ 3.144494] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
|
||||
[ 3.144509] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
|
||||
[ 3.144524] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
|
||||
[ 3.144538] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
|
||||
[ 3.144552] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
|
||||
[ 3.144565] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
|
||||
[ 3.144578] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
|
||||
[ 3.144591] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
|
||||
[ 3.145478] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
|
||||
[ 3.146000] ata_piix 0000:00:01.0: version 2.13
|
||||
[ 3.146012] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
|
||||
[ 3.146049] ata_piix 0000:00:01.0: enabling bus mastering
|
||||
[ 3.146644] scsi0 : ata_piix
|
||||
[ 3.146827] scsi1 : ata_piix
|
||||
[ 3.146881] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
|
||||
[ 3.146894] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
|
||||
[ 3.147093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
|
||||
[ 3.147106] e1000: Copyright (c) 1999-2006 Intel Corporation.
|
||||
[ 3.147129] e1000 0000:00:00.0: enabling device (0000 -> 0002)
|
||||
[ 3.147142] e1000 0000:00:00.0: enabling bus mastering
|
||||
[ 3.301707] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
|
||||
[ 3.301718] ata1.00: 2096640 sectors, multi 0: LBA
|
||||
[ 3.301753] ata1.00: configured for UDMA/33
|
||||
[ 3.301838] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
|
||||
[ 3.302037] sd 0:0:0:0: Attached scsi generic sg0 type 0
|
||||
[ 3.302073] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
|
||||
[ 3.302130] sd 0:0:0:0: [sda] Write Protect is off
|
||||
[ 3.302141] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
|
||||
[ 3.302170] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
|
||||
[ 3.302373] sda: sda1
|
||||
[ 3.302577] sd 0:0:0:0: [sda] Attached SCSI disk
|
||||
[ 3.422032] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
|
||||
[ 3.422047] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
|
||||
[ 3.422076] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
|
||||
[ 3.422087] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
|
||||
[ 3.422118] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
|
||||
[ 3.422131] igb: Copyright (c) 2007-2014 Intel Corporation.
|
||||
[ 3.422262] usbcore: registered new interface driver usb-storage
|
||||
[ 3.422357] mousedev: PS/2 mouse device common for all mice
|
||||
[ 3.422646] usbcore: registered new interface driver usbhid
|
||||
[ 3.422657] usbhid: USB HID core driver
|
||||
[ 3.422710] TCP: cubic registered
|
||||
[ 3.422720] NET: Registered protocol family 17
|
||||
[ 3.423338] VFS: Mounted root (ext2 filesystem) on device 8:1.
|
||||
[ 3.423384] devtmpfs: mounted
|
||||
[ 3.423472] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
|
||||
INIT: version 2.88 booting
|
||||
Starting udev
|
||||
[ 3.470418] udevd[607]: starting version 182
|
||||
[ 3.470435] udevd[607]: starting version 182
|
||||
Starting Bootlog daemon: bootlogd.
|
||||
[ 3.586551] random: dd urandom read with 21 bits of entropy available
|
||||
[ 3.596617] random: dd urandom read with 22 bits of entropy available
|
||||
Populating dev cache
|
||||
net.ipv4.conf.default.rp_filter = 1
|
||||
net.ipv4.conf.all.rp_filter = 1
|
||||
|
|
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
|
|||
hwclock: can't open '/dev/misc/rtc': No such file or directory
|
||||
INIT: Entering runlevel: 5
|
||||
Configuring network interfaces... udhcpc (v1.21.1) started
|
||||
[ 3.791840] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
[ 3.791906] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
Sending discover...
|
||||
|
|
|
|||
|
|
@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
|
|||
type=LinuxArmSystem
|
||||
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
|
||||
atags_addr=134217728
|
||||
boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
|
||||
boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
|
||||
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
|
||||
cache_line_size=64
|
||||
clk_domain=system.clk_domain
|
||||
dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
default_p_state=UNDEFINED
|
||||
dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
|
||||
early_kernel_symbols=false
|
||||
enable_context_switch_stats_dump=false
|
||||
eventq_index=0
|
||||
exit_on_work_items=false
|
||||
flags_addr=469827632
|
||||
gic_cpu_addr=738205696
|
||||
have_large_asid_64=false
|
||||
have_lpae=false
|
||||
have_lpae=true
|
||||
have_security=false
|
||||
have_virtualization=false
|
||||
highest_el_is_64=false
|
||||
init_param=0
|
||||
kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
|
||||
kernel_addr_check=true
|
||||
load_addr_mask=268435455
|
||||
load_offset=2147483648
|
||||
|
|
@ -40,12 +42,18 @@ mmap_using_noreserve=false
|
|||
multi_proc=true
|
||||
multi_thread=false
|
||||
num_work_ids=16
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
panic_on_oops=true
|
||||
panic_on_panic=true
|
||||
phys_addr_range_64=40
|
||||
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
|
||||
power_model=Null
|
||||
readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
|
||||
reset_addr_64=0
|
||||
symbolfile=
|
||||
thermal_components=
|
||||
thermal_model=Null
|
||||
work_begin_ckpt_count=0
|
||||
work_begin_cpu_id_exit=-1
|
||||
work_begin_exit_count=0
|
||||
|
|
@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
|
|||
[system.bridge]
|
||||
type=Bridge
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
delay=50000
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
|
||||
req_size=16
|
||||
resp_size=16
|
||||
|
|
@ -86,7 +99,7 @@ table_size=65536
|
|||
[system.cf0.image.child]
|
||||
type=RawDiskImage
|
||||
eventq_index=0
|
||||
image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
|
||||
image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
|
||||
read_only=true
|
||||
|
||||
[system.clk_domain]
|
||||
|
|
@ -104,6 +117,7 @@ branchPred=Null
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -122,6 +136,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -143,13 +161,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=4
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -168,8 +190,13 @@ type=LRU
|
|||
assoc=4
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -192,9 +219,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu0.dtb]
|
||||
|
|
@ -208,9 +240,14 @@ walker=system.cpu0.dtb.walker
|
|||
[system.cpu0.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[3]
|
||||
|
||||
|
|
@ -221,13 +258,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=1
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=2
|
||||
is_read_only=true
|
||||
max_miss_count=0
|
||||
mshrs=4
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=2
|
||||
|
|
@ -246,8 +287,13 @@ type=LRU
|
|||
assoc=1
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=32768
|
||||
|
||||
|
|
@ -305,9 +351,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu0.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu0.itb]
|
||||
|
|
@ -321,9 +372,14 @@ walker=system.cpu0.itb.walker
|
|||
[system.cpu0.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
port=system.toL2Bus.slave[2]
|
||||
|
||||
|
|
@ -338,6 +394,7 @@ branchPred=Null
|
|||
checker=Null
|
||||
clk_domain=system.cpu_clk_domain
|
||||
cpu_id=0
|
||||
default_p_state=UNDEFINED
|
||||
do_checkpoint_insts=true
|
||||
do_quiesce=true
|
||||
do_statistics_insts=true
|
||||
|
|
@ -356,6 +413,10 @@ max_insts_any_thread=0
|
|||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
profile=0
|
||||
progress_interval=0
|
||||
simpoint_start_insts=
|
||||
|
|
@ -387,9 +448,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
|
|||
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.dtb]
|
||||
|
|
@ -403,9 +469,14 @@ walker=system.cpu1.dtb.walker
|
|||
[system.cpu1.dtb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.isa]
|
||||
|
|
@ -458,9 +529,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker
|
|||
[system.cpu1.istage2_mmu.stage2_tlb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=true
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.itb]
|
||||
|
|
@ -474,9 +550,14 @@ walker=system.cpu1.itb.walker
|
|||
[system.cpu1.itb.walker]
|
||||
type=ArmTableWalker
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
is_stage2=false
|
||||
num_squash_per_cycle=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sys=system
|
||||
|
||||
[system.cpu1.tracer]
|
||||
|
|
@ -507,9 +588,14 @@ sys=system
|
|||
[system.iobus]
|
||||
type=NoncoherentXBar
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=1
|
||||
frontend_latency=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
use_default_range=false
|
||||
width=16
|
||||
|
|
@ -523,13 +609,17 @@ addr_ranges=2147483648:2415919103
|
|||
assoc=8
|
||||
clk_domain=system.clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=false
|
||||
hit_latency=50
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=50
|
||||
|
|
@ -548,8 +638,13 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=50
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=1024
|
||||
|
||||
|
|
@ -560,13 +655,17 @@ addr_ranges=0:18446744073709551615
|
|||
assoc=8
|
||||
clk_domain=system.cpu_clk_domain
|
||||
clusivity=mostly_incl
|
||||
default_p_state=UNDEFINED
|
||||
demand_mshr_reserve=1
|
||||
eventq_index=0
|
||||
forward_snoops=true
|
||||
hit_latency=20
|
||||
is_read_only=false
|
||||
max_miss_count=0
|
||||
mshrs=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
prefetch_on_access=false
|
||||
prefetcher=Null
|
||||
response_latency=20
|
||||
|
|
@ -585,20 +684,31 @@ type=LRU
|
|||
assoc=8
|
||||
block_size=64
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
hit_latency=20
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
sequential_access=false
|
||||
size=4194304
|
||||
|
||||
[system.membus]
|
||||
type=CoherentXBar
|
||||
children=badaddr_responder
|
||||
children=badaddr_responder snoop_filter
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=4
|
||||
frontend_latency=3
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=true
|
||||
power_model=Null
|
||||
response_latency=2
|
||||
snoop_filter=Null
|
||||
snoop_filter=system.membus.snoop_filter
|
||||
snoop_response_latency=4
|
||||
system=system
|
||||
use_default_range=false
|
||||
|
|
@ -610,11 +720,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io
|
|||
[system.membus.badaddr_responder]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=0
|
||||
pio_latency=100000
|
||||
pio_size=8
|
||||
power_model=Null
|
||||
ret_bad_addr=true
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -625,16 +740,28 @@ update_data=false
|
|||
warn_access=warn
|
||||
pio=system.membus.default
|
||||
|
||||
[system.membus.snoop_filter]
|
||||
type=SnoopFilter
|
||||
eventq_index=0
|
||||
lookup_latency=1
|
||||
max_capacity=8388608
|
||||
system=system
|
||||
|
||||
[system.physmem]
|
||||
type=SimpleMemory
|
||||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=2147483648:2415919103
|
||||
port=system.membus.master[5]
|
||||
|
||||
|
|
@ -649,10 +776,15 @@ system=system
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470024192
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[18]
|
||||
|
||||
|
|
@ -733,14 +865,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=2
|
||||
default_p_state=UNDEFINED
|
||||
disks=
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=2
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=2
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[2]
|
||||
pio=system.iobus.master[9]
|
||||
|
|
@ -749,13 +886,18 @@ pio=system.iobus.master[9]
|
|||
type=Pl111
|
||||
amba_id=1315089
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=46
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471793664
|
||||
pio_latency=10000
|
||||
pixel_clock=41667
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
dma=system.iobus.slave[1]
|
||||
|
|
@ -765,6 +907,7 @@ pio=system.iobus.master[5]
|
|||
type=SubSystem
|
||||
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.dcc.osc_cpu]
|
||||
type=RealViewOsc
|
||||
|
|
@ -835,10 +978,15 @@ voltage_domain=system.voltage_domain
|
|||
[system.realview.energy_ctrl]
|
||||
type=EnergyCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
dvfs_handler=system.dvfs_handler
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470286336
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[22]
|
||||
|
||||
|
|
@ -918,17 +1066,22 @@ SubsystemVendorID=32902
|
|||
VendorID=32902
|
||||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fetch_comp_delay=10000
|
||||
fetch_delay=10000
|
||||
hardware_address=00:90:00:00:00:01
|
||||
host=system.realview.pci_host
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=0
|
||||
pci_func=0
|
||||
phy_epid=896
|
||||
phy_pid=680
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
rx_desc_cache_size=64
|
||||
rx_fifo_size=393216
|
||||
rx_write_delay=0
|
||||
|
|
@ -954,12 +1107,18 @@ type=Pl390
|
|||
clk_domain=system.clk_domain
|
||||
cpu_addr=738205696
|
||||
cpu_pio_delay=10000
|
||||
default_p_state=UNDEFINED
|
||||
dist_addr=738201600
|
||||
dist_pio_delay=10000
|
||||
eventq_index=0
|
||||
gem5_extensions=true
|
||||
int_latency=10000
|
||||
it_lines=128
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[2]
|
||||
|
||||
|
|
@ -967,14 +1126,19 @@ pio=system.membus.master[2]
|
|||
type=HDLcd
|
||||
amba_id=1314816
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
enable_capture=true
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num=117
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=721420288
|
||||
pio_latency=10000
|
||||
pixel_buffer_size=2048
|
||||
pixel_chunk=32
|
||||
power_model=Null
|
||||
pxl_clk=system.realview.dcc.osc_pxl
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
|
|
@ -1060,14 +1224,19 @@ VendorID=32902
|
|||
clk_domain=system.clk_domain
|
||||
config_latency=20000
|
||||
ctrl_offset=0
|
||||
default_p_state=UNDEFINED
|
||||
disks=system.cf0
|
||||
eventq_index=0
|
||||
host=system.realview.pci_host
|
||||
io_shift=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_bus=0
|
||||
pci_dev=1
|
||||
pci_func=0
|
||||
pio_latency=30000
|
||||
power_model=Null
|
||||
system=system
|
||||
dma=system.iobus.slave[3]
|
||||
pio=system.iobus.master[23]
|
||||
|
|
@ -1076,13 +1245,18 @@ pio=system.iobus.master[23]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=44
|
||||
is_mouse=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470155264
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[7]
|
||||
|
|
@ -1091,13 +1265,18 @@ pio=system.iobus.master[7]
|
|||
type=Pl050
|
||||
amba_id=1314896
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=1000000
|
||||
int_num=45
|
||||
is_mouse=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470220800
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
vnc=system.vncserver
|
||||
pio=system.iobus.master[8]
|
||||
|
|
@ -1105,11 +1284,16 @@ pio=system.iobus.master[8]
|
|||
[system.realview.l2x0_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=739246080
|
||||
pio_latency=100000
|
||||
pio_size=4095
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1123,11 +1307,16 @@ pio=system.iobus.master[12]
|
|||
[system.realview.lan_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=436207616
|
||||
pio_latency=100000
|
||||
pio_size=65535
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1141,19 +1330,25 @@ pio=system.iobus.master[19]
|
|||
[system.realview.local_cpu_timer]
|
||||
type=CpuLocalTimer
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num_timer=29
|
||||
int_num_watchdog=30
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=738721792
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.membus.master[4]
|
||||
|
||||
[system.realview.mcc]
|
||||
type=SubSystem
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
|
||||
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
|
||||
eventq_index=0
|
||||
thermal_domain=Null
|
||||
|
||||
[system.realview.mcc.osc_clcd]
|
||||
type=RealViewOsc
|
||||
|
|
@ -1199,14 +1394,29 @@ position=0
|
|||
site=0
|
||||
voltage_domain=system.voltage_domain
|
||||
|
||||
[system.realview.mcc.temp_crtl]
|
||||
type=RealViewTemperatureSensor
|
||||
dcc=0
|
||||
device=0
|
||||
eventq_index=0
|
||||
parent=system.realview.realview_io
|
||||
position=0
|
||||
site=0
|
||||
system=system
|
||||
|
||||
[system.realview.mmc_fake]
|
||||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470089728
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[21]
|
||||
|
||||
|
|
@ -1215,11 +1425,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=true
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=0:67108863
|
||||
port=system.membus.master[1]
|
||||
|
||||
|
|
@ -1229,21 +1444,31 @@ clk_domain=system.clk_domain
|
|||
conf_base=805306368
|
||||
conf_device_bits=12
|
||||
conf_size=268435456
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pci_dma_base=0
|
||||
pci_mem_base=0
|
||||
pci_pio_base=788529152
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[2]
|
||||
|
||||
[system.realview.realview_io]
|
||||
type=RealViewCtrl
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
idreg=35979264
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469827584
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
proc_id0=335544320
|
||||
proc_id1=335544320
|
||||
system=system
|
||||
|
|
@ -1253,12 +1478,17 @@ pio=system.iobus.master[1]
|
|||
type=PL031
|
||||
amba_id=3412017
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=36
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=471269376
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
time=Thu Jan 1 00:00:00 2009
|
||||
pio=system.iobus.master[10]
|
||||
|
|
@ -1267,10 +1497,15 @@ pio=system.iobus.master[10]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=true
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=469893120
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[16]
|
||||
|
||||
|
|
@ -1280,12 +1515,17 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=34
|
||||
int_num1=34
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470876160
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[3]
|
||||
|
||||
|
|
@ -1295,26 +1535,36 @@ amba_id=1316868
|
|||
clk_domain=system.clk_domain
|
||||
clock0=1000000
|
||||
clock1=1000000
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_num0=35
|
||||
int_num1=35
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470941696
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[4]
|
||||
|
||||
[system.realview.uart]
|
||||
type=Pl011
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
end_on_eot=false
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
int_delay=100000
|
||||
int_num=37
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470351872
|
||||
pio_latency=100000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
system=system
|
||||
terminal=system.terminal
|
||||
pio=system.iobus.master[0]
|
||||
|
|
@ -1323,10 +1573,15 @@ pio=system.iobus.master[0]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470417408
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[13]
|
||||
|
||||
|
|
@ -1334,10 +1589,15 @@ pio=system.iobus.master[13]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470482944
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[14]
|
||||
|
||||
|
|
@ -1345,21 +1605,31 @@ pio=system.iobus.master[14]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470548480
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[15]
|
||||
|
||||
[system.realview.usb_fake]
|
||||
type=IsaFake
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
fake_mem=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=452984832
|
||||
pio_latency=100000
|
||||
pio_size=131071
|
||||
power_model=Null
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
|
|
@ -1373,11 +1643,16 @@ pio=system.iobus.master[20]
|
|||
[system.realview.vgic]
|
||||
type=VGic
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
gic=system.realview.gic
|
||||
hv_addr=738213888
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_delay=10000
|
||||
platform=system.realview
|
||||
power_model=Null
|
||||
ppint=25
|
||||
system=system
|
||||
vcpu_addr=738222080
|
||||
|
|
@ -1388,11 +1663,16 @@ type=SimpleMemory
|
|||
bandwidth=73.000000
|
||||
clk_domain=system.clk_domain
|
||||
conf_table_reported=false
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
in_addr_map=true
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
power_model=Null
|
||||
range=402653184:436207615
|
||||
port=system.iobus.master[11]
|
||||
|
||||
|
|
@ -1400,10 +1680,15 @@ port=system.iobus.master[11]
|
|||
type=AmbaFake
|
||||
amba_id=0
|
||||
clk_domain=system.clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
ignore_access=false
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
pio_addr=470745088
|
||||
pio_latency=100000
|
||||
power_model=Null
|
||||
system=system
|
||||
pio=system.iobus.master[17]
|
||||
|
||||
|
|
@ -1419,9 +1704,15 @@ port=3456
|
|||
type=CoherentXBar
|
||||
children=snoop_filter
|
||||
clk_domain=system.cpu_clk_domain
|
||||
default_p_state=UNDEFINED
|
||||
eventq_index=0
|
||||
forward_latency=0
|
||||
frontend_latency=1
|
||||
p_state_clk_gate_bins=20
|
||||
p_state_clk_gate_max=1000000000000
|
||||
p_state_clk_gate_min=1000
|
||||
point_of_coherency=false
|
||||
power_model=Null
|
||||
response_latency=1
|
||||
snoop_filter=system.toL2Bus.snoop_filter
|
||||
snoop_response_latency=1
|
||||
|
|
|
|||
|
|
@ -2,8 +2,11 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
|
|||
warn: Sockets disabled, not accepting vnc client connections
|
||||
warn: Sockets disabled, not accepting terminal connections
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
|
||||
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
|
||||
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
|
||||
warn: ClockedObject: Already in the requested power state, request ignored
|
||||
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
|
||||
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
|
||||
|
|
@ -592,15 +595,3 @@ warn: User mode does not have SPSR
|
|||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
warn: User mode does not have SPSR
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic/simout
|
||||
Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic/simerr
|
||||
gem5 Simulator System. http://gem5.org
|
||||
gem5 is copyrighted software; use the --copyright option for details.
|
||||
|
||||
gem5 compiled Dec 4 2015 11:13:17
|
||||
gem5 started Dec 4 2015 12:10:26
|
||||
gem5 executing on e104799-lin, pid 2423
|
||||
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
|
||||
gem5 compiled Jul 21 2016 14:37:41
|
||||
gem5 started Jul 21 2016 14:38:22
|
||||
gem5 executing on e108600-lin, pid 23081
|
||||
command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
|
||||
|
||||
Selected 64-bit ARM architecture, updating default disk image...
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
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