arm, config: Add an example ARM big.LITTLE(tm) configuration script
An ARM big.LITTLE system consists of two cpu clusters: the big CPUs are typically complex out-of-order cores and the little CPUs are simpler in-order ones. The fs_bigLITTLE.py script can run a full system simulation with various number of big and little cores and cache hierarchy. The commit also includes two example device tree files for booting Linux on the bigLITTLE system. Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Gabor Dozsa
parent
752f1c1fe9
commit
a288c94387
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# Copyright (c) 2016 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
|
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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||||
# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
|
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# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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# Gabor Dozsa
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# System components used by the bigLITTLE.py configuration script
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import m5
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from m5.objects import *
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m5.util.addToPath('../../common')
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from Caches import *
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class L1I(L1_ICache):
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hit_latency = 1
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response_latency = 1
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mshrs = 4
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tgts_per_mshr = 8
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size = '48kB'
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assoc = 3
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class L1D(L1_DCache):
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hit_latency = 2
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response_latency = 1
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mshrs = 16
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tgts_per_mshr = 16
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size = '32kB'
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assoc = 2
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write_buffers = 16
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class WalkCache(PageTableWalkerCache):
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hit_latency = 4
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response_latency = 4
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mshrs = 6
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tgts_per_mshr = 8
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size = '1kB'
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assoc = 8
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write_buffers = 16
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class L2(L2Cache):
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hit_latency = 12
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response_latency = 5
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mshrs = 32
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tgts_per_mshr = 8
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size = '1MB'
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assoc = 16
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write_buffers = 8
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clusivity='mostly_excl'
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class L3(Cache):
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size = '16MB'
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assoc = 16
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hit_latency = 20
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response_latency = 20
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mshrs = 20
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tgts_per_mshr = 12
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clusivity='mostly_excl'
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class MemBus(SystemXBar):
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badaddr_responder = BadAddr(warn_access="warn")
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default = Self.badaddr_responder.pio
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class SimpleSystem(LinuxArmSystem):
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cache_line_size = 64
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voltage_domain = VoltageDomain(voltage="1.0V")
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clk_domain = SrcClockDomain(clock="1GHz",
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voltage_domain=Parent.voltage_domain)
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realview = VExpress_GEM5_V1()
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gic_cpu_addr = realview.gic.cpu_addr
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flags_addr = realview.realview_io.pio_addr + 0x30
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membus = MemBus()
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intrctrl = IntrControl()
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terminal = Terminal()
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vncserver = VncServer()
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iobus = IOXBar()
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# CPUs->PIO
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iobridge = Bridge(delay='50ns')
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# Device DMA -> MEM
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dmabridge = Bridge(delay='50ns', ranges=realview._mem_regions)
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_pci_devices = 0
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_clusters = []
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_cpus = []
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def attach_pci(self, dev):
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dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
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self._pci_devices += 1
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self.realview.attachPciDevice(dev, self.iobus)
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def connect(self):
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self.iobridge.master = self.iobus.slave
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self.iobridge.slave = self.membus.master
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self.dmabridge.master = self.membus.slave
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self.dmabridge.slave = self.iobus.master
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.realview.attachOnChipIO(self.membus, self.iobridge)
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self.realview.attachIO(self.iobus)
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self.system_port = self.membus.slave
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@ -0,0 +1,308 @@
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# Copyright (c) 2016 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
|
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
|
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# modification, are permitted provided that the following conditions are
|
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# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
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# redistributions in binary form must reproduce the above copyright
|
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# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Gabor Dozsa
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# Andreas Sandberg
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# This is an example configuration script for full system simulation of
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# a generic ARM bigLITTLE system.
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import argparse
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import os
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import sys
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import m5
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from m5.objects import *
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m5.util.addToPath("../../common")
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import SysPaths
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import CpuConfig
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import devices
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default_dtb = 'armv8_gem5_v1_big_little_2_2.dtb'
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default_kernel = 'vmlinux4.3.aarch64'
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default_disk = 'aarch64-ubuntu-trusty-headless.img'
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default_rcs = 'bootscript.rcS'
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default_mem_size= "2GB"
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def createSystem(kernel, mem_mode, bootscript, disks=[]):
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sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel),
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readfile=bootscript,
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mem_mode=mem_mode,
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machine_type="DTOnly")
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mem_region = sys.realview._mem_regions[0]
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sys.mem_ctrls = SimpleMemory(
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range=AddrRange(start=mem_region[0], size=default_mem_size))
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sys.mem_ctrls.port = sys.membus.master
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sys.connect()
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# Attach disk images
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if disks:
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def cow_disk(image_file):
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image = CowDiskImage()
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image.child.image_file = SysPaths.disk(image_file)
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return image
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sys.disk_images = [ cow_disk(f) for f in disks ]
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sys.pci_vio_block = [ PciVirtIO(vio=VirtIOBlock(image=img))
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for img in sys.disk_images ]
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for dev in sys.pci_vio_block:
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sys.attach_pci(dev)
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sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary)
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return sys
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class CpuCluster(SubSystem):
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def addCPUs(self, cpu_config, num_cpus, cpu_clock, cpu_voltage="1.0V"):
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try:
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self._cluster_id
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m5.util.panic("CpuCluster.addCPUs() must be called exactly once")
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except AttributeError:
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pass
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assert num_cpus > 0
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system = self._parent
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self._cluster_id = len(system._clusters)
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system._clusters.append(self)
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self._config = cpu_config
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self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
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self.clk_domain = SrcClockDomain(clock=cpu_clock,
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voltage_domain=self.voltage_domain)
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cpu_class = cpu_config['cpu']
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self.cpus = [ cpu_class(cpu_id=len(system._cpus) + idx,
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clk_domain=self.clk_domain)
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for idx in range(num_cpus) ]
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for cpu in self.cpus:
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.socket_id = self._cluster_id
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system._cpus.append(cpu)
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def createCache(self, key):
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try:
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return self._config[key]()
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except KeyError:
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return None
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def addL1(self):
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self._cluster_id
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for cpu in self.cpus:
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l1i = self.createCache('l1i')
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l1d = self.createCache('l1d')
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iwc = self.createCache('wcache')
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dwc = self.createCache('wcache')
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cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
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def addL2(self, clk_domain):
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self._cluster_id
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self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
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#self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain,
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#snoop_filter=NULL)
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self.l2 = self._config['l2']()
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for cpu in self.cpus:
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cpu.connectAllPorts(self.toL2Bus)
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self.toL2Bus.master = self.l2.cpu_side
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def connectMemSide(self, bus):
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self._cluster_id
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bus.slave
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try:
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self.l2.mem_side = bus.slave
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except AttributeError:
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for cpu in self.cpus:
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cpu.connectAllPorts(bus)
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def addCaches(system, last_cache_level):
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cluster_mem_bus = system.membus
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assert last_cache_level >= 1 and last_cache_level <= 3
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for cluster in system._clusters:
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cluster.addL1()
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if last_cache_level > 1:
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for cluster in system._clusters:
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cluster.addL2(cluster.clk_domain)
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if last_cache_level > 2:
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max_clock_cluster = max(system._clusters,
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key=lambda c: c.clk_domain.clock[0])
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system.l3 = devices.L3(clk_domain=max_clock_cluster.clk_domain)
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system.toL3Bus = L2XBar(width=64)
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system.toL3Bus.master = system.l3.cpu_side
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system.l3.mem_side = system.membus.slave
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cluster_mem_bus = system.toL3Bus
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return cluster_mem_bus
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def main():
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parser = argparse.ArgumentParser(
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description="Generic ARM big.LITTLE configuration")
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parser.add_argument("--restore-from", type=str, default=None,
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help="Restore from checkpoint")
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parser.add_argument("--dtb", type=str, default=default_dtb,
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help="DTB file to load")
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parser.add_argument("--kernel", type=str, default=default_kernel,
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help="Linux kernel")
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parser.add_argument("--disk", action="append", type=str, default=[],
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help="Disks to instantiate")
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parser.add_argument("--bootscript", type=str, default=default_rcs,
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help="Linux bootscript")
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parser.add_argument("--atomic", action="store_true", default=False,
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help="Use atomic CPUs")
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parser.add_argument("--kernel-init", type=str, default="/sbin/init",
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help="Override init")
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parser.add_argument("--big-cpus", type=int, default=1,
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help="Number of big CPUs to instantiate")
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parser.add_argument("--little-cpus", type=int, default=1,
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help="Number of little CPUs to instantiate")
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parser.add_argument("--caches", action="store_true", default=False,
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help="Instantiate caches")
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parser.add_argument("--last-cache-level", type=int, default=2,
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help="Last level of caches (e.g. 3 for L3)")
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parser.add_argument("--big-cpu-clock", type=str, default="2GHz",
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help="Big CPU clock frequency")
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parser.add_argument("--little-cpu-clock", type=str, default="1GHz",
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help="Little CPU clock frequency")
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m5.ticks.fixGlobalFrequency()
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options = parser.parse_args()
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if options.atomic:
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cpu_config = { 'cpu' : AtomicSimpleCPU }
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big_cpu_config, little_cpu_config = cpu_config, cpu_config
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else:
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big_cpu_config = { 'cpu' : CpuConfig.get("arm_detailed"),
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'l1i' : devices.L1I,
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'l1d' : devices.L1D,
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'wcache' : devices.WalkCache,
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'l2' : devices.L2 }
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little_cpu_config = { 'cpu' : MinorCPU,
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'l1i' : devices.L1I,
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'l1d' : devices.L1D,
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'wcache' : devices.WalkCache,
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'l2' : devices.L2 }
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big_cpu_class = big_cpu_config['cpu']
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little_cpu_class = little_cpu_config['cpu']
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kernel_cmd = [
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"earlyprintk=pl011,0x1c090000",
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"console=ttyAMA0",
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"lpj=19988480",
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"norandmaps",
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"loglevel=8",
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"mem=%s" % default_mem_size,
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"root=/dev/vda1",
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"rw",
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"init=%s" % options.kernel_init,
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"vmalloc=768MB",
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]
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root = Root(full_system=True)
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assert big_cpu_class.memory_mode() == little_cpu_class.memory_mode()
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disks = default_disk if len(options.disk) == 0 else options.disk
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system = createSystem(options.kernel, big_cpu_class.memory_mode(),
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options.bootscript, disks=disks)
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root.system = system
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system.boot_osflags = " ".join(kernel_cmd)
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# big cluster
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if options.big_cpus > 0:
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system.bigCluster = CpuCluster()
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system.bigCluster.addCPUs(big_cpu_config, options.big_cpus,
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options.big_cpu_clock)
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# LITTLE cluster
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if options.little_cpus > 0:
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system.littleCluster = CpuCluster()
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system.littleCluster.addCPUs(little_cpu_config, options.little_cpus,
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options.little_cpu_clock)
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# add caches
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if options.caches:
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cluster_mem_bus = addCaches(system, options.last_cache_level)
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else:
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if big_cpu_class.require_caches():
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m5.util.panic("CPU model %s requires caches" % str(big_cpu_class))
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if little_cpu_class.require_caches():
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m5.util.panic("CPU model %s requires caches" %
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str(little_cpu_class))
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cluster_mem_bus = system.membus
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# connect each cluster to the memory hierarchy
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for cluster in system._clusters:
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cluster.connectMemSide(cluster_mem_bus)
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# Linux device tree
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system.dtb_filename = SysPaths.binary(options.dtb)
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# Get and load from the chkpt or simpoint checkpoint
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if options.restore_from is not None:
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m5.instantiate(options.restore_from)
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else:
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m5.instantiate()
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# start simulation (and drop checkpoints when requested)
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while True:
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event = m5.simulate()
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exit_msg = event.getCause()
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if exit_msg == "checkpoint":
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print "Dropping checkpoint at tick %d" % m5.curTick()
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cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick())
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m5.checkpoint(os.path.join(cpt_dir))
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print "Checkpoint done."
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else:
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print exit_msg, " @ ", m5.curTick()
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break
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sys.exit(event.getCode())
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if __name__ == "__m5_main__":
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main()
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@ -1,4 +1,4 @@
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# Copyright (c) 2015 ARM Limited
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||||
# Copyright (c) 2015-2016 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -37,7 +37,9 @@ TARGETS=\
|
|||
armv7_gem5_v1_16cpu.dtb \
|
||||
armv8_gem5_v1_1cpu.dtb armv8_gem5_v1_2cpu.dtb \
|
||||
armv8_gem5_v1_4cpu.dtb armv8_gem5_v1_8cpu.dtb \
|
||||
armv8_gem5_v1_16cpu.dtb
|
||||
armv8_gem5_v1_16cpu.dtb \
|
||||
armv8_gem5_v1_big_little_2_2.dtb \
|
||||
armv8_gem5_v1_big_little_2_4.dtb
|
||||
|
||||
GEN_DTS=mkdir -p .gen; \
|
||||
$(CPP) -x assembler-with-cpp \
|
||||
|
|
@ -54,6 +56,10 @@ all: $(TARGETS)
|
|||
.gen/armv8_gem5_v1_%cpu.dts: armv8.dts platforms/vexpress_gem5_v1.dtsi
|
||||
$(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
|
||||
|
||||
.gen/armv8_gem5_v1_big_little%.dts: armv8_big_little.dts \
|
||||
platforms/vexpress_gem5_v1.dtsi
|
||||
$(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
|
||||
|
||||
%.dtb: .gen/%.dts
|
||||
$(DTC) -I dts -O dtb -o $@ $<
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016 ARM Limited
|
||||
* All rights reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Andreas Sandberg
|
||||
* Gabor Dozsa
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x80000000 0x00010000;
|
||||
|
||||
#include CONF_PLATFORM
|
||||
|
||||
/* Assign a unique ID for pre-defined configurations. The selected
|
||||
* configuration is picked up from CONF_CPUS
|
||||
*/
|
||||
// 2 big and 2 little cpus
|
||||
#define _2_2 1
|
||||
// 2 big and 4 little cpus
|
||||
#define _2_4 2
|
||||
|
||||
#define CPU(n,id) \
|
||||
CPU ## n: cpu@ ## id { \
|
||||
device_type = "cpu"; \
|
||||
compatible = "gem5,armv8", "arm,armv8"; \
|
||||
reg = < ## id >; \
|
||||
enable-method = "spin-table"; \
|
||||
cpu-release-addr = <0 0x8000fff8>; \
|
||||
};
|
||||
|
||||
|
||||
/ {
|
||||
model = "V2P-AARCH64";
|
||||
compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x80000000 0x4 0x00000000>;
|
||||
};
|
||||
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
#if CONF_CPUS == _2_2
|
||||
CPU(0,0x0)
|
||||
CPU(1,0x1)
|
||||
CPU(2,0x102)
|
||||
CPU(3,0x103)
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 { cpu = <&CPU0>; };
|
||||
core1 { cpu = <&CPU1>; };
|
||||
};
|
||||
cluster1 {
|
||||
core0 { cpu = <&CPU2>; };
|
||||
core1 { cpu = <&CPU3>; };
|
||||
};
|
||||
};
|
||||
#elif CONF_CPUS == _2_4
|
||||
CPU(0,0x0)
|
||||
CPU(1,0x1)
|
||||
CPU(2,0x102)
|
||||
CPU(3,0x103)
|
||||
CPU(4,0x104)
|
||||
CPU(5,0x105)
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 { cpu = <&CPU0>; };
|
||||
core1 { cpu = <&CPU1>; };
|
||||
};
|
||||
cluster1 {
|
||||
core0 { cpu = <&CPU2>; };
|
||||
core1 { cpu = <&CPU3>; };
|
||||
core2 { cpu = <&CPU4>; };
|
||||
core3 { cpu = <&CPU5>; };
|
||||
};
|
||||
};
|
||||
#else
|
||||
#error Missing configuration section
|
||||
#endif
|
||||
};
|
||||
|
||||
virt-encoder {
|
||||
compatible = "drm,virtual-encoder";
|
||||
port {
|
||||
hdlcd0_virt_input: endpoint@0 {
|
||||
remote-endpoint = <&hdlcd0_output>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
|
||||
timing0: timing_1080p60 {
|
||||
/* 1920x1080-60 */
|
||||
clock-frequency = <148500000>;
|
||||
hactive = <1920>;
|
||||
vactive = <1080>;
|
||||
hfront-porch = <148>;
|
||||
hback-porch = <88>;
|
||||
hsync-len = <44>;
|
||||
vfront-porch = <36>;
|
||||
vback-porch = <4>;
|
||||
vsync-len = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdlcd0 {
|
||||
status = "ok";
|
||||
|
||||
port {
|
||||
hdlcd0_output: endpoint@0 {
|
||||
remote-endpoint = <&hdlcd0_virt_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue