stats: Update to match classic memory changes
This commit is contained in:
Andreas Sandberg
parent
ee7d8fdcb2
commit
55ed9609f1
147 changed files with 89695 additions and 89151 deletions
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@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu
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sim_ticks 51111167268500 # Number of ticks simulated
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final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 810187 # Simulator instruction rate (inst/s)
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host_op_rate 952145 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 42160127212 # Simulator tick rate (ticks/s)
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host_mem_usage 675168 # Number of bytes of host memory used
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host_seconds 1212.31 # Real time elapsed on the host
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host_inst_rate 933162 # Simulator instruction rate (inst/s)
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host_op_rate 1096667 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 48559439795 # Simulator tick rate (ticks/s)
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host_mem_usage 681072 # Number of bytes of host memory used
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host_seconds 1052.55 # Real time elapsed on the host
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sim_insts 982198023 # Number of instructions simulated
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sim_ops 1154295627 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -16,60 +16,60 @@ system.clk_domain.clock 1000 # Cl
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system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu0.dtb.walker 206336 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 188224 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 3277940 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 38030472 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 3278004 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 38031624 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 207616 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 185152 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 2205440 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 36882176 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 36882368 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory
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system.physmem.bytes_read::total 81620156 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 3277940 # Number of instructions bytes read from this memory
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system.physmem.bytes_read::total 81621564 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 3278004 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 2205440 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 5483380 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 103277952 # Number of bytes written to this memory
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system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 103278592 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
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system.physmem.bytes_written::total 103298532 # Number of bytes written to this memory
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system.physmem.bytes_written::total 103299172 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 3224 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2941 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 91625 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 594239 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 91626 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 594257 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 3244 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 2893 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 34460 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 576284 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 576287 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1315735 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1613718 # Number of write requests responded to by this memory
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system.physmem.num_reads::total 1315757 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1613728 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1616291 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1616301 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 4037 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 3683 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 64134 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 744074 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 64135 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 744096 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 4062 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 3623 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 43150 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 721607 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 721611 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1596914 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 64134 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1596942 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 64135 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 43150 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 107283 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2020653 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2020666 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2021056 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2020653 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_write::total 2021069 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2020666 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 4037 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 3683 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 64134 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 744476 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 64135 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 744499 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 4062 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 43150 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 721607 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 721611 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3617970 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3618010 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
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system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
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@ -338,9 +338,9 @@ system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500
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system.cpu0.dcache.ReadReq_hits::cpu0.data 85600060 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::cpu1.data 85509890 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 171109950 # number of ReadReq hits
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system.cpu0.dcache.WriteReq_hits::cpu0.data 79543301 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::cpu1.data 79530135 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 159073436 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::cpu0.data 79551757 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::cpu1.data 79538240 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 159089997 # number of WriteReq hits
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system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209327 # number of SoftPFReq hits
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system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214988 # number of SoftPFReq hits
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system.cpu0.dcache.SoftPFReq_hits::total 424315 # number of SoftPFReq hits
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@ -353,18 +353,18 @@ system.cpu0.dcache.LoadLockedReq_hits::total 4303549
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system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2274909 # number of StoreCondReq hits
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system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2280735 # number of StoreCondReq hits
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system.cpu0.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits
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system.cpu0.dcache.demand_hits::cpu0.data 165287591 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::cpu1.data 165232078 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::total 330519669 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu0.data 165496918 # number of overall hits
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system.cpu0.dcache.overall_hits::cpu1.data 165447066 # number of overall hits
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system.cpu0.dcache.overall_hits::total 330943984 # number of overall hits
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system.cpu0.dcache.demand_hits::cpu0.data 165296047 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::cpu1.data 165240183 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::total 330536230 # number of demand (read+write) hits
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system.cpu0.dcache.overall_hits::cpu0.data 165505374 # number of overall hits
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system.cpu0.dcache.overall_hits::cpu1.data 165455171 # number of overall hits
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system.cpu0.dcache.overall_hits::total 330960545 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::cpu0.data 3016323 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::cpu1.data 2986728 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::total 6003051 # number of ReadReq misses
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system.cpu0.dcache.WriteReq_misses::cpu0.data 1295379 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::cpu1.data 1272732 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 2568111 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::cpu0.data 1286923 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::cpu1.data 1264627 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 2551550 # number of WriteReq misses
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system.cpu0.dcache.SoftPFReq_misses::cpu0.data 788168 # number of SoftPFReq misses
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system.cpu0.dcache.SoftPFReq_misses::cpu1.data 797714 # number of SoftPFReq misses
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system.cpu0.dcache.SoftPFReq_misses::total 1585882 # number of SoftPFReq misses
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@ -376,12 +376,12 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 127105
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system.cpu0.dcache.LoadLockedReq_misses::total 253898 # number of LoadLockedReq misses
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system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
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system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
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system.cpu0.dcache.demand_misses::cpu0.data 5073259 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::cpu1.data 4744675 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::total 9817934 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu0.data 5861427 # number of overall misses
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system.cpu0.dcache.overall_misses::cpu1.data 5542389 # number of overall misses
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system.cpu0.dcache.overall_misses::total 11403816 # number of overall misses
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system.cpu0.dcache.demand_misses::cpu0.data 5064803 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::cpu1.data 4736570 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::total 9801373 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::cpu0.data 5852971 # number of overall misses
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system.cpu0.dcache.overall_misses::cpu1.data 5534284 # number of overall misses
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system.cpu0.dcache.overall_misses::total 11387255 # number of overall misses
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 88616383 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::cpu1.data 88496618 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses)
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@ -409,9 +409,9 @@ system.cpu0.dcache.overall_accesses::total 342347800 #
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system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034038 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033750 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_miss_rate::total 0.033894 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016024 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015751 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015920 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015651 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses
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system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790147 # miss rate for SoftPFReq accesses
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system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787709 # miss rate for SoftPFReq accesses
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system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788919 # miss rate for SoftPFReq accesses
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@ -423,20 +423,20 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055708
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system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055711 # miss rate for LoadLockedReq accesses
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system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
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system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029779 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027914 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::total 0.028848 # miss rate for demand accesses
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system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034206 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032414 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses
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||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029730 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027866 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::total 0.028799 # miss rate for demand accesses
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||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034156 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032366 # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.writebacks::writebacks 8916863 # number of writebacks
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system.cpu0.dcache.writebacks::total 8916863 # number of writebacks
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system.cpu0.dcache.writebacks::writebacks 8918956 # number of writebacks
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system.cpu0.dcache.writebacks::total 8918956 # number of writebacks
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system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
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system.cpu0.icache.tags.replacements 14265255 # number of replacements
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system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
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@ -829,138 +829,138 @@ system.iocache.avg_blocked_cycles::no_targets nan
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system.iocache.writebacks::writebacks 106631 # number of writebacks
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system.iocache.writebacks::total 106631 # number of writebacks
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||||
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
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||||
system.l2c.tags.replacements 1725785 # number of replacements
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||||
system.l2c.tags.tagsinuse 65319.566840 # Cycle average of tags in use
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||||
system.l2c.tags.total_refs 46977185 # Total number of references to valid blocks.
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system.l2c.tags.sampled_refs 1788801 # Sample count of references to valid blocks.
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system.l2c.tags.avg_refs 26.261828 # Average number of references to valid blocks.
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system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
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system.l2c.tags.occ_blocks::writebacks 37198.027902 # Average occupied blocks per requestor
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||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 157.533597 # Average occupied blocks per requestor
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system.l2c.tags.occ_blocks::cpu0.itb.walker 243.219072 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 3426.787378 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 9571.465720 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.009111 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.itb.walker 207.682961 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2648.640796 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 11713.200303 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.567597 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002404 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003711 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 1725813 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65403.901917 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 49468109 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1788889 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 27.652978 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 9615.108088 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 224.707200 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 268.802991 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 3426.785629 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 22887.229719 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.dtb.walker 209.300949 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.itb.walker 228.038258 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2648.603044 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 25895.326039 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.146715 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003429 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.004102 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.052289 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.146049 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002335 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.itb.walker 0.003169 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.040415 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.178729 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.996697 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 315 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 62701 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 315 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 54255 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.004807 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.956741 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 426273955 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 426273955 # Number of data accesses
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.349231 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003194 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.itb.walker 0.003480 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.040414 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.395131 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 371 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 62705 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 371 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 55700 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.005661 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.956802 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 423190040 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 423190040 # Number of data accesses
|
||||
system.l2c.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 280712 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 145885 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 277418 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 142199 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 846214 # number of ReadReq hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 8916863 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 8916863 # number of WritebackDirty hits
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 265559 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 135827 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 262154 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 132135 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 795675 # number of ReadReq hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 14263678 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 5752 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 5452 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 11204 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 852175 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 837197 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 1689372 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 7090160 # number of ReadCleanReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 15680 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 15013 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 30693 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 852174 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 837196 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 1689370 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 7090159 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 7092615 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 14182775 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 3753750 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 3744981 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 7498731 # number of ReadSharedReq hits
|
||||
system.l2c.InvalidateReq_hits::cpu0.data 340284 # number of InvalidateReq hits
|
||||
system.l2c.InvalidateReq_hits::cpu1.data 354276 # number of InvalidateReq hits
|
||||
system.l2c.InvalidateReq_hits::total 694560 # number of InvalidateReq hits
|
||||
system.l2c.demand_hits::cpu0.dtb.walker 280712 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 145885 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 7090160 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 4605925 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 277418 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 142199 # number of demand (read+write) hits
|
||||
system.l2c.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 3753733 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 3744979 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits
|
||||
system.l2c.InvalidateReq_hits::cpu0.data 340283 # number of InvalidateReq hits
|
||||
system.l2c.InvalidateReq_hits::cpu1.data 354274 # number of InvalidateReq hits
|
||||
system.l2c.InvalidateReq_hits::total 694557 # number of InvalidateReq hits
|
||||
system.l2c.demand_hits::cpu0.dtb.walker 265559 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 135827 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 7090159 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 4605907 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 262154 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 132135 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 7092615 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 4582178 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 24217092 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 280712 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 145885 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 7090160 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 4605925 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 277418 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 142199 # number of overall hits
|
||||
system.l2c.demand_hits::cpu1.data 4582175 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 24166531 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 265559 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 135827 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 7090159 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 4605907 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 262154 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 132135 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 7092615 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 4582178 # number of overall hits
|
||||
system.l2c.overall_hits::total 24217092 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 4582175 # number of overall hits
|
||||
system.l2c.overall_hits::total 24166531 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.dtb.walker 3224 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.itb.walker 2941 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.dtb.walker 3244 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.itb.walker 2893 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 12302 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 20291 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 19639 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 39930 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 1907 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 1973 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 3880 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 417161 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 410444 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 827605 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 48524 # number of ReadCleanReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 417162 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 410445 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 827607 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 48525 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 34473 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 82997 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 177534 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 166566 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 344100 # number of ReadSharedReq misses
|
||||
system.l2c.InvalidateReq_misses::cpu0.data 421273 # number of InvalidateReq misses
|
||||
system.l2c.InvalidateReq_misses::cpu1.data 130939 # number of InvalidateReq misses
|
||||
system.l2c.InvalidateReq_misses::total 552212 # number of InvalidateReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 177551 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 166568 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 344119 # number of ReadSharedReq misses
|
||||
system.l2c.InvalidateReq_misses::cpu0.data 421274 # number of InvalidateReq misses
|
||||
system.l2c.InvalidateReq_misses::cpu1.data 130941 # number of InvalidateReq misses
|
||||
system.l2c.InvalidateReq_misses::total 552215 # number of InvalidateReq misses
|
||||
system.l2c.demand_misses::cpu0.dtb.walker 3224 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.itb.walker 2941 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 48524 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 594695 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 48525 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 594713 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.dtb.walker 3244 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.itb.walker 2893 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 34473 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 577010 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1267004 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 577013 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1267026 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.dtb.walker 3224 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.itb.walker 2941 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 48524 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 594695 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 48525 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 594713 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.dtb.walker 3244 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.itb.walker 2893 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 34473 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 577010 # number of overall misses
|
||||
system.l2c.overall_misses::total 1267004 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 283936 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 148826 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 280662 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 145092 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 858516 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 8916863 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 8916863 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.overall_misses::cpu1.data 577013 # number of overall misses
|
||||
system.l2c.overall_misses::total 1267026 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 268783 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 138768 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 265398 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 135028 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 807977 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 26043 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 25091 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 51134 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 17587 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 16986 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 34573 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 1269336 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -975,122 +975,122 @@ system.l2c.ReadSharedReq_accesses::total 7842831 # nu
|
|||
system.l2c.InvalidateReq_accesses::cpu0.data 761557 # number of InvalidateReq accesses(hits+misses)
|
||||
system.l2c.InvalidateReq_accesses::cpu1.data 485215 # number of InvalidateReq accesses(hits+misses)
|
||||
system.l2c.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.dtb.walker 283936 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.itb.walker 148826 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.dtb.walker 268783 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.itb.walker 138768 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.inst 7138684 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 5200620 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.dtb.walker 280662 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.itb.walker 145092 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.dtb.walker 265398 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.itb.walker 135028 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 7127088 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 5159188 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 25484096 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 283936 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 148826 # number of overall (read+write) accesses
|
||||
system.l2c.demand_accesses::total 25433557 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 268783 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 138768 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 7138684 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 5200620 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.dtb.walker 280662 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.itb.walker 145092 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.dtb.walker 265398 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.itb.walker 135028 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 7127088 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 5159188 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 25484096 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019761 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019939 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.014329 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.779135 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782711 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.780889 # miss rate for UpgradeReq accesses
|
||||
system.l2c.overall_accesses::total 25433557 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011995 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.021194 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.012223 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021425 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.015226 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.108432 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.116154 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.112226 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.328645 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.328976 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.328809 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.328646 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.328977 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006797 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004837 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045159 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042583 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.043874 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.553173 # miss rate for InvalidateReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.269858 # miss rate for InvalidateReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.019761 # miss rate for demand accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045164 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042584 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.553175 # miss rate for InvalidateReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.269862 # miss rate for InvalidateReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::total 0.442916 # miss rate for InvalidateReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011995 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.021194 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.006797 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.114351 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.itb.walker 0.019939 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.114354 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.012223 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.itb.walker 0.021425 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004837 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.111841 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.049717 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.019761 # miss rate for overall accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.111842 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.049817 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011995 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.021194 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.006797 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.114351 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.itb.walker 0.019939 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.114354 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.012223 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.itb.walker 0.021425 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004837 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.111841 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.049717 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.111842 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.049817 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.writebacks::writebacks 1507087 # number of writebacks
|
||||
system.l2c.writebacks::total 1507087 # number of writebacks
|
||||
system.membus.snoop_filter.tot_requests 3814674 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1911370 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2c.writebacks::writebacks 1507097 # number of writebacks
|
||||
system.l2c.writebacks::total 1507097 # number of writebacks
|
||||
system.membus.snoop_filter.tot_requests 3778676 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1875347 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524928 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 524948 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1613718 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 226292 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40497 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1613728 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 226309 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4447 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40498 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 827048 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 827048 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448249 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4448 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 827050 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 827050 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448269 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 658872 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 658872 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5534223 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 5663415 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5462200 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 5591392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6009908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5937885 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177699296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 177868346 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177701344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 177870394 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 185259130 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 185261178 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 3924959 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.009320 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.096090 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3888961 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3888378 99.07% 99.07% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 36581 0.93% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3852380 99.06% 99.06% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3924959 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3888961 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -1171,23 +1171,23 @@ system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500
|
|||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
system.toL2Bus.snoop_filter.tot_requests 52404582 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 26532237 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_requests 52388021 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 26515676 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states
|
||||
system.toL2Bus.trans_dist::ReadReq 1320370 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 23428973 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 8916863 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 2689192 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 51134 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 2687099 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 34573 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 51135 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 34574 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution
|
||||
|
|
@ -1195,27 +1195,27 @@ system.toL2Bus.trans_dist::ReadSharedReq 7842831 # Tr
|
|||
system.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42883049 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35055805 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35022683 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 830232 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1657150 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 80426236 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 80393114 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1233896614 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234030566 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3320928 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6628600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 3070004370 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1762480 # Total snoops (count)
|
||||
system.toL2Bus.snoopTraffic 96494080 # Total snoop traffic (bytes)
|
||||
system.toL2Bus.snoop_fanout::samples 54910458 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.011218 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.105318 # Request fanout histogram
|
||||
system.toL2Bus.pkt_size::total 3070138322 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1762508 # Total snoops (count)
|
||||
system.toL2Bus.snoopTraffic 96494720 # Total snoop traffic (bytes)
|
||||
system.toL2Bus.snoop_fanout::samples 54893925 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.011221 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.105334 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 54294485 98.88% 98.88% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 615973 1.12% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 54277951 98.88% 98.88% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 615974 1.12% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 54910458 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 54893925 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.062409 # Number of seconds simulated
|
||||
sim_ticks 62408957500 # Number of ticks simulated
|
||||
final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.062421 # Number of seconds simulated
|
||||
sim_ticks 62420912500 # Number of ticks simulated
|
||||
final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 176281 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 177159 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 121425676 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 399932 # Number of bytes of host memory used
|
||||
host_seconds 513.97 # Real time elapsed on the host
|
||||
host_inst_rate 255603 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 256876 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 176097831 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 405340 # Number of bytes of host memory used
|
||||
host_seconds 354.47 # Real time elapsed on the host
|
||||
sim_insts 90602850 # Number of instructions simulated
|
||||
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 996736 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu
|
|||
system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 15574 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 62408863500 # Total gap between requests
|
||||
system.physmem.totGap 62420817500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 75120250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 72080000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -217,48 +217,48 @@ system.physmem.busUtilRead 0.12 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 14020 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 14024 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 4007246.92 # Average gap between requests
|
||||
system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 4008014.48 # Average gap between requests
|
||||
system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 671.544396 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 671.524455 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 671.428274 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 671.484088 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 20808236 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted
|
||||
system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 20808241 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups.
|
||||
|
|
@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu
|
|||
system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 124817915 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 124841825 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90602850 # Number of instructions committed
|
||||
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.377638 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.725880 # IPC: instructions per cycle
|
||||
system.cpu.cpi 1.377902 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.725741 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
|
||||
|
|
@ -432,60 +432,60 @@ system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 91054081 # Class of committed instruction
|
||||
system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 946101 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26267146 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26267147 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 980615 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 980613 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
|
||||
|
|
@ -494,28 +494,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -524,14 +524,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 943282 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
|
||||
|
|
@ -542,16 +542,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194
|
|||
system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -562,71 +562,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 5 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 55672985 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27835291 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 27835051 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 27835051 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 801 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 60780500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 27835852 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -641,48 +641,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801
|
|||
system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
|
||||
|
|
@ -711,18 +709,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15581 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1081439500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21652500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 58471000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1161563000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 58471000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -751,18 +749,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -791,18 +789,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 954685000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -815,25 +813,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
|
||||
|
|
@ -867,7 +865,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 1201999 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1030 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14544 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14544 # Transaction distribution
|
||||
|
|
@ -888,9 +892,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15574 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.361598 # Number of seconds simulated
|
||||
sim_ticks 361597758500 # Number of ticks simulated
|
||||
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.361613 # Number of seconds simulated
|
||||
sim_ticks 361613361500 # Number of ticks simulated
|
||||
final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1165746 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1165794 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1728825291 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 381188 # Number of bytes of host memory used
|
||||
host_seconds 209.16 # Real time elapsed on the host
|
||||
host_inst_rate 1370596 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2032709522 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 385816 # Number of bytes of host memory used
|
||||
host_seconds 177.90 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
|
||||
|
|
@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 56256 # Nu
|
|||
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 723195517 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 723226723 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 243825150 # Number of instructions committed
|
||||
|
|
@ -53,7 +53,7 @@ system.cpu.num_mem_refs 105711441 # nu
|
|||
system.cpu.num_load_insts 82803521 # Number of load instructions
|
||||
system.cpu.num_store_insts 22907920 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29302884 # Number of branches fetched
|
||||
|
|
@ -92,25 +92,25 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 244431613 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
|
||||
|
|
@ -131,16 +131,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n
|
|||
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -161,16 +161,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -189,16 +189,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
|
|||
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -209,26 +209,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||
|
|
@ -237,7 +237,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 781
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits
|
||||
|
|
@ -250,12 +250,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n
|
|||
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 882 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
|
||||
|
|
@ -268,12 +268,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
|
|||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -288,48 +288,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882
|
|||
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
|
||||
|
|
@ -358,18 +356,18 @@ system.cpu.l2cache.demand_misses::total 15603 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -398,18 +396,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -428,18 +426,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15603
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -452,25 +450,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
|
||||
|
|
@ -504,7 +502,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1036 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,51 +1,51 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.366199 # Number of seconds simulated
|
||||
sim_ticks 366199170500 # Number of ticks simulated
|
||||
final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.366229 # Number of seconds simulated
|
||||
sim_ticks 366229314500 # Number of ticks simulated
|
||||
final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 454673 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 800606 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1053878980 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 406480 # Number of bytes of host memory used
|
||||
host_seconds 347.48 # Real time elapsed on the host
|
||||
host_inst_rate 561124 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 988050 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1300728257 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 412916 # Number of bytes of host memory used
|
||||
host_seconds 281.56 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1922944 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6528 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6656 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 102 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 30046 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 104 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 732398341 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 732458629 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 157988548 # Number of instructions committed
|
||||
|
|
@ -66,7 +66,7 @@ system.cpu.num_mem_refs 122219137 # nu
|
|||
system.cpu.num_load_insts 90779385 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439752 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29309705 # Number of branches fetched
|
||||
|
|
@ -105,25 +105,25 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 278192465 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
|
||||
|
|
@ -140,14 +140,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n
|
|||
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 25500310500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2830649000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28330959500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28330959500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28330959500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28330959500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -164,14 +164,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13707.452092 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13707.452092 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -188,14 +188,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
|
|||
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26264130500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26264130500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -204,22 +204,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 665.626582 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.626582 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
|
||||
|
|
@ -229,7 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 715
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits
|
||||
|
|
@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n
|
|||
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 50660000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 50660000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 50660000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 50660000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 50660000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses
|
||||
|
|
@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
|
|||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62698.019802 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62698.019802 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -280,48 +280,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808
|
|||
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 49852000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 49852000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 49852000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 313 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks.
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 315 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 21080.806353 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4100347 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30047 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 136.464439 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 0.624695 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000019 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.626347 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.643335 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29732 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 33073199 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 33073199 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits
|
||||
|
|
@ -330,38 +330,38 @@ system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 #
|
|||
system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1960501 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2037586 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2037591 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2037586 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2037591 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 219 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 219 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 29243 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 30046 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30044 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29243 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30046 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1755983000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 48585000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1769232500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1817817500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 48585000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1769232500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1817817500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -382,91 +382,91 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530
|
|||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.014532 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014532 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 102 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 104 # number of writebacks
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 29243 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 30046 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 29243 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 30046 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
|
||||
|
|
@ -479,53 +479,59 @@ system.cpu.toL2Bus.pkt_count::total 6198031 # Pa
|
|||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 313 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 6528 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoops 315 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 6656 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2067952 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2067952 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1020 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 102 # Transaction distribution
|
||||
system.membus.snoop_filter.tot_requests 30164 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1022 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 104 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 14 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 1022 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 60210 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 1929600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 30160 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 30046 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 30046 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 30160 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 30046 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 30614500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 150230000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.279361 # Nu
|
|||
sim_ticks 279360903000 # Number of ticks simulated
|
||||
final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1100009 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1191455 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 606617028 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259840 # Number of bytes of host memory used
|
||||
host_seconds 460.52 # Real time elapsed on the host
|
||||
host_inst_rate 1206466 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1306763 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 665324846 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263448 # Number of bytes of host memory used
|
||||
host_seconds 419.89 # Real time elapsed on the host
|
||||
sim_insts 506578818 # Number of instructions simulated
|
||||
sim_ops 548692039 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 548692589 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 630707528 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 632196069 # Transaction distribution
|
||||
|
|
@ -239,14 +245,14 @@ system.membus.pkt_size::total 2705349287 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 687926230 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 687926230 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,45 +1,45 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.708539 # Number of seconds simulated
|
||||
sim_ticks 708539449500 # Number of ticks simulated
|
||||
final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.708700 # Number of seconds simulated
|
||||
sim_ticks 708700329500 # Number of ticks simulated
|
||||
final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 665557 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 720769 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 933837970 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269828 # Number of bytes of host memory used
|
||||
host_seconds 758.74 # Real time elapsed on the host
|
||||
host_inst_rate 820539 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 888607 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1151553403 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275232 # Number of bytes of host memory used
|
||||
host_seconds 615.43 # Real time elapsed on the host
|
||||
sim_insts 504984064 # Number of instructions simulated
|
||||
sim_ops 546875315 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 1417078899 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 1417400659 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504984064 # Number of instructions committed
|
||||
|
|
@ -182,7 +182,7 @@ system.cpu.num_mem_refs 172743505 # nu
|
|||
system.cpu.num_load_insts 115883283 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860222 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 121552863 # Number of branches fetched
|
||||
|
|
@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 548692589 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 1136276 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
|
|
@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits
|
||||
|
|
@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 1140371 # n
|
|||
system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1140372 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006774
|
|||
system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1065708 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1065429 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses
|
||||
|
|
@ -323,16 +323,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1140371
|
|||
system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -343,26 +343,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
|
|
@ -372,7 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits
|
||||
|
|
@ -385,12 +385,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n
|
|||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses
|
||||
|
|
@ -403,12 +403,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022
|
|||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -423,89 +423,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521
|
|||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 110394 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 110813 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 28700.010798 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2150809 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 143581 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 14.979761 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 210357436000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.875855 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18498717 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18498717 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 744258 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 999933 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1009151 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses
|
||||
system.cpu.l2cache.overall_hits::cpu.data 999933 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1009151 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 100833 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 100833 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 39606 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 140439 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 142742 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 142364 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 140439 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 142742 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8642481500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8642481500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1065429 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -520,101 +520,101 @@ system.cpu.l2cache.demand_accesses::total 1151893 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.123919 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123919 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 96330 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 96648 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 96648 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 140439 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 142742 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 142742 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
|
||||
|
|
@ -623,53 +623,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 6165120 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 110813 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 41576 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 108784 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 41909 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 96648 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 12014 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100833 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100833 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 250615 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 142743 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 142743 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 250615 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 142743 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 644372828 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 713710000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.885773 # Nu
|
|||
sim_ticks 885772926000 # Number of ticks simulated
|
||||
final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 771975 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1428542 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 826990545 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269652 # Number of bytes of host memory used
|
||||
host_seconds 1071.08 # Real time elapsed on the host
|
||||
host_inst_rate 861241 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1593729 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 922618164 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273768 # Number of bytes of host memory used
|
||||
host_seconds 960.06 # Real time elapsed on the host
|
||||
sim_insts 826847304 # Number of instructions simulated
|
||||
sim_ops 1530082521 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1530082521 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution
|
||||
|
|
@ -122,14 +128,14 @@ system.membus.pkt_size::total 11823849838 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1601552189 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1601552189 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,51 +1,51 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.650501 # Number of seconds simulated
|
||||
sim_ticks 1650501252500 # Number of ticks simulated
|
||||
final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.650924 # Number of seconds simulated
|
||||
sim_ticks 1650923912500 # Number of ticks simulated
|
||||
final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 516047 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 954946 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1030101248 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278616 # Number of bytes of host memory used
|
||||
host_seconds 1602.27 # Real time elapsed on the host
|
||||
host_inst_rate 598809 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1108098 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1195612149 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 285816 # Number of bytes of host memory used
|
||||
host_seconds 1380.82 # Real time elapsed on the host
|
||||
sim_insts 826847304 # Number of instructions simulated
|
||||
sim_ops 1530082521 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 3301002505 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 3301847825 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826847304 # Number of instructions committed
|
||||
|
|
@ -66,7 +66,7 @@ system.cpu.num_mem_refs 533241508 # nu
|
|||
system.cpu.num_load_insts 384083313 # Number of load instructions
|
||||
system.cpu.num_store_insts 149158195 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 149981740 # Number of branches fetched
|
||||
|
|
@ -105,16 +105,16 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1530082521 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 2517016 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
|
|
@ -124,7 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits
|
||||
|
|
@ -141,14 +141,14 @@ system.cpu.dcache.demand_misses::cpu.data 2521112 # n
|
|||
system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2521112 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -165,22 +165,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004728
|
|||
system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2325221 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2324919 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses
|
||||
|
|
@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2521112
|
|||
system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -205,22 +205,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
|
||||
|
|
@ -232,7 +232,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1507
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits
|
||||
|
|
@ -245,12 +245,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n
|
|||
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses
|
||||
|
|
@ -263,12 +263,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003
|
|||
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -283,89 +283,88 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814
|
|||
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 124423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 124423000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 348438 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 349420 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 380855 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 584841 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1002 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556392 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1556392 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1002 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2141233 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2142235 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1002 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2141233 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2142235 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 206529 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1812 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 381691 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -380,101 +379,101 @@ system.cpu.l2cache.demand_accesses::total 2523926 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 293208 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 293952 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
|
||||
|
|
@ -483,55 +482,61 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 18765312 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 349420 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 174499 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 175162 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 53608 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206529 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206529 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 727569 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 381691 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 727569 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 381691 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.233526 # Number of seconds simulated
|
||||
sim_ticks 233525789500 # Number of ticks simulated
|
||||
final_tick 233525789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.233534 # Number of seconds simulated
|
||||
sim_ticks 233533887500 # Number of ticks simulated
|
||||
final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 279317 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 279317 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 163615265 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 255720 # Number of bytes of host memory used
|
||||
host_seconds 1427.29 # Real time elapsed on the host
|
||||
host_inst_rate 225573 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 225573 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 132138421 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260868 # Number of bytes of host memory used
|
||||
host_seconds 1767.34 # Real time elapsed on the host
|
||||
sim_insts 398664651 # Number of instructions simulated
|
||||
sim_ops 398664651 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1067462 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1090209 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2157672 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1067462 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1067462 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1067462 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1090209 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2157672 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7873 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 233525688500 # Total gap between requests
|
||||
system.physmem.totGap 233533785500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6857 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 948 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 326.852693 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 195.480715 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 331.694198 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 535 34.72% 34.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 344 22.32% 57.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 186 12.07% 69.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 104 6.75% 75.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 66 4.28% 80.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 53 3.44% 83.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 28 1.82% 85.40% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 39 2.53% 87.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 186 12.07% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52273750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 199892500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 53440000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6639.62 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25389.62 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.02 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6330 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6327 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 29661588.78 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6804000 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3712500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 29662617.24 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5982776145 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 134867232750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 156147584715 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.653337 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 224361889750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7797920000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.682165 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1365674000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 4845960 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2644125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5743132470 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 135077446500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 156107858775 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.483223 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 224713608000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7797920000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.481917 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1013955750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 45912937 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 26702744 # Number of conditional branches predicted
|
||||
system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 45912940 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 25186730 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 74.689251 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 2249877 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 13974 # Number of indirect misses.
|
||||
system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 95338457 # DTB read hits
|
||||
system.cpu.dtb.read_hits 95338456 # DTB read hits
|
||||
system.cpu.dtb.read_misses 116 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 95338573 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 95338572 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73578378 # DTB write hits
|
||||
system.cpu.dtb.write_misses 849 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73579227 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 168916835 # DTB hits
|
||||
system.cpu.dtb.data_hits 168916834 # DTB hits
|
||||
system.cpu.dtb.data_misses 965 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 168917800 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 96959231 # ITB hits
|
||||
system.cpu.dtb.data_accesses 168917799 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 96959232 # ITB hits
|
||||
system.cpu.itb.fetch_misses 1239 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 96960470 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 96960471 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 467051579 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 467067775 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664651 # Number of instructions committed
|
||||
system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.171540 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.853577 # IPC: instructions per cycle
|
||||
system.cpu.cpi 1.171581 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.853548 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
|
||||
|
|
@ -344,18 +344,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 398664651 # Class of committed instruction
|
||||
system.cpu.tickCycles 455740556 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 11311023 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 771 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3291.966637 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 167817023 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40292.202401 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.966637 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.803703 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803703 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id
|
||||
|
|
@ -365,31 +365,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73514800 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514800 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 167817023 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 167817023 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 167817023 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 167817023 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 167817024 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5929 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5929 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 6990 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 6990 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 6990 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 6990 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 77930500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 77930500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 429190000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 429190000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 507120500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 507120500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 507120500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 507120500 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 6989 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73450.047125 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73450.047125 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72388.261090 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 72388.261090 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72549.427754 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72549.427754 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu
|
|||
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2733 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2733 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2825 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2825 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2825 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses
|
||||
|
|
@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165
|
|||
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70280500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 70280500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239912500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 239912500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310193000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 310193000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310193000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 310193000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -454,69 +454,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72528.895769 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72528.895769 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75066.489362 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75066.489362 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 3193 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1919.750364 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 96954060 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18749.576484 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.750364 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937378 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.937378 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 193923633 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 193923633 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 96954060 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 96954060 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 96954060 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 96954060 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 96954060 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 96954060 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 96954061 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5171 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 318040500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 318040500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 318040500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 318040500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 318040500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 318040500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 96959231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 96959231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 96959231 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 96959231 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 96959231 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 96959231 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 96959232 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 96959232 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 96959232 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 96959232 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 96959232 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61504.641269 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61504.641269 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61504.641269 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61504.641269 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61504.641269 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62260.394508 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62260.394508 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62260.394508 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62260.394508 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62260.394508 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -531,47 +531,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5171
|
|||
system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312869500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 312869500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312869500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 312869500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312869500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 312869500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 316777500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 316777500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 316777500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 316777500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 316777500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 316777500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60504.641269 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60504.641269 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4425.384656 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4801 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.910487 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 7128.160045 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5427 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.689318 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 372.164909 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.179805 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 642.039942 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011358 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104101 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019594 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.135052 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4442 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 114871 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 114871 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.137560 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3717.022485 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104100 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113435 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.217534 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits
|
||||
|
|
@ -600,18 +599,18 @@ system.cpu.l2cache.demand_misses::total 7873 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7873 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234589500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 234589500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291713500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 291713500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67354500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 67354500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 291713500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 301944000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 593657500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 291713500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 301944000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 593657500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 237071000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 237071000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 295621500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 295621500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 70008000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 70008000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 295621500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 307079000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 602700500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 295621500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 307079000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 602700500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -640,18 +639,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.843295 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74781.479120 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74781.479120 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74894.351733 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74894.351733 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80088.585018 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80088.585018 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75404.229646 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75404.229646 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -670,18 +669,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7873
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203219500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203219500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252763500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252763500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58944500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58944500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252763500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262164000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 514927500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252763500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262164000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 514927500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -694,25 +693,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.479120 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.479120 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64894.351733 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64894.351733 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70088.585018 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70088.585018 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution
|
||||
|
|
@ -744,9 +743,15 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # La
|
|||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 4736 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3137 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3137 # Transaction distribution
|
||||
|
|
@ -767,9 +772,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7873 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9219000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 41801750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.567385 # Number of seconds simulated
|
||||
sim_ticks 567385356500 # Number of ticks simulated
|
||||
final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.567393 # Number of seconds simulated
|
||||
sim_ticks 567392530500 # Number of ticks simulated
|
||||
final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1154582 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1154582 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1643217424 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254440 # Number of bytes of host memory used
|
||||
host_seconds 345.29 # Real time elapsed on the host
|
||||
host_inst_rate 646502 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 646502 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 920122456 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259072 # Number of bytes of host memory used
|
||||
host_seconds 616.65 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 459136 # Number of bytes read from this memory
|
||||
|
|
@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 205120 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 1134770713 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 1134785061 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664609 # Number of instructions committed
|
||||
|
|
@ -85,7 +85,7 @@ system.cpu.num_mem_refs 168275276 # nu
|
|||
system.cpu.num_load_insts 94754511 # Number of load instructions
|
||||
system.cpu.num_store_insts 73520765 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1134770713 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1134785061 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 44587535 # Number of branches fetched
|
||||
|
|
@ -124,16 +124,16 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 398664665 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
|
||||
|
|
@ -143,7 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
|
||||
|
|
@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n
|
|||
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -224,34 +224,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
|
||||
|
|
@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n
|
|||
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3673 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
|
||||
|
|
@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009
|
|||
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -302,48 +302,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673
|
|||
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits
|
||||
|
|
@ -372,18 +370,18 @@ system.cpu.l2cache.demand_misses::total 7174 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -412,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -442,18 +440,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7174
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -466,25 +464,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution
|
||||
|
|
@ -518,7 +516,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 4032 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.225030 # Number of seconds simulated
|
||||
sim_ticks 225030243000 # Number of ticks simulated
|
||||
final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.225041 # Number of seconds simulated
|
||||
sim_ticks 225040911000 # Number of ticks simulated
|
||||
final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 131394 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 157754 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 108291606 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275248 # Number of bytes of host memory used
|
||||
host_seconds 2078.00 # Real time elapsed on the host
|
||||
host_inst_rate 161529 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 193933 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 133133968 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 280148 # Number of bytes of host memory used
|
||||
host_seconds 1690.33 # Real time elapsed on the host
|
||||
sim_insts 273037855 # Number of instructions simulated
|
||||
sim_ops 327812212 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 485568 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 219136 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7587 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 225029996000 # Total gap between requests
|
||||
system.physmem.totGap 225040663000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 51456750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 55497500 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -217,48 +217,48 @@ system.physmem.busUtilRead 0.02 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6068 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6044 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 29659944.11 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 29661350.07 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.664832 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states
|
||||
system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.691134 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.764823 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states
|
||||
system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.800930 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 32430290 # Number of BP lookups
|
||||
system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 32430292 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups.
|
||||
|
|
@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 2264813 # Nu
|
|||
system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 450060486 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 450081822 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037855 # Number of instructions committed
|
||||
system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.648345 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.606669 # IPC: instructions per cycle
|
||||
system.cpu.cpi 1.648423 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.606640 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction
|
||||
|
|
@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 327812212 # Class of committed instruction
|
||||
system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 1355 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
|
||||
|
|
@ -451,43 +451,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 7
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168632427 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168632429 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 6936 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 6935 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses)
|
||||
|
|
@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
|
||||
|
|
@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -528,12 +528,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu
|
|||
system.cpu.dcache.writebacks::total 1010 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
|
||||
|
|
@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509
|
|||
system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -564,72 +564,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 38188 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 69819783 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 69819782 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 40126 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126
|
|||
system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits
|
||||
|
|
@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 7630 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7630 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214976500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 214976500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 256075000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 256075000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 105174500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 105174500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 256075000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 320151000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 576226000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 256075000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 320151000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 576226000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.170931 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75324.632095 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75324.632095 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74744.600117 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74744.600117 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77907.037037 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77907.037037 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75521.100917 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75521.100917 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7587
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186436500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186436500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 221700500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 221700500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 89390500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 89390500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 221700500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275827000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 497527500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 221700500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275827000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 497527500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65324.632095 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65324.632095 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64748.977804 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64748.977804 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution
|
||||
|
|
@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 60188498 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 4733 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2854 # Transaction distribution
|
||||
|
|
@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7587 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu
|
|||
sim_ticks 201717314000 # Number of ticks simulated
|
||||
final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 732440 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 879375 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 541118678 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263976 # Number of bytes of host memory used
|
||||
host_seconds 372.78 # Real time elapsed on the host
|
||||
host_inst_rate 781022 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 937704 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 577011080 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268872 # Number of bytes of host memory used
|
||||
host_seconds 349.59 # Real time elapsed on the host
|
||||
sim_insts 273037595 # Number of instructions simulated
|
||||
sim_ops 327811950 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 327812145 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 434895828 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 434906723 # Transaction distribution
|
||||
|
|
@ -239,14 +245,14 @@ system.membus.pkt_size::total 2275398075 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 517024352 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 517024352 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.517291 # Number of seconds simulated
|
||||
sim_ticks 517291025500 # Number of ticks simulated
|
||||
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.517298 # Number of seconds simulated
|
||||
sim_ticks 517297855500 # Number of ticks simulated
|
||||
final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 451771 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 542368 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 856851233 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273716 # Number of bytes of host memory used
|
||||
host_seconds 603.71 # Real time elapsed on the host
|
||||
host_inst_rate 565388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 678769 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1072356714 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278352 # Number of bytes of host memory used
|
||||
host_seconds 482.39 # Real time elapsed on the host
|
||||
sim_insts 272739286 # Number of instructions simulated
|
||||
sim_ops 327433744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
|
||||
|
|
@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 166912 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 1034582051 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 1034595711 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 272739286 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 168107847 # nu
|
|||
system.cpu.num_load_insts 85732248 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563503 # Number of branches fetched
|
||||
|
|
@ -214,16 +214,16 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 327812214 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3078.320204 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751543 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
|
||||
|
|
@ -233,7 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
|
||||
|
|
@ -258,14 +258,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n
|
|||
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 89418000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 269696500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 269696500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -290,14 +290,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60253.909741 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475
|
|||
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87767000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 87767000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177406500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 177406500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 186000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265173500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 265173500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 265359500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -342,26 +342,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1765.939670 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862275 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862275 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||
|
|
@ -371,7 +371,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1524
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
|
||||
|
|
@ -384,12 +384,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n
|
|||
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 341054000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 341054000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 341054000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
|
||||
|
|
@ -402,12 +402,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045
|
|||
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21858.232391 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21858.232391 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -422,48 +422,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603
|
|||
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 5901.352793 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 3.031616 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.180095 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
|
||||
|
|
@ -492,18 +490,18 @@ system.cpu.l2cache.demand_misses::total 6832 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 255885500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 413785500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 255885500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 413785500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -532,18 +530,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -562,18 +560,18 @@ system.cpu.l2cache.demand_mshr_misses::total 6832
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -586,25 +584,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
|
||||
|
|
@ -638,7 +636,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 6833 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu
|
|||
sim_ticks 464394627000 # Number of ticks simulated
|
||||
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2033284 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2033284 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1016862727 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248468 # Number of bytes of host memory used
|
||||
host_seconds 456.69 # Real time elapsed on the host
|
||||
host_inst_rate 1533629 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1533629 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 766980884 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 251816 # Number of bytes of host memory used
|
||||
host_seconds 605.48 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 928789150 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution
|
||||
|
|
@ -144,14 +150,14 @@ system.membus.pkt_size::total 6109961839 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1264600947 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1264600947 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,43 +1,43 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.288319 # Number of seconds simulated
|
||||
sim_ticks 1288319411500 # Number of ticks simulated
|
||||
final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.288611 # Number of seconds simulated
|
||||
sim_ticks 1288611150500 # Number of ticks simulated
|
||||
final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1112167 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1112167 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1543016447 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257436 # Number of bytes of host memory used
|
||||
host_seconds 834.94 # Real time elapsed on the host
|
||||
host_inst_rate 1122029 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1122029 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1557051854 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262324 # Number of bytes of host memory used
|
||||
host_seconds 827.60 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18512320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18649344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 289255 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291396 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_read::cpu.inst 106335 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14366103 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14472437 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 106335 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 106335 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3311870 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3311870 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3311870 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 106335 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14366103 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 17784307 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 2576638823 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 2577222301 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 928587629 # Number of instructions committed
|
||||
|
|
@ -92,7 +92,7 @@ system.cpu.num_mem_refs 336013318 # nu
|
|||
system.cpu.num_load_insts 237705247 # Number of load instructions
|
||||
system.cpu.num_store_insts 98308071 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2576638823 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2577222301 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 123111018 # Number of branches fetched
|
||||
|
|
@ -131,16 +131,16 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 928789150 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 776432 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4094.168779 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 1112572500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.168779 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
|
||||
|
|
@ -167,14 +167,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n
|
|||
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20380048000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 20380048000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4229584000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4229584000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24609632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24609632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24609632000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24609632000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -191,22 +191,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28643.214329 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28643.214329 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61285.884024 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61285.884024 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31529.467232 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31529.467232 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88866 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 88841 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88841 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
|
||||
|
|
@ -215,14 +215,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528
|
|||
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19668534000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19668534000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4160570000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4160570000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23829104000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23829104000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23829104000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23829104000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -231,24 +231,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27643.214329 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27643.214329 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60285.884024 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60285.884024 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 4618 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1474.409268 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.409268 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.719926 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.719926 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
|
||||
|
|
@ -257,7 +257,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1428
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits
|
||||
|
|
@ -270,12 +270,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n
|
|||
system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 6168 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 187267500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 187267500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 187267500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 187267500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 187267500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 187267500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
|
||||
|
|
@ -288,12 +288,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007
|
|||
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30361.138132 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 30361.138132 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 30361.138132 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 30361.138132 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -308,90 +308,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168
|
|||
system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 181099500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 181099500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 181099500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 181099500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 181099500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 181099500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 258847 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29361.138132 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29361.138132 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 258865 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32717.214949 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1276112 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291633 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.375746 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 4209362000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27.944200 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.856544 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 32641.414205 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000853 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001460 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.996137 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998450 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31170 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12833601 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12833601 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88841 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88841 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488907 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 488907 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 491273 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 495300 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 495307 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 491273 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 495300 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222607 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222607 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 289255 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 291396 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291389 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 289255 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291396 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4032205000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4032205000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 129556500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 129556500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13467735000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13467735000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 129556500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 17499940000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17629496500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 129556500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 17499940000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17629496500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88841 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88841 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -410,26 +410,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717
|
|||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312864 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312864 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370589 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.370405 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370589 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.370405 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.015004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.015004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60512.143858 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60512.143858 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.051661 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.051661 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60500.132123 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60500.132123 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -444,63 +444,63 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648
|
|||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222607 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222607 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 289255 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291396 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles
|
||||
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|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles
|
||||
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|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 289255 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291396 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3365725000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3365725000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 108146500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 108146500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11241665000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11241665000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108146500 # number of demand (read+write) MSHR miss cycles
|
||||
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|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14715536500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108146500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14607390000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14715536500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312864 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312864 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.370405 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.370405 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.015004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.015004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50512.143858 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50512.143858 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.051661 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.051661 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1726 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1726 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155524 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 879773 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution
|
||||
|
|
@ -509,53 +509,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258847 # Total snoops (count)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56329920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258865 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1045561 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001651 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.040596 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1043835 99.83% 99.83% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1726 0.17% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1045561 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 877332000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 224741 # Transaction distribution
|
||||
system.membus.snoop_filter.tot_requests 548536 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 257140 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 224748 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190447 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190457 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 224748 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839932 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 839932 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22917056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22917056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 548519 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 291396 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 291396 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 548519 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 291396 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 815280500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1456980000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu
|
|||
sim_ticks 395726778500 # Number of ticks simulated
|
||||
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 860032 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1058813 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 531234389 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264584 # Number of bytes of host memory used
|
||||
host_seconds 744.92 # Real time elapsed on the host
|
||||
host_inst_rate 969638 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1193752 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 598936996 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268708 # Number of bytes of host memory used
|
||||
host_seconds 660.72 # Real time elapsed on the host
|
||||
sim_insts 640654411 # Number of instructions simulated
|
||||
sim_ops 788730070 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 788730744 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
|
||||
|
|
@ -239,14 +245,14 @@ system.membus.pkt_size::total 4241547525 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,45 +1,45 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.045756 # Number of seconds simulated
|
||||
sim_ticks 1045756396500 # Number of ticks simulated
|
||||
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.046047 # Number of seconds simulated
|
||||
sim_ticks 1046047111500 # Number of ticks simulated
|
||||
final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 546786 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 671760 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 894330624 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273552 # Number of bytes of host memory used
|
||||
host_seconds 1169.32 # Real time elapsed on the host
|
||||
host_inst_rate 666714 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 819099 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1090788712 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 278188 # Number of bytes of host memory used
|
||||
host_seconds 958.98 # Real time elapsed on the host
|
||||
sim_insts 639366787 # Number of instructions simulated
|
||||
sim_ops 785501035 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 2091512793 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 2092094223 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 639366787 # Number of instructions committed
|
||||
|
|
@ -182,7 +182,7 @@ system.cpu.num_mem_refs 381221435 # nu
|
|||
system.cpu.num_load_insts 252240938 # Number of load instructions
|
||||
system.cpu.num_store_insts 128980497 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 137364860 # Number of branches fetched
|
||||
|
|
@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 788730744 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 778046 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
||||
|
|
@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits
|
||||
|
|
@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n
|
|||
system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 782143 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88995 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88967 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -329,16 +329,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003
|
|||
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -349,26 +349,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 8769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
||||
|
|
@ -376,7 +376,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1339
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits
|
||||
|
|
@ -389,12 +389,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n
|
|||
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 10208 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses
|
||||
|
|
@ -407,12 +407,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016
|
|||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -427,90 +427,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208
|
|||
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210621500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 210621500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210621500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 210621500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210621500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 210621500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 257772 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20632.983934 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20632.983934 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20632.983934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 257791 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32695.724167 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1287496 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290559 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.431100 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 4679738000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 22.200866 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.803141 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 32627.720160 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000678 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001398 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.995719 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997794 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30945 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12914999 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12914999 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88967 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88967 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490296 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 490296 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 493526 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 501975 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 501982 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 493526 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 501975 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222523 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222523 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 288616 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 290375 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 290368 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 290375 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3998679500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17568112000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 106512500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17568112000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88967 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -529,26 +529,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407
|
|||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312173 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312173 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.369007 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.366473 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369007 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.366473 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.801900 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60552.870949 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60501.251556 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60501.251556 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60501.461903 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60552.870949 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.148585 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60501.461903 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -561,61 +561,61 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093
|
|||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222523 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222523 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288616 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 290375 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution
|
||||
|
|
@ -624,53 +624,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 257772 # Total snoops (count)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 257791 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 224275 # Transaction distribution
|
||||
system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 224282 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190094 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190103 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 546561 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 290376 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 546561 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 290376 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu
|
|||
sim_ticks 913189263000 # Number of ticks simulated
|
||||
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2010513 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2010513 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1008901575 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 239516 # Number of bytes of host memory used
|
||||
host_seconds 905.13 # Real time elapsed on the host
|
||||
host_inst_rate 1729437 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1729437 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 867853739 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243124 # Number of bytes of host memory used
|
||||
host_seconds 1052.24 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1826378509 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution
|
||||
|
|
@ -144,14 +150,14 @@ system.membus.pkt_size::total 10108087278 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2431702674 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2431702674 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,43 +1,43 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.636720 # Number of seconds simulated
|
||||
sim_ticks 2636719559500 # Number of ticks simulated
|
||||
final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.639614 # Number of seconds simulated
|
||||
sim_ticks 2639613874500 # Number of ticks simulated
|
||||
final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1223384 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1223384 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1772587765 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249508 # Number of bytes of host memory used
|
||||
host_seconds 1487.50 # Real time elapsed on the host
|
||||
host_inst_rate 1111155 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1111155 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1611744129 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254908 # Number of bytes of host memory used
|
||||
host_seconds 1637.74 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 126106432 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 126157760 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 66087296 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 66087296 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.num_reads::cpu.data 1970413 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1971215 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1032614 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1032614 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 19445 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 47774575 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 47794021 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 19445 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 19445 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 25036729 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 25036729 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 25036729 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 19445 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47774575 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72830749 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 5273439119 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 5279227749 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1819780127 # Number of instructions committed
|
||||
|
|
@ -92,7 +92,7 @@ system.cpu.num_mem_refs 611922547 # nu
|
|||
system.cpu.num_load_insts 449492741 # Number of load instructions
|
||||
system.cpu.num_store_insts 162429806 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5273439119 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 5279227749 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
|
|
@ -131,26 +131,26 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1826378509 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4079.303630 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 41048093500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.303630 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995924 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2646 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
|
||||
|
|
@ -167,14 +167,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n
|
|||
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 152711735000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 152711735000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 64261460000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 64261460000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 216973195000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 216973195000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 216973195000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 216973195000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -191,22 +191,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053
|
|||
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21144.140311 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21144.140311 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34013.009972 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34013.009972 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23812.503196 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23812.503196 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3679426 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 3664823 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3664823 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
|
||||
|
|
@ -215,14 +215,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734
|
|||
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145489321000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 145489321000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62372140000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 62372140000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207861461000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 207861461000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207861461000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 207861461000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -231,24 +231,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20144.140311 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20144.140311 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33013.009972 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33013.009972 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 612.633318 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.633318 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299137 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299137 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
|
|
@ -256,7 +256,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 730
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits
|
||||
|
|
@ -269,12 +269,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n
|
|||
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 802 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 50541500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 50541500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 50541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 50541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 50541500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 50541500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
|
||||
|
|
@ -287,12 +287,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63019.326683 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 63019.326683 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 63019.326683 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 63019.326683 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -307,86 +307,86 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802
|
|||
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 48957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 48957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48957500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 48957500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49739500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 49739500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49739500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 49739500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49739500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 49739500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1919525 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1949317 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.377074 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 218471945000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.824340 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.460561 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001185 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.470286 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.932032 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1058 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62019.326683 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62019.326683 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1938767 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31260.683710 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 16248398 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1971535 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 8.241496 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 217871689000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8.109026 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.419408 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31214.155276 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000247 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001172 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.952580 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.954000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 664 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1281 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27794 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 147732935 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 147732935 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3664823 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3664823 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106935 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1106935 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6053359 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6053359 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7160294 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7160294 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7160294 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7160294 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782385 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782385 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1095314 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1095314 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046007 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6046007 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7141321 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7141321 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7141321 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7141321 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 794006 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 794006 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1169055 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1169055 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176407 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1176407 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951440 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1952242 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1970413 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1971215 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951440 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1952242 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46551911500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46551911500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47746500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47746500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69565328500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69565328500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 47746500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116117240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116164986500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 47746500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116117240000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116164986500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3679426 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3679426 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1970413 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1971215 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48037363000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 48037363000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48529000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 48529000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71172626500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 71172626500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 48529000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 119209989500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 119258518500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 48529000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 119209989500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 119258518500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3664823 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3664823 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -401,101 +401,101 @@ system.cpu.l2cache.demand_accesses::total 9112536 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414109 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414109 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420260 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.420260 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161865 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161865 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162883 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162883 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214168 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214237 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.216250 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.216319 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214168 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214237 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.005113 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.005113 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59534.289277 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59534.289277 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.607948 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.607948 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59503.374326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59503.374326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.216250 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.216319 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60509.975062 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60509.975062 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.002550 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.002550 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60500.005580 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60500.005580 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1021962 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 1032614 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1032614 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 794006 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 794006 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1169055 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1169055 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176407 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176407 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951440 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1952242 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1970413 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1971215 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38728061500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38728061500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39726500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39726500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57874778500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57874778500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39726500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96602840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96642566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39726500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96602840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96642566500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1970413 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1971215 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40097303000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40097303000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40509000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40509000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59408556500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59408556500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40509000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99505859500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 99546368500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40509000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99505859500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 99546368500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414109 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420260 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420260 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161865 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161865 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162883 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162883 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.216319 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.216319 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50509.975062 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50509.975062 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.002550 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.002550 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1292 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1292 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4697437 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6348968 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
|
||||
|
|
@ -504,53 +504,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919525 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 65405568 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 817699648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 817751040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1938767 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 66087296 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11051303 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000117 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.010812 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11050011 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1292 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11051303 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12774911500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1169857 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 896683 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782385 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782385 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoop_filter.tot_requests 3908932 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1937717 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1177209 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1032614 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 905103 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 794006 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 794006 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1177209 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5880147 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5880147 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192245056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 192245056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 3870887 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 1971215 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1971215 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3870887 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 1971215 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8039396000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 9856075000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu
|
|||
sim_ticks 832017490500 # Number of ticks simulated
|
||||
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1008264 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1086251 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 543126570 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 256604 # Number of bytes of host memory used
|
||||
host_seconds 1531.90 # Real time elapsed on the host
|
||||
host_inst_rate 1176831 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1267857 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 633929666 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260476 # Number of bytes of host memory used
|
||||
host_seconds 1312.48 # Real time elapsed on the host
|
||||
sim_insts 1544563042 # Number of instructions simulated
|
||||
sim_ops 1664032434 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032481 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution
|
||||
|
|
@ -239,14 +245,14 @@ system.membus.pkt_size::total 8383808423 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2172060895 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,45 +1,45 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.377030 # Number of seconds simulated
|
||||
sim_ticks 2377029670500 # Number of ticks simulated
|
||||
final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.379922 # Number of seconds simulated
|
||||
sim_ticks 2379921906500 # Number of ticks simulated
|
||||
final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 744525 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 802329 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1150119113 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266344 # Number of bytes of host memory used
|
||||
host_seconds 2066.77 # Real time elapsed on the host
|
||||
host_inst_rate 802178 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 864460 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1240688848 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272000 # Number of bytes of host memory used
|
||||
host_seconds 1918.23 # Real time elapsed on the host
|
||||
sim_insts 1538759602 # Number of instructions simulated
|
||||
sim_ops 1658228915 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 4754059341 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 4759843813 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1538759602 # Number of instructions committed
|
||||
|
|
@ -182,7 +182,7 @@ system.cpu.num_mem_refs 633153380 # nu
|
|||
system.cpu.num_load_insts 458306334 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462427 # Number of branches fetched
|
||||
|
|
@ -221,26 +221,26 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032481 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
|
||||
|
|
@ -263,14 +263,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n
|
|||
system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -295,22 +295,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526
|
|||
system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3681379 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3667054 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
|
||||
|
|
@ -321,16 +321,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235
|
|||
system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -341,26 +341,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
|
|
@ -368,7 +368,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 606
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits
|
||||
|
|
@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n
|
|||
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 638 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
|
||||
|
|
@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -419,90 +419,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638
|
|||
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1919027 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1938113 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000309 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000710 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.965759 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.966777 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 744 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27370 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3667054 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1095453 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1095453 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6049829 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6049829 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7145282 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7145304 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7145282 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7145304 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 793696 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 793696 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176258 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1176258 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1969954 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1970570 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 37281000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71177285500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 71177285500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 37281000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 119233240500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 37281000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 119233240500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3667054 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3667054 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -517,101 +517,101 @@ system.cpu.l2cache.demand_accesses::total 9115874 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420134 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.420134 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162779 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162779 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.216117 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.216169 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.216117 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.216169 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1021127 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1031709 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176258 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176258 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1969954 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1970570 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1969954 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1970570 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40081714000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40081714000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 31121000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 31121000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59414705500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59414705500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31121000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99496419500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 99527540500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution
|
||||
|
|
@ -620,53 +620,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919027 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 65352128 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1938113 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1169580 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 897056 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782134 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782134 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1176874 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 905404 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 793696 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 793696 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 3869897 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 1970570 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1970570 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3869897 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 1970570 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8048170000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 9852850000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu
|
|||
sim_ticks 2846007227500 # Number of ticks simulated
|
||||
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 953043 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1484927 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 901693633 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259304 # Number of bytes of host memory used
|
||||
host_seconds 3156.29 # Real time elapsed on the host
|
||||
host_inst_rate 913315 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1423027 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 864105629 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264708 # Number of bytes of host memory used
|
||||
host_seconds 3293.59 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
|
||||
|
|
@ -122,14 +128,14 @@ system.membus.pkt_size::total 38674388193 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 5690945966 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,51 +1,51 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.895948 # Number of seconds simulated
|
||||
sim_ticks 5895947852500 # Number of ticks simulated
|
||||
final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 5.898831 # Number of seconds simulated
|
||||
sim_ticks 5898831348500 # Number of ticks simulated
|
||||
final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 735742 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1146353 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1442081312 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269296 # Number of bytes of host memory used
|
||||
host_seconds 4088.50 # Real time elapsed on the host
|
||||
host_inst_rate 637466 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 993229 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1250066735 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275724 # Number of bytes of host memory used
|
||||
host_seconds 4718.81 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 11791895705 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 11797662697 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 3008081022 # Number of instructions committed
|
||||
|
|
@ -66,7 +66,7 @@ system.cpu.num_mem_refs 1677713084 # nu
|
|||
system.cpu.num_load_insts 1239184746 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528338 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 248500691 # Number of branches fetched
|
||||
|
|
@ -105,26 +105,26 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
|
||||
|
|
@ -141,14 +141,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n
|
|||
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -165,22 +165,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432
|
|||
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3682716 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3669049 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
|
||||
|
|
@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677
|
|||
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -205,31 +205,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits
|
||||
|
|
@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n
|
|||
system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 675 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses
|
||||
|
|
@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -280,86 +280,86 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675
|
|||
system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41853500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 41853500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41853500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1919169 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 1938075 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1095863 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1095863 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046986 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6046986 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7142849 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7142849 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7142849 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7142849 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 793964 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 793964 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1175864 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1175864 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1969828 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1970503 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -374,101 +374,101 @@ system.cpu.l2cache.demand_accesses::total 9113352 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1022289 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1032938 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution
|
||||
|
|
@ -477,55 +477,61 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919169 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 65426496 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1938075 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 1176539 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 904164 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 793964 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 793964 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 3870249 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 1970503 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3870249 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 1970503 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.053345 # Number of seconds simulated
|
||||
sim_ticks 53344764500 # Number of ticks simulated
|
||||
final_tick 53344764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.053349 # Number of seconds simulated
|
||||
sim_ticks 53349450500 # Number of ticks simulated
|
||||
final_tick 53349450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 260335 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 260335 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 151110624 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253412 # Number of bytes of host memory used
|
||||
host_seconds 353.02 # Real time elapsed on the host
|
||||
host_inst_rate 273465 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 273465 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 158745564 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258296 # Number of bytes of host memory used
|
||||
host_seconds 336.07 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 340608 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 202880 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 3803185 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2581847 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6385031 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3803185 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3803185 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3803185 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2581847 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6385031 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 3802851 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2581620 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6384471 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 3802851 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 3802851 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 3802851 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2581620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6384471 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 5322 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 53344677500 # Total gap between requests
|
||||
system.physmem.totGap 53349362500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -92,8 +92,8 @@ system.physmem.writePktSize::4 0 # Wr
|
|||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 4932 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 989 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 343.749242 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 211.692592 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 325.528362 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 314 31.75% 31.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 216 21.84% 53.59% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 88 8.90% 62.49% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 117 11.83% 74.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 52 5.26% 79.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 40 4.04% 83.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 29 2.93% 86.55% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 21 2.12% 88.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 112 11.32% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 989 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 40222250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 140009750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 345.743381 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 213.338865 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 326.606559 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 303 30.86% 30.86% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 220 22.40% 53.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 94 9.57% 62.83% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 105 10.69% 73.52% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 62 6.31% 79.84% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 36 3.67% 83.50% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 29 2.95% 86.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 22 2.24% 88.70% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 111 11.30% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 40016750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 139804250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7557.73 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7519.12 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26307.73 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.39 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 26269.12 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.38 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.39 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.38 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
||||
|
|
@ -217,49 +217,49 @@ system.physmem.busUtilRead 0.05 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 4331 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 4333 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 10023426.81 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3538080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1930500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 20022600 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 10024307.12 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.42 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3462480 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1889250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 1791514845 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 30434811000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 35735961585 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.917071 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 50627942250 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 1795262310 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 30431523750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 35736125550 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.920144 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 50622338000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1781260000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 934855250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 940274500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3938760 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2149125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 21411000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 3923640 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2140875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 21247200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1835182260 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 30396506250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 35743331955 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.055238 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 50563679500 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 1822659075 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 30407483250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 35741598600 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.022916 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 50582866250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1781260000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 998933000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 980601250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 11450644 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8210940 # Number of conditional branches predicted
|
||||
system.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 11450641 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8210938 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 765018 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 6085193 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5320740 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 6085190 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5320739 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 87.437490 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1176675 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 87.437516 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1176674 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits.
|
||||
|
|
@ -270,22 +270,22 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20415220 # DTB read hits
|
||||
system.cpu.dtb.read_hits 20415218 # DTB read hits
|
||||
system.cpu.dtb.read_misses 43383 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20458603 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 20458601 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6579912 # DTB write hits
|
||||
system.cpu.dtb.write_misses 276 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6580188 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26995132 # DTB hits
|
||||
system.cpu.dtb.data_hits 26995130 # DTB hits
|
||||
system.cpu.dtb.data_misses 43659 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 27038791 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 22968620 # ITB hits
|
||||
system.cpu.dtb.data_accesses 27038789 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 22968614 # ITB hits
|
||||
system.cpu.itb.fetch_misses 90 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 22968710 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 22968704 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 389 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 106689529 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 106698901 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903089 # Number of instructions committed
|
||||
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2191325 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2191321 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.160892 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.861407 # IPC: instructions per cycle
|
||||
system.cpu.cpi 1.160994 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.861331 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction
|
||||
|
|
@ -344,16 +344,16 @@ system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 91903089 # Class of committed instruction
|
||||
system.cpu.tickCycles 103791732 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 2897797 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 103791781 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 2907120 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1447.584436 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26572205 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1447.584590 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26572201 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11910.445988 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11910.444195 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584436 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584590 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.353414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id
|
||||
|
|
@ -363,41 +363,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 228
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 53153443 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53153443 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20074007 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20074007 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6498198 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6498198 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26572205 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26572205 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26572205 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26572205 # number of overall hits
|
||||
system.cpu.dcache.tags.tag_accesses 53153439 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53153439 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 20074005 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20074005 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 6498196 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6498196 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26572201 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26572201 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26572201 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26572201 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2905 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2905 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3401 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3401 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3401 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3401 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 37448500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 37448500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 219755500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 219755500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 257204000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 257204000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 257204000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 257204000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20074503 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20074503 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2907 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2907 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 3403 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 3403 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3403 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3403 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 37687000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 37687000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 223750000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 223750000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 261437000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 261437000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 261437000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 261437000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20074501 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20074501 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26575606 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26575606 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26575606 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26575606 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 26575604 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26575604 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 26575604 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26575604 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses
|
||||
|
|
@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000128
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75501.008065 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75501.008065 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75647.332186 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75647.332186 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 75625.992355 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 75625.992355 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 76825.448134 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 76825.448134 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu
|
|||
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1162 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1162 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1170 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1170 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1170 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1170 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1164 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1164 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1172 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1172 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1172 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1172 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses
|
||||
|
|
@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2231
|
|||
system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36544000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36544000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137282000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 137282000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 173826000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 173826000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 173826000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 173826000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36777500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 36777500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 140150000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 140150000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176927500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 176927500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176927500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 176927500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -454,24 +454,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74885.245902 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74885.245902 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78761.904762 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78761.904762 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 13865 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1642.714068 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22952789 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1642.701416 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22952783 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1449.955085 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1449.954706 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1642.714068 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.802106 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.802106 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1642.701416 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.802100 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.802100 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
|
|
@ -479,45 +479,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 45953070 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45953070 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22952789 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22952789 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22952789 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22952789 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22952789 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22952789 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 45953058 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45953058 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22952783 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22952783 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22952783 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22952783 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22952783 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22952783 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15831 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 409090000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 409090000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 409090000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 409090000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 409090000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 409090000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22968620 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22968620 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22968620 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22968620 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22968620 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22968620 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 411111000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 411111000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 411111000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 411111000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 411111000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 411111000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22968614 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22968614 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22968614 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22968614 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22968614 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22968614 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25841.071316 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25841.071316 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25841.071316 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25841.071316 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 25968.732234 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 25968.732234 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -532,48 +532,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15831
|
|||
system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393260000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 393260000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393260000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 393260000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393260000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 393260000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 395281000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 395281000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 395281000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 395281000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 395281000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 395281000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24841.134483 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24841.134483 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2482.282304 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 26642 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3671 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.257423 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 3575.444447 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.761061 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.458659 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 362.062585 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000542 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.450993 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.993454 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064162 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011049 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.075753 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3671 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2509 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.112030 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 262078 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 262078 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.044952 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.109114 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits
|
||||
|
|
@ -602,18 +600,18 @@ system.cpu.l2cache.demand_misses::total 5322 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5322 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 134394000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 134394000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236583500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 236583500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35249500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35249500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 236583500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 169643500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 406227000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 236583500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 169643500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 406227000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 137262000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 137262000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 238604500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 238604500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35483000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35483000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 238604500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 172745000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 411349500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 238604500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 172745000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 411349500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -642,18 +640,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294668 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78272.568433 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78272.568433 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74632.018927 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74632.018927 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76329.763247 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76329.763247 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -672,18 +670,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5322
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 117224000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 117224000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204883500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204883500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30899500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30899500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204883500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148123500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 353007000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204883500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148123500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 353007000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120092000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120092000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 206904500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 206904500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31133000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31133000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206904500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151225000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 358129500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206904500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151225000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 358129500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -696,25 +694,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68272.568433 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68272.568433 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64632.018927 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64632.018927 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution
|
||||
|
|
@ -748,7 +746,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23745000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 3605 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1717 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1717 # Transaction distribution
|
||||
|
|
@ -769,9 +773,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5322 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 6419500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 6421000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 28179750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 28180500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.132486 # Number of seconds simulated
|
||||
sim_ticks 132485848500 # Number of ticks simulated
|
||||
final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.132488 # Number of seconds simulated
|
||||
sim_ticks 132487590500 # Number of ticks simulated
|
||||
final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 159309 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 167937 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 122483807 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270152 # Number of bytes of host memory used
|
||||
host_seconds 1081.66 # Real time elapsed on the host
|
||||
host_inst_rate 200266 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 211113 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 153975874 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275560 # Number of bytes of host memory used
|
||||
host_seconds 860.44 # Real time elapsed on the host
|
||||
sim_insts 172317810 # Number of instructions simulated
|
||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 247552 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 3868 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 132485754500 # Total gap between requests
|
||||
system.physmem.totGap 132487495500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 30291250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 28381250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -217,56 +217,56 @@ system.physmem.busUtilRead 0.01 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 2934 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 2936 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 34251746.25 # Average gap between requests
|
||||
system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem.avgGap 34252196.35 # Average gap between requests
|
||||
system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.835850 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.825360 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.833625 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.826698 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 49693791 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted
|
||||
system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 49693795 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 264971697 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 264975181 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 172317810 # Number of instructions committed
|
||||
system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.537692 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.650325 # IPC: instructions per cycle
|
||||
system.cpu.cpi 1.537712 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.650317 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
|
||||
|
|
@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 181650743 # Class of committed instruction
|
||||
system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 42 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
|
|
@ -451,11 +451,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
|
||||
|
|
@ -464,10 +464,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407
|
|||
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40710586 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40710587 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses
|
||||
|
|
@ -478,16 +478,16 @@ system.cpu.dcache.demand_misses::cpu.data 2402 # n
|
|||
system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2403 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
|
||||
|
|
@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407
|
|||
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses
|
||||
|
|
@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000059
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810
|
|||
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -564,26 +564,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 2864 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id
|
||||
|
|
@ -593,7 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1069
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits
|
||||
|
|
@ -606,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 4664 # n
|
|||
system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 4664 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses
|
||||
|
|
@ -624,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066
|
|||
system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4664
|
|||
system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 76244 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits
|
||||
|
|
@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 3885 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3885 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84399500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 84399500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 162646500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 162646500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50260000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 50260000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 162646500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 134659500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 297306000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 162646500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.600000 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3869
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution
|
||||
|
|
@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 6994999 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 2777 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1091 # Transaction distribution
|
||||
|
|
@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3868 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,53 +4,53 @@ sim_seconds 1.869358 # Nu
|
|||
sim_ticks 1869357999000 # Number of ticks simulated
|
||||
final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1359256 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1359255 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 39091338244 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 332080 # Number of bytes of host memory used
|
||||
host_seconds 47.82 # Real time elapsed on the host
|
||||
host_inst_rate 1685575 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1685575 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48476092750 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 336716 # Number of bytes of host memory used
|
||||
host_seconds 38.56 # Real time elapsed on the host
|
||||
sim_insts 64999904 # Number of instructions simulated
|
||||
sim_ops 64999904 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 66535744 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 766400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 68167296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 68167488 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7836352 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7836352 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 7837888 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7837888 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1039621 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 11975 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1065114 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 122443 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 122443 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 1065117 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 122467 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 122467 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 35592763 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 35592831 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 409980 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 36465619 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 36465721 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4192002 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4192002 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4192002 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4192823 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4192823 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4192823 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 35592763 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 35592831 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 409980 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40657620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40658545 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
|
|
@ -264,28 +264,28 @@ system.cpu0.dcache.tags.data_accesses 51822038 # Nu
|
|||
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 4360096 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 4360096 # number of WriteReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 10428970 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 10428970 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 10428970 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 10428970 # number of overall hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132871 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 132871 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 10428981 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 10428981 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 10428981 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 10428981 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 236527 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 236527 # number of WriteReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 1796603 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 1796603 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 1796603 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 1796603 # number of overall misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6899 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 6899 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 1796592 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 1796592 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 1796592 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 1796592 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -300,24 +300,24 @@ system.cpu0.dcache.overall_accesses::cpu0.data 12225573
|
|||
system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051459 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::total 0.051459 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051457 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::total 0.051457 # miss rate for WriteReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049517 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049517 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049360 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049360 # miss rate for StoreCondReq accesses
|
||||
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses
|
||||
system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses
|
||||
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses
|
||||
system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses
|
||||
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.writebacks::writebacks 633126 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 633126 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::writebacks 633925 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 633925 # number of writebacks
|
||||
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu0.icache.tags.replacements 618292 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use
|
||||
|
|
@ -560,28 +560,28 @@ system.cpu1.dcache.tags.data_accesses 20020608 # Nu
|
|||
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 1954643 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::total 1954643 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 1954647 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::total 1954647 # number of WriteReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 4587331 # number of overall hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64211 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 64211 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 4587335 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 4587335 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 4587335 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 4587335 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 78317 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::total 78317 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 78313 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::total 78313 # number of WriteReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 219202 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 219202 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 219202 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 219202 # number of overall misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7304 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 7304 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 219198 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 219198 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 219198 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 219198 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -596,24 +596,24 @@ system.cpu1.dcache.overall_accesses::cpu1.data 4806533
|
|||
system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038522 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::total 0.038522 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.045605 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045605 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.045605 # miss rate for overall accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102132 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102132 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045604 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.045604 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045604 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.045604 # miss rate for overall accesses
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.writebacks::writebacks 144536 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 144536 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::writebacks 144832 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 144832 # number of writebacks
|
||||
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu1.icache.tags.replacements 380647 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use
|
||||
|
|
@ -755,242 +755,240 @@ system.iocache.avg_blocked_cycles::no_targets nan
|
|||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.l2c.tags.replacements 999922 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65337.856710 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4259780 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 3.999899 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 55997.404382 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4860.296070 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4190.275138 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 175.171519 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 114.709600 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy
|
||||
system.l2c.tags.replacements 999962 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65520.418446 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4560628 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1065470 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 4.280391 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 618103500 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 304.654016 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4865.757369 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 58473.870947 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 175.171504 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 1700.964609 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.004649 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.074246 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.892240 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.001750 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.996977 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 6047 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 46377199 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46377199 # Number of data accesses
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.025955 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.999762 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65508 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 2411 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 2462 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 9328 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 50633 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.999573 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 46077158 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46077158 # Number of data accesses
|
||||
system.l2c.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.l2c.WritebackDirty_hits::writebacks 777662 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 777662 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 778757 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 778757 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168081 # number of ReadExReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 3102 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 2744 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 5846 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 1187 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 2308 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 111978 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 56627 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168605 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626716 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 129010 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755726 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626251 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 128790 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755041 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738192 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738229 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185615 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910407 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185417 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910246 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738192 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738229 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 185615 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910407 # number of overall hits
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 1165 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 1095 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 2260 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 113871 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 11066 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 124937 # number of ReadExReq misses
|
||||
system.l2c.overall_hits::cpu1.data 185417 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910246 # number of overall hits
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 4 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 2 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 113307 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 11044 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 124351 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 926616 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1036 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 927652 # number of ReadSharedReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1040486 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1039923 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1066093 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12080 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1065509 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1040486 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1039923 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12101 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066093 # number of overall misses
|
||||
system.l2c.WritebackDirty_accesses::writebacks 777662 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 777662 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.overall_misses::cpu1.data 12080 # number of overall misses
|
||||
system.l2c.overall_misses::total 1065509 # number of overall misses
|
||||
system.l2c.WritebackDirty_accesses::writebacks 778757 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 778757 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 225347 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 3106 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 2746 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 5852 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu0.data 1187 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 1122 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 225285 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 293018 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 292956 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.data 1553331 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.data 130045 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::total 1683376 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu0.data 1552867 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.data 129826 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::total 1682693 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 1778678 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 1778152 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 197716 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2976500 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 197497 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2975755 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 1778678 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 1778152 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 197716 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2976500 # number of overall (read+write) accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505314 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.426380 # miss rate for ReadExReq accesses
|
||||
system.l2c.overall_accesses::cpu1.data 197497 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2975755 # number of overall (read+write) accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001288 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000728 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.001025 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.000891 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.000433 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.502950 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.163201 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.424470 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596534 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551065 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596713 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007980 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551290 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584977 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584834 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.061165 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.358063 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584977 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584834 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.061165 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358063 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.writebacks::writebacks 80923 # number of writebacks
|
||||
system.l2c.writebacks::total 80923 # number of writebacks
|
||||
system.membus.snoop_filter.tot_requests 2182334 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1076327 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2c.writebacks::writebacks 80947 # number of writebacks
|
||||
system.l2c.writebacks::total 80947 # number of writebacks
|
||||
system.membus.snoop_filter.tot_requests 2174394 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1068384 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948784 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948786 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 122443 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 918012 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 125244 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 124222 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 122467 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 918018 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 13880 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 11895 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 135 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 125245 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 124223 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941337 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172393 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3216467 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3156480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3200554 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3341628 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3325715 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73364992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73451154 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76119890 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 2204371 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.000517 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.022725 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2196431 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.000519 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.022766 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2203232 99.95% 99.95% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2195292 99.95% 99.95% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2204371 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2196431 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.toL2Bus.snoop_filter.tot_requests 6035847 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 3018700 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_requests 6035809 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 3018662 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 1621 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 1531 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 777662 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 778757 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1205462 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1204367 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 19598 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 14203 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 33801 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450127 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450061 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 9133705 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684375 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 9133629 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766459 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155817595 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 307065106 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1000943 # Total snoops (count)
|
||||
system.toL2Bus.snoopTraffic 5195776 # Total snoop traffic (bytes)
|
||||
system.toL2Bus.snoop_fanout::samples 7058663 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.106768 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.309067 # Request fanout histogram
|
||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23377367 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 307135186 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1000983 # Total snoops (count)
|
||||
system.toL2Bus.snoopTraffic 5197312 # Total snoop traffic (bytes)
|
||||
system.toL2Bus.snoop_fanout::samples 7058665 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.106769 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.309069 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6305567 89.33% 89.33% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 752556 10.66% 99.99% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6305559 89.33% 89.33% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 752566 10.66% 99.99% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7058663 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7058665 # Request fanout histogram
|
||||
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.829332 # Number of seconds simulated
|
||||
sim_ticks 1829331993500 # Number of ticks simulated
|
||||
final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1829332003500 # Number of ticks simulated
|
||||
final_tick 1829332003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1344723 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1344722 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 40972777153 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 326188 # Number of bytes of host memory used
|
||||
host_seconds 44.65 # Real time elapsed on the host
|
||||
host_inst_rate 1751464 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1751464 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 53365900898 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 334408 # Number of bytes of host memory used
|
||||
host_seconds 34.28 # Real time elapsed on the host
|
||||
sim_insts 60038469 # Number of instructions simulated
|
||||
sim_ops 60038469 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
|
|
@ -41,8 +41,8 @@ system.physmem.bw_total::cpu.inst 464922 # To
|
|||
system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -78,15 +78,15 @@ system.cpu.itb.data_acv 0 # DT
|
|||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numPwrStateTransitions 12714 # Number of power state transitions
|
||||
system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 283043475.573698 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 441371914.604153 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 283043477.146767 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 441371906.848107 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307374222 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 3658670345 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307384222 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 3658670365 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
|
|
@ -102,11 +102,11 @@ system.cpu.kern.ipl_good::21 243 0.16% 49.46% # nu
|
|||
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811929137500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829331796000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
|
|
@ -172,7 +172,7 @@ system.cpu.kern.mode_switch_good::idle 0.081545 # fr
|
|||
system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801033409500 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.cpu.committedInsts 60038469 # Number of instructions committed
|
||||
system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
|
||||
|
|
@ -189,8 +189,8 @@ system.cpu.num_fp_register_writes 166520 # nu
|
|||
system.cpu.num_mem_refs 16115703 # number of memory refs
|
||||
system.cpu.num_load_insts 9747509 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368194 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 3598621022.088898 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049342.911102 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064428 # Number of branches fetched
|
||||
|
|
@ -229,7 +229,7 @@ system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Cl
|
|||
system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050307 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 2042707 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks.
|
||||
|
|
@ -246,11 +246,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3
|
|||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807772 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807772 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848209 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848209 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
||||
|
|
@ -259,10 +259,10 @@ system.cpu.dcache.demand_hits::cpu.data 13655981 # nu
|
|||
system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655981 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721711 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721711 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
|
||||
|
|
@ -297,14 +297,14 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833475 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 919603 # number of replacements
|
||||
system.cpu.dcache.writebacks::writebacks 833476 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833476 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 919606 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 59130074 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920118 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.263577 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||
|
|
@ -314,21 +314,21 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59130077 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920230 # number of overall misses
|
||||
system.cpu.icache.tags.tag_accesses 60970540 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 60970540 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59130074 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59130074 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59130074 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59130074 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59130074 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59130074 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920233 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920233 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920233 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920233 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920233 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920233 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses
|
||||
|
|
@ -347,96 +347,96 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 919603 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 919603 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.writebacks::writebacks 919606 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 919606 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 992419 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057582 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.311847 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 65520.104765 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4865571 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057941 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.599095 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.327000 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.506195 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3046 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54052 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 48753652 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48753652 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 833475 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 833475 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 919351 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 919351 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187286 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187286 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906923 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 906923 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906923 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998516 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905439 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906923 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998516 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905439 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117060 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117060 # number of ReadExReq misses
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 264.552906 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732213 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819646 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.004037 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074047 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.921674 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 606 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6629 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55077 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 48449706 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48449706 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 833476 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 919354 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 919354 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187293 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906926 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 906926 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811229 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 811229 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906926 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998522 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905448 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906926 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998522 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905448 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117054 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117054 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044704 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1057993 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044698 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1057987 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044704 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1057993 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 833475 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 833475 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 919351 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 919351 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044698 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1057987 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 833476 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 919354 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 919354 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920212 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 920212 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920215 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 920215 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738873 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1738873 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920215 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920215 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384628 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384628 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384607 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384607 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511303 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357016 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357014 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511303 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357016 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357014 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -445,45 +445,45 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74359 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962435 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 833475 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 919603 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 919606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1209231 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 920230 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760063 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 920233 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738873 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760072 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8923286 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154606 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 301903918 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1075988 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 7415744 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7018629 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154670 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 301904366 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 993364 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 4774656 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6936011 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000753 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.027431 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7013406 99.93% 99.93% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6930788 99.92% 99.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5223 0.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7018629 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6936011 # Request fanout histogram
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -496,7 +496,7 @@ system.disk2.dma_read_txs 0 # Nu
|
|||
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
||||
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
||||
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
|
||||
|
|
@ -527,13 +527,13 @@ system.iobus.pkt_size_system.bridge.master::total 46126
|
|||
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.replacements 41686 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
||||
|
|
@ -542,7 +542,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16
|
|||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 375534 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 375534 # Number of data accesses
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
||||
|
|
@ -575,26 +575,32 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
|
|||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 1034179 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 7184 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948291 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917188 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 147 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 147 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 133 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 133 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116925 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 116925 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107383 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141427 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107355 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141399 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266565 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266537 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -603,22 +609,22 @@ system.membus.pkt_size_system.iocache.mem_side::total 2667904
|
|||
system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 2149812 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2149798 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.000494 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.022210 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2149812 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2148737 99.95% 99.95% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 1061 0.05% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2149812 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_fanout::total 2149798 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
@ -650,28 +656,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to
|
|||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,58 +1,58 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.783855 # Number of seconds simulated
|
||||
sim_ticks 2783855034000 # Number of ticks simulated
|
||||
final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 2783854715000 # Number of ticks simulated
|
||||
final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 850769 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1035674 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 16588804734 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 576284 # Number of bytes of host memory used
|
||||
host_seconds 167.82 # Real time elapsed on the host
|
||||
sim_insts 142771937 # Number of instructions simulated
|
||||
sim_ops 173801895 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 492350 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 599357 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 9600186649 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 585092 # Number of bytes of host memory used
|
||||
host_seconds 289.98 # Real time elapsed on the host
|
||||
sim_insts 142771202 # Number of instructions simulated
|
||||
sim_ops 173801044 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
|
|
@ -65,9 +65,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7
|
|||
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -75,7 +75,7 @@ system.cf0.dma_write_full_pages 540 # Nu
|
|||
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -105,7 +105,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 10028 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
|
||||
|
|
@ -126,9 +126,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864
|
|||
system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 31526014 # DTB read hits
|
||||
system.cpu.dtb.read_hits 31525882 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8580 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23124171 # DTB write hits
|
||||
system.cpu.dtb.write_hits 23124079 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1448 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
|
|
@ -139,13 +139,13 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 31534594 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125619 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 31534462 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125527 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 54650185 # DTB hits
|
||||
system.cpu.dtb.hits 54649961 # DTB hits
|
||||
system.cpu.dtb.misses 10028 # DTB misses
|
||||
system.cpu.dtb.accesses 54660213 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.accesses 54659989 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 4762 # Table walker walks requested
|
||||
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
|
||||
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
|
||||
|
|
@ -194,7 +194,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
|||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 147038452 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 147037694 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -211,14 +211,14 @@ system.cpu.itb.domain_faults 0 # Nu
|
|||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 147043214 # ITB inst accesses
|
||||
system.cpu.itb.hits 147038452 # DTB hits
|
||||
system.cpu.itb.inst_accesses 147042456 # ITB inst accesses
|
||||
system.cpu.itb.hits 147037694 # DTB hits
|
||||
system.cpu.itb.misses 4762 # DTB misses
|
||||
system.cpu.itb.accesses 147043214 # DTB accesses
|
||||
system.cpu.itb.accesses 147042456 # DTB accesses
|
||||
system.cpu.numPwrStateTransitions 6160 # Number of power state transitions
|
||||
system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
|
||||
|
|
@ -228,38 +228,38 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00%
|
|||
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 5567713149 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 5567712511 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142771937 # Number of instructions committed
|
||||
system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 142771202 # Number of instructions committed
|
||||
system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 16873976 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153161571 # number of integer instructions
|
||||
system.cpu.num_func_calls 16873864 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153160791 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11484 # number of float instructions
|
||||
system.cpu.num_int_register_reads 285044694 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55938751 # number of memory refs
|
||||
system.cpu.num_load_insts 31855653 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083098 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55938510 # number of memory refs
|
||||
system.cpu.num_load_insts 31855508 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083002 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
||||
system.cpu.Branches 36397005 # Number of branches fetched
|
||||
system.cpu.Branches 36396820 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
||||
|
|
@ -287,17 +287,17 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177218735 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 819389 # number of replacements
|
||||
system.cpu.op_class::total 177217860 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 819387 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
|
|
@ -307,51 +307,51 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52863792 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52863571 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814061 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814058 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
|
||||
|
|
@ -372,14 +372,14 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682017 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1698989 # number of replacements
|
||||
system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682138 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1698988 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
||||
|
|
@ -390,27 +390,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145342052 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699507 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145341295 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699506 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
|
||||
|
|
@ -423,73 +423,70 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698989 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 109914 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy
|
||||
system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698988 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 109912 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses
|
||||
|
|
@ -497,116 +494,116 @@ system.cpu.l2cache.ReadSharedReq_misses::total 15568
|
|||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 181652 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 179992 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101950 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101949 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182976 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 115326 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
|
|
@ -657,14 +654,14 @@ system.iobus.pkt_size_system.bridge.master::total 159061
|
|||
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.replacements 36430 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor
|
||||
system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
|
|
@ -672,7 +669,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16
|
|||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 328176 # Number of data accesses
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
|
|
@ -705,65 +702,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
|
|||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8204 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8203 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 145998 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 145998 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 145996 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 145996 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 434823 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 430442 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 434823 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_fanout::total 430442 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
@ -795,28 +798,28 @@ system.realview.ethernet.totalRxOrn 0 # to
|
|||
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,58 +1,58 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.783855 # Number of seconds simulated
|
||||
sim_ticks 2783855034000 # Number of ticks simulated
|
||||
final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 2783854715000 # Number of ticks simulated
|
||||
final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 704767 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 857940 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 13741971204 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 573692 # Number of bytes of host memory used
|
||||
host_seconds 202.58 # Real time elapsed on the host
|
||||
sim_insts 142771937 # Number of instructions simulated
|
||||
sim_ops 173801895 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 812904 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 989581 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15850589349 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 583016 # Number of bytes of host memory used
|
||||
host_seconds 175.63 # Real time elapsed on the host
|
||||
sim_insts 142771202 # Number of instructions simulated
|
||||
sim_ops 173801044 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
|
|
@ -65,9 +65,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7
|
|||
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -75,7 +75,7 @@ system.cf0.dma_write_full_pages 540 # Nu
|
|||
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -105,7 +105,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 10028 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
|
||||
|
|
@ -126,9 +126,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864
|
|||
system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 31526014 # DTB read hits
|
||||
system.cpu.dtb.read_hits 31525882 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8580 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23124171 # DTB write hits
|
||||
system.cpu.dtb.write_hits 23124079 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1448 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
|
|
@ -139,13 +139,13 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 31534594 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125619 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 31534462 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125527 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 54650185 # DTB hits
|
||||
system.cpu.dtb.hits 54649961 # DTB hits
|
||||
system.cpu.dtb.misses 10028 # DTB misses
|
||||
system.cpu.dtb.accesses 54660213 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.accesses 54659989 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 4762 # Table walker walks requested
|
||||
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
|
||||
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
|
||||
|
|
@ -194,7 +194,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
|||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 147038452 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 147037694 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -211,14 +211,14 @@ system.cpu.itb.domain_faults 0 # Nu
|
|||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 147043214 # ITB inst accesses
|
||||
system.cpu.itb.hits 147038452 # DTB hits
|
||||
system.cpu.itb.inst_accesses 147042456 # ITB inst accesses
|
||||
system.cpu.itb.hits 147037694 # DTB hits
|
||||
system.cpu.itb.misses 4762 # DTB misses
|
||||
system.cpu.itb.accesses 147043214 # DTB accesses
|
||||
system.cpu.itb.accesses 147042456 # DTB accesses
|
||||
system.cpu.numPwrStateTransitions 6160 # Number of power state transitions
|
||||
system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
|
||||
|
|
@ -228,38 +228,38 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00%
|
|||
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state
|
||||
system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 5567713149 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 5567712511 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142771937 # Number of instructions committed
|
||||
system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 142771202 # Number of instructions committed
|
||||
system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 16873976 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153161571 # number of integer instructions
|
||||
system.cpu.num_func_calls 16873864 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153160791 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11484 # number of float instructions
|
||||
system.cpu.num_int_register_reads 285044694 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55938751 # number of memory refs
|
||||
system.cpu.num_load_insts 31855653 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083098 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55938510 # number of memory refs
|
||||
system.cpu.num_load_insts 31855508 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083002 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
||||
system.cpu.Branches 36397005 # Number of branches fetched
|
||||
system.cpu.Branches 36396820 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
||||
|
|
@ -287,17 +287,17 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177218735 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 819389 # number of replacements
|
||||
system.cpu.op_class::total 177217860 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 819387 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
|
|
@ -307,51 +307,51 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52863792 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52863571 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814061 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814058 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
|
||||
|
|
@ -372,14 +372,14 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682017 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1698989 # number of replacements
|
||||
system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682138 # number of writebacks
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1698988 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
||||
|
|
@ -390,27 +390,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145342052 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699507 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145341295 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699506 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
|
||||
|
|
@ -423,73 +423,70 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
|
|||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698989 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 109914 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy
|
||||
system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698988 # number of writebacks
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 109912 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses
|
||||
|
|
@ -497,116 +494,116 @@ system.cpu.l2cache.ReadSharedReq_misses::total 15568
|
|||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 181652 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 179992 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101950 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101949 # number of writebacks
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182976 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 115326 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram
|
||||
system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
|
|
@ -657,14 +654,14 @@ system.iobus.pkt_size_system.bridge.master::total 159061
|
|||
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.tags.replacements 36430 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor
|
||||
system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
|
|
@ -672,7 +669,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16
|
|||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 328176 # Number of data accesses
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
||||
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
|
||||
|
|
@ -705,65 +702,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
|
|||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
||||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 40087 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8204 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8203 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 145998 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 145998 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 145996 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 145996 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 434823 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 430442 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 434823 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_fanout::total 430442 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
||||
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
||||
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
||||
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
||||
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
@ -795,28 +798,28 @@ system.realview.ethernet.totalRxOrn 0 # to
|
|||
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
||||
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
||||
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
||||
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu
|
|||
sim_ticks 2783854715000 # Number of ticks simulated
|
||||
final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 842839 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1026021 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 16434267548 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 578044 # Number of bytes of host memory used
|
||||
host_seconds 169.39 # Real time elapsed on the host
|
||||
host_inst_rate 808320 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 984000 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15761202711 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 583272 # Number of bytes of host memory used
|
||||
host_seconds 176.63 # Real time elapsed on the host
|
||||
sim_insts 142771202 # Number of instructions simulated
|
||||
sim_ops 173801044 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -333,8 +333,8 @@ system.cpu0.dcache.ReadReq_hits::cpu0.data 15303909 #
|
|||
system.cpu0.dcache.ReadReq_hits::cpu1.data 14824794 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 30128703 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 10894549 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu1.data 11445217 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 22339766 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu1.data 11445218 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits
|
||||
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185793 # number of SoftPFReq hits
|
||||
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209252 # number of SoftPFReq hits
|
||||
system.cpu0.dcache.SoftPFReq_hits::total 395045 # number of SoftPFReq hits
|
||||
|
|
@ -345,17 +345,17 @@ system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236699
|
|||
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223423 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 26198458 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::cpu1.data 26270011 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 52468469 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::cpu1.data 26270012 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 52468470 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 26384251 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::cpu1.data 26479263 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 52863514 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::cpu1.data 26479264 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 52863515 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 197405 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::cpu1.data 198906 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 396311 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 137584 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu1.data 164079 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu1.data 164078 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
|
||||
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54365 # number of SoftPFReq misses
|
||||
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61704 # number of SoftPFReq misses
|
||||
system.cpu0.dcache.SoftPFReq_misses::total 116069 # number of SoftPFReq misses
|
||||
|
|
@ -365,11 +365,11 @@ system.cpu0.dcache.LoadLockedReq_misses::total 8628
|
|||
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 334989 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::cpu1.data 362985 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 697974 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::cpu1.data 362984 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 697973 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 389354 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::cpu1.data 424689 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 814043 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::cpu1.data 424688 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 814042 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 15501314 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu1.data 15023700 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -417,8 +417,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu
|
|||
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 682241 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::writebacks 682362 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 682362 # number of writebacks
|
||||
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu0.icache.tags.replacements 1698988 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
|
|
@ -801,92 +801,89 @@ system.iocache.writebacks::writebacks 36190 # nu
|
|||
system.iocache.writebacks::total 36190 # number of writebacks
|
||||
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.l2c.tags.replacements 109906 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65155.312233 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4527993 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 175187 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 25.846627 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 48764.096462 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924324 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 5146.050132 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4729.659368 # Average occupied blocks per requestor
|
||||
system.l2c.tags.tagsinuse 65246.862245 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4830712 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 175332 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 27.551799 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.924122 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999998 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 5146.889475 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 28219.641429 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978701 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 4022.536499 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 2489.066650 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.078522 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.072169 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 4023.136773 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 27850.291746 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000075 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.078535 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.430598 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.061379 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.037980 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 40604073 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 40604073 # Number of data accesses
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.061388 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.424962 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65419 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 55478 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.998215 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 40281361 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 40281361 # Number of data accesses
|
||||
system.l2c.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 4711 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 2279 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 4978 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 2423 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 14391 # number of ReadReq hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 682241 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 682241 # number of WritebackDirty hits
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 3721 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 1793 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 3957 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 1933 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 11404 # number of ReadReq hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 682362 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 682362 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 1666989 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 72332 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 78800 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 151132 # number of ReadExReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 1257 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 1489 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 2746 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 73078 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 79712 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 152790 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 833454 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 847737 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 246679 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 258766 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.dtb.walker 4711 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 2279 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.dtb.walker 3721 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 1793 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 833454 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 319011 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 4978 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 2423 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 319757 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 3957 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 1933 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 847737 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 337566 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2352159 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 4711 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 2279 # number of overall hits
|
||||
system.l2c.demand_hits::cpu1.data 338478 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 2350830 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 3721 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 1793 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 833454 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 319011 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 4978 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 2423 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 319757 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 3957 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 1933 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 847737 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 337566 # number of overall hits
|
||||
system.l2c.overall_hits::total 2352159 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 338478 # number of overall hits
|
||||
system.l2c.overall_hits::total 2350830 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 8 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 1250 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 1478 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 9 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 63990 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 83785 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 147775 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 63244 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 82873 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 146117 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 10757 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 7541 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses
|
||||
|
|
@ -896,31 +893,31 @@ system.l2c.ReadSharedReq_misses::total 15563 # nu
|
|||
system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 10757 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 73743 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 72997 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 7541 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 89595 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 181644 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 88683 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 179986 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 10757 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 73743 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 72997 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 7541 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 89595 # number of overall misses
|
||||
system.l2c.overall_misses::total 181644 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4716 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 2280 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 4980 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 2423 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 14399 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 682241 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 682241 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.overall_misses::cpu1.data 88683 # number of overall misses
|
||||
system.l2c.overall_misses::total 179986 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3726 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 1794 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 3959 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 1933 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 11412 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 682362 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 682362 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 1493 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 136322 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -932,58 +929,58 @@ system.l2c.ReadCleanReq_accesses::total 1699489 # nu
|
|||
system.l2c.ReadSharedReq_accesses::cpu0.data 256432 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::cpu1.data 264576 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.dtb.walker 4716 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.itb.walker 2280 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.dtb.walker 3726 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.itb.walker 1794 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.inst 844211 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 392754 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.dtb.walker 4980 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.itb.walker 2423 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.dtb.walker 3959 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.itb.walker 1933 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 855278 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2533803 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 4716 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 2280 # number of overall (read+write) accesses
|
||||
system.l2c.demand_accesses::total 2530816 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.dtb.walker 3726 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.itb.walker 1794 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 844211 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 392754 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.dtb.walker 4980 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.itb.walker 2423 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.dtb.walker 3959 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.itb.walker 1933 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 855278 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 2533803 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000439 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.000556 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990491 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989290 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.l2c.overall_accesses::total 2530816 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000557 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.000701 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.003962 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002679 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.469403 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.515330 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.494385 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.463931 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.509721 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012742 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008817 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038033 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021960 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000439 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000557 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.012742 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.187759 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.185859 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.008817 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.209745 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.071688 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001060 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000439 # miss rate for overall accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.207610 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.071118 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000557 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.012742 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.187759 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000402 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.185859 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.008817 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.209745 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.071688 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.207610 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.071118 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -992,8 +989,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
|
|||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.writebacks::writebacks 101943 # number of writebacks
|
||||
system.l2c.writebacks::total 101943 # number of writebacks
|
||||
system.membus.snoop_filter.tot_requests 367174 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 155394 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.tot_requests 362797 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 151017 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -1005,9 +1002,9 @@ system.membus.trans_dist::WriteReq 27546 # Tr
|
|||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8203 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 145996 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 145996 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 34109 # Transaction distribution
|
||||
|
|
@ -1016,11 +1013,11 @@ system.membus.trans_dist::InvalidateResp 36224 # Tr
|
|||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506560 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 613920 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 497806 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 605166 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723278 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 714524 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
@ -1031,17 +1028,17 @@ system.membus.pkt_size_system.iocache.mem_side::total 2331520
|
|||
system.membus.pkt_size::total 20586073 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 434807 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.012707 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.112006 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 430430 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.112567 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 429282 98.73% 98.73% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 5525 1.27% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 424905 98.72% 98.72% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 434807 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 430430 # Request fanout histogram
|
||||
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -1111,8 +1108,8 @@ system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000
|
|||
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
|
||||
system.toL2Bus.snoop_filter.tot_requests 5060295 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 2540893 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_requests 5060294 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 2540892 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -1122,38 +1119,38 @@ system.toL2Bus.trans_dist::ReadReq 71240 # Tr
|
|||
system.toL2Bus.trans_dist::ReadResp 2291754 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 682241 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 682362 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 137146 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 137025 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116044 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581955 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581953 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20756 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41550 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 7760305 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 7760303 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96320737 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96328481 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83100 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 313985053 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 313992797 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 115320 # Total snoops (count)
|
||||
system.toL2Bus.snoopTraffic 6540928 # Total snoop traffic (bytes)
|
||||
system.toL2Bus.snoop_fanout::samples 5254492 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::samples 5254491 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.018785 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.135764 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 5155788 98.12% 98.12% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 5155787 98.12% 98.12% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 98704 1.88% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 5254492 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 5254491 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu
|
|||
sim_ticks 200409271000 # Number of ticks simulated
|
||||
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 17965406 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 17965399 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 6873925677 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 491760 # Number of bytes of host memory used
|
||||
host_seconds 29.16 # Real time elapsed on the host
|
||||
host_inst_rate 11448115 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 11448111 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4380279881 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 499724 # Number of bytes of host memory used
|
||||
host_seconds 45.75 # Real time elapsed on the host
|
||||
sim_insts 523780905 # Number of instructions simulated
|
||||
sim_ops 523780905 # Number of ops (including micro ops) simulated
|
||||
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -235,6 +235,12 @@ drivesys.iobus.pkt_size_drivesys.bridge.master::total 948604
|
|||
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
drivesys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
drivesys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
drivesys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
drivesys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
drivesys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
drivesys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
|
||||
drivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution
|
||||
drivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution
|
||||
|
|
@ -262,14 +268,14 @@ drivesys.membus.pkt_size::total 175319714 # Cu
|
|||
drivesys.membus.snoops 0 # Total snoops (count)
|
||||
drivesys.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
drivesys.membus.snoop_fanout::samples 27247410 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::mean 0.786764 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::stdev 0.409593 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::0 5810141 21.32% 21.32% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::1 21437269 78.68% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::0 27247410 100.00% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::total 27247410 # Request fanout histogram
|
||||
drivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
|
||||
drivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -587,6 +593,12 @@ testsys.iobus.pkt_size_testsys.bridge.master::total 942152
|
|||
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
testsys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
testsys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
testsys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
testsys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
testsys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
testsys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
|
||||
testsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution
|
||||
testsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution
|
||||
|
|
@ -614,14 +626,14 @@ testsys.membus.pkt_size::total 183678150 # Cu
|
|||
testsys.membus.snoops 0 # Total snoops (count)
|
||||
testsys.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
testsys.membus.snoop_fanout::samples 28885173 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::mean 0.784032 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::stdev 0.411493 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::0 6238286 21.60% 21.60% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::1 22646887 78.40% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::0 28885173 100.00% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::total 28885173 # Request fanout histogram
|
||||
testsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
|
||||
testsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -709,11 +721,11 @@ sim_seconds 0.000407 # Nu
|
|||
sim_ticks 407341500 # Number of ticks simulated
|
||||
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 9196187733 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 9194395313 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7148094141 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 491760 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 5887840528 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 5886957075 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4576964640 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 499724 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 523853183 # Number of instructions simulated
|
||||
sim_ops 523853183 # Number of ops (including micro ops) simulated
|
||||
drivesys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -919,6 +931,12 @@ drivesys.iobus.pkt_size_drivesys.bridge.master::total 1928
|
|||
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes)
|
||||
drivesys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
drivesys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
drivesys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
drivesys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
drivesys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
drivesys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
drivesys.membus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
|
||||
drivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution
|
||||
drivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution
|
||||
|
|
@ -946,14 +964,14 @@ drivesys.membus.pkt_size::total 340576 # Cu
|
|||
drivesys.membus.snoops 0 # Total snoops (count)
|
||||
drivesys.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
drivesys.membus.snoop_fanout::samples 52004 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::mean 0.788439 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::stdev 0.408419 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::0 11002 21.16% 21.16% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::1 41002 78.84% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::0 52004 100.00% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
drivesys.membus.snoop_fanout::total 52004 # Request fanout histogram
|
||||
drivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
|
||||
drivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
|
||||
|
|
@ -1218,6 +1236,12 @@ testsys.iobus.pkt_size_testsys.bridge.master::total 1928
|
|||
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes)
|
||||
testsys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
testsys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
testsys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
testsys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
testsys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
testsys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
testsys.membus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
|
||||
testsys.membus.trans_dist::ReadReq 47876 # Transaction distribution
|
||||
testsys.membus.trans_dist::ReadResp 48080 # Transaction distribution
|
||||
|
|
@ -1245,14 +1269,14 @@ testsys.membus.pkt_size::total 340448 # Cu
|
|||
testsys.membus.snoops 0 # Total snoops (count)
|
||||
testsys.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
testsys.membus.snoop_fanout::samples 51975 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::mean 0.788360 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::stdev 0.408475 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::0 11000 21.16% 21.16% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::1 40975 78.84% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::0 51975 100.00% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
testsys.membus.snoop_fanout::total 51975 # Request fanout histogram
|
||||
testsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
|
||||
testsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000038 # Number of seconds simulated
|
||||
sim_ticks 37822000 # Number of ticks simulated
|
||||
final_tick 37822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 38282000 # Number of ticks simulated
|
||||
final_tick 38282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 100508 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 100471 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 592356577 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249008 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 159466 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 159415 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 951356890 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253388 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 6413 # Number of instructions simulated
|
||||
sim_ops 6413 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 34048 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 23232 # Nu
|
|||
system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 532 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 614245677 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 285971128 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 900216805 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 614245677 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 614245677 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 614245677 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 285971128 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 900216805 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 606864845 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 282534873 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 889399718 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 606864845 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 606864845 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 606864845 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 282534873 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 889399718 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 532 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 37718000 # Total gap between requests
|
||||
system.physmem.totGap 38177000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -187,71 +187,71 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 385.560976 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 252.880176 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 333.081835 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 17 20.73% 20.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 21 25.61% 46.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 9 10.98% 57.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 11 13.41% 70.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 4 4.88% 75.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3 3.66% 79.27% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 3 3.66% 82.93% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 5 6.10% 89.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 10.98% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3215000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13190000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 377.831325 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 247.256857 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 329.629090 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 20 24.10% 45.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 11 13.25% 59.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 11 13.25% 72.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 3 3.61% 75.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 4 4.82% 80.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 3 3.61% 84.34% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 4 4.82% 89.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 10.84% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 3252000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 13227000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6043.23 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6112.78 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24793.23 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 900.22 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 24862.78 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 889.40 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 900.22 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 889.40 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.03 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 6.95 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 6.95 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 438 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 437 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 70898.50 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 71761.28 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.14 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 2020200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 366250 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 21270690 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 184500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 25871865 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 823.813565 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 196750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 30182000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1505400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 20148930 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 1168500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 25398495 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 808.740487 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 1794750 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 20078820 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 1230000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 25385970 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 808.341665 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 2146500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 28584000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 28481000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 2005 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1239 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
|
||||
|
|
@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 75644 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 76564 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6413 # Number of instructions committed
|
||||
system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 11.795416 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.084779 # IPC: instructions per cycle
|
||||
system.cpu.cpi 11.938874 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.083760 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction
|
||||
|
|
@ -345,24 +345,24 @@ system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 6413 # Class of committed instruction
|
||||
system.cpu.tickCycles 12651 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 62993 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.idleCycles 63913 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.701168 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.736314 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.701168 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025318 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025318 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.736314 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025326 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025326 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
|
||||
|
|
@ -379,14 +379,14 @@ system.cpu.dcache.demand_misses::cpu.data 221 # n
|
|||
system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 221 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7590000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7590000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9158000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9158000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 16748000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 16748000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 16748000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 16748000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7713000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 7713000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9281000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9281000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 16994000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 16994000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 16994000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 16994000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -403,14 +403,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099955
|
|||
system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79062.500000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 79062.500000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73264 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73264 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 75782.805430 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 75782.805430 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74248 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 74248 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 76895.927602 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 76895.927602 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -431,14 +431,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169
|
|||
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7494000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7494000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5379500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5379500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12873500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12873500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12873500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12873500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7617000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7617000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5452500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5452500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13069500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 13069500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13069500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 13069500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -447,31 +447,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78062.500000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78062.500000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73691.780822 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73691.780822 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 174.485780 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 174.445567 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 174.485780 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.085198 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.085198 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 174.445567 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.085178 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.085178 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5736 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits
|
||||
|
|
@ -484,12 +484,12 @@ system.cpu.icache.demand_misses::cpu.inst 364 # n
|
|||
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 364 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28087500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28087500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28087500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28087500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28087500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28087500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28460500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 28460500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 28460500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 28460500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 28460500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 28460500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses
|
||||
|
|
@ -502,12 +502,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.135517
|
|||
system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77163.461538 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 77163.461538 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 77163.461538 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 77163.461538 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 78188.186813 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 78188.186813 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -520,43 +520,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364
|
|||
system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27723500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 27723500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27723500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 27723500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27723500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 27723500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28096500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 28096500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28096500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 28096500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28096500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 28096500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76163.461538 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76163.461538 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 232.271171 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 278.242026 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.500375 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.770796 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005325 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007088 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.459359 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 103.782667 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005324 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.008491 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
@ -575,18 +575,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 532 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5270000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5270000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27166000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27166000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7348500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7348500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 27166000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12618500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 39784500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 27166000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12618500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 39784500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5343000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5343000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27539000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27539000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 27539000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 12814500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 40353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 27539000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 12814500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 40353500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -611,18 +611,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72191.780822 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72191.780822 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74837.465565 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74837.465565 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76546.875000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76546.875000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74782.894737 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74782.894737 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -641,18 +641,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4540000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4540000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23536000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23536000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6388500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6388500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23536000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10928500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 34464500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23536000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10928500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 34464500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4613000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23909000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23909000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23909000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11124500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 35033500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23909000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11124500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 35033500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -665,25 +665,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62191.780822 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62191.780822 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64837.465565 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64837.465565 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66546.875000 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66546.875000 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
|
|
@ -714,7 +714,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 546000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 459 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
|
|
@ -738,6 +744,6 @@ system.membus.snoop_fanout::total 532 # Re
|
|||
system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2826500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 3214500 # Number of ticks simulated
|
||||
final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1026789 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1024872 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 513643962 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238508 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 280584 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 280421 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 140703848 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 242116 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6413 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 7598 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 7598 # Transaction distribution
|
||||
|
|
@ -144,14 +150,14 @@ system.membus.pkt_size::total 41152 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 8463 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.757769 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.428459 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2050 24.22% 24.22% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 6413 75.78% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 8463 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 8463 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000036 # Number of seconds simulated
|
||||
sim_ticks 35682500 # Number of ticks simulated
|
||||
final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 36128500 # Number of ticks simulated
|
||||
final_tick 36128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 318235 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 317806 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1768975757 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248500 # Number of bytes of host memory used
|
||||
host_inst_rate 310790 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 310669 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1752338800 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252108 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 6403 # Number of instructions simulated
|
||||
sim_ops 6403 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 28544 # Number of bytes read from this memory
|
||||
|
|
@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
|||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_read::cpu.inst 492464398 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 297604384 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 790068782 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 492464398 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 492464398 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 492464398 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 297604384 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 790068782 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 71365 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 72257 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6403 # Number of instructions committed
|
||||
|
|
@ -85,7 +85,7 @@ system.cpu.num_mem_refs 2060 # nu
|
|||
system.cpu.num_load_insts 1192 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 71365 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 72257 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1056 # Number of branches fetched
|
||||
|
|
@ -124,23 +124,23 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6413 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.721081 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.721081 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025323 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
|
||||
|
|
@ -157,14 +157,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n
|
|||
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 168 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5985000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5985000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4599000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4599000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10584000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10584000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10584000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10584000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081951
|
|||
system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -203,14 +203,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4526000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4526000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10416000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10416000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10416000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10416000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -219,31 +219,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 127.170991 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.170991 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062095 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062095 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 13107 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits
|
||||
|
|
@ -256,12 +256,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n
|
|||
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 279 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17528500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17528500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17528500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17528500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17528500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses
|
||||
|
|
@ -274,12 +274,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043499
|
|||
system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62826.164875 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62826.164875 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62826.164875 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62826.164875 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -292,43 +292,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279
|
|||
system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17249500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17249500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17249500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17249500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17249500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17249500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.164875 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61826.164875 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 230.937880 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002242 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.167974 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 103.769906 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003881 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.007048 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013611 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
@ -347,18 +347,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4416500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4416500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5747500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5747500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 10164000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 26983500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 10164000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 26983500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -383,18 +383,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -413,18 +413,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3686500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3686500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4797500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4797500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8484000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 22523500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8484000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 22523500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -437,25 +437,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
|
|
@ -486,7 +486,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
|
|
@ -508,7 +514,7 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 446 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000020 # Number of seconds simulated
|
||||
sim_ticks 20329000 # Number of ticks simulated
|
||||
final_tick 20329000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000021 # Number of seconds simulated
|
||||
sim_ticks 20616000 # Number of ticks simulated
|
||||
final_tick 20616000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 113549 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 113428 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 891182571 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248724 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_inst_rate 91304 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 91266 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 727585147 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252076 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 2585 # Number of instructions simulated
|
||||
sim_ops 2585 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 19840 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu
|
|||
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 310 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 708347681 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 267598013 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 975945693 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 708347681 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 708347681 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 708347681 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 267598013 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 975945693 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 698486612 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 263872720 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 962359333 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 698486612 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 698486612 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 698486612 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 263872720 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 962359333 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 310 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 20241500 # Total gap between requests
|
||||
system.physmem.totGap 20527500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -188,70 +188,70 @@ system.physmem.wrQLenPdf::61 0 # Wh
|
|||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 281.421645 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 332.320856 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 424.585366 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 277.937119 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 331.553388 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 3 7.32% 56.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 5 12.20% 51.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 2 4.88% 56.10% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 6 14.63% 70.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1774250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7586750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 1590750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 7403250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 5723.39 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 5131.45 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24473.39 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 975.95 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 23881.45 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 962.36 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 975.95 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 962.36 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.62 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 7.52 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 260 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 65295.16 # Average gap between requests
|
||||
system.physmem.avgGap 66217.74 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 787800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 10557540 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 238500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 12729495 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 804.010422 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 825750 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 12758055 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 805.814306 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 727750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 14971750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1162200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 10490850 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 13284945 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 838.894625 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 10417320 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 361500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 13250265 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 836.902890 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 560000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14872250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 14766250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 794 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect
|
||||
|
|
@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 40658 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 41232 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2585 # Number of instructions committed
|
||||
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 15.728433 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.063579 # IPC: instructions per cycle
|
||||
system.cpu.cpi 15.950484 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.062694 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction
|
||||
|
|
@ -344,25 +344,25 @@ system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 2585 # Class of committed instruction
|
||||
system.cpu.tickCycles 5421 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 35237 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 5423 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 35809 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 48.302993 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 48.342284 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 48.302993 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011793 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011793 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 48.342284 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
|
||||
|
|
@ -379,14 +379,14 @@ system.cpu.dcache.demand_misses::cpu.data 102 # n
|
|||
system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 102 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4783500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4783500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3258000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8041500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8041500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8041500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8041500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4617500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4617500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3301000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3301000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7918500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7918500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7918500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7918500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -403,14 +403,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.128463
|
|||
system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81076.271186 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 81076.271186 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75767.441860 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75767.441860 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 78838.235294 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 78838.235294 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 78838.235294 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 78838.235294 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78262.711864 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 78262.711864 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76767.441860 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 76767.441860 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 77632.352941 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 77632.352941 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -433,14 +433,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
|
|||
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6671500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6671500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6671500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6671500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4487000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4487000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2044500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2044500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6531500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6531500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6531500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6531500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -449,31 +449,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80241.379310 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80241.379310 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78488.235294 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78488.235294 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78488.235294 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78488.235294 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77362.068966 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77362.068966 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75722.222222 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75722.222222 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 119.197826 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 119.307121 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 754 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.351111 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 119.197826 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.058202 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.058202 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 119.307121 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.058255 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.058255 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 2183 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2183 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 754 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 754 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 754 # number of demand (read+write) hits
|
||||
|
|
@ -486,12 +486,12 @@ system.cpu.icache.demand_misses::cpu.inst 225 # n
|
|||
system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 225 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17116000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17116000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17116000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17116000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17116000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17116000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17383000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17383000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17383000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17383000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses
|
||||
|
|
@ -504,12 +504,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229826
|
|||
system.cpu.icache.demand_miss_rate::total 0.229826 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.229826 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.229826 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76071.111111 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 76071.111111 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76071.111111 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 76071.111111 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76071.111111 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 76071.111111 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77257.777778 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 77257.777778 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 77257.777778 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 77257.777778 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -522,43 +522,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 225
|
|||
system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16891000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16891000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16891000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16891000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16891000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16891000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17158000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17158000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17158000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229826 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.229826 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.229826 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75071.111111 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75071.111111 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75071.111111 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75071.111111 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75071.111111 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75071.111111 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76257.777778 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 147.090026 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 167.807293 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 283 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.314039 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 27.775987 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003641 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004489 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 283 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008636 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.421716 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.385576 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003644 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001477 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005121 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses
|
||||
|
|
@ -571,18 +571,18 @@ system.cpu.l2cache.demand_misses::total 310 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 310 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16553500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16553500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4566000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4566000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16553500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6543000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23096500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16553500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6543000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23096500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2004000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2004000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16820500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16820500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4399000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4399000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16820500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6403000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23223500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16820500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6403000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23223500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -607,18 +607,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73571.111111 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73571.111111 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78724.137931 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78724.137931 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73571.111111 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76976.470588 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74504.838710 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73571.111111 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76976.470588 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74504.838710 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74222.222222 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74222.222222 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74757.777778 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74757.777778 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75844.827586 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75844.827586 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74914.516129 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74914.516129 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -637,18 +637,18 @@ system.cpu.l2cache.demand_mshr_misses::total 310
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14303500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14303500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3986000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3986000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14303500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5693000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19996500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14303500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5693000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19996500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1734000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1734000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14570500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14570500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3819000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3819000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14570500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5553000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20123500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14570500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5553000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20123500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -661,25 +661,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63571.111111 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63571.111111 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68724.137931 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68724.137931 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.111111 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66976.470588 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64504.838710 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.111111 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66976.470588 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64504.838710 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64222.222222 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64222.222222 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64757.777778 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64757.777778 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65844.827586 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65844.827586 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
|
|
@ -707,10 +707,16 @@ system.cpu.toL2Bus.snoop_fanout::total 310 # Re
|
|||
system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 283 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
|
|
@ -733,7 +739,7 @@ system.membus.snoop_fanout::max_value 0 # Re
|
|||
system.membus.snoop_fanout::total 310 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1648250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 8.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 8.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
sim_ticks 12409500 # Number of ticks simulated
|
||||
final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000013 # Number of seconds simulated
|
||||
sim_ticks 12542500 # Number of ticks simulated
|
||||
final_tick 12542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 95060 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 95002 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 493600045 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248984 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_inst_rate 60996 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 60977 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 320317516 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 253100 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu
|
|||
system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 964422418 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 438373827 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1402796245 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 964422418 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 964422418 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 964422418 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 438373827 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1402796245 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 954195735 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 433725334 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1387921068 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 954195735 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 954195735 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 954195735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 433725334 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1387921068 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 272 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 12313000 # Total gap between requests
|
||||
system.physmem.totGap 12445000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 81 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 157 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
||||
|
|
@ -188,9 +188,9 @@ system.physmem.wrQLenPdf::61 0 # Wh
|
|||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 398.222222 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 237.741650 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 358.174986 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation
|
||||
|
|
@ -201,37 +201,37 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By
|
|||
system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 1652750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 6752750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 1866000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 6966000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6076.29 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6860.29 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24826.29 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1402.80 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 25610.29 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1387.92 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1402.80 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1387.92 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 10.96 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 10.84 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 10.84 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
|
||||
system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 226 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 45268.38 # Average gap between requests
|
||||
system.physmem.avgGap 45753.68 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 592800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 6707115 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 833.570297 # Core power per rank (mW)
|
||||
system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 832.600901 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 260000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
|
|
@ -239,31 +239,31 @@ system.physmem_0.memoryStateTime::ACT 7777500 # Ti
|
|||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 6969270 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 866.151313 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 708000 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 5198400 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 267750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 6961155 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 865.142768 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 432500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 260000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 7367500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 1003 # Number of BP lookups
|
||||
system.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 1001 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 688 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 687 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 176 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 25.581395 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 25.618632 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions.
|
||||
system.cpu.branchPred.indirectLookups 101 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectLookups 100 # Number of indirect predictor lookups.
|
||||
system.cpu.branchPred.indirectHits 3 # Number of indirect target hits.
|
||||
system.cpu.branchPred.indirectMisses 98 # Number of indirect misses.
|
||||
system.cpu.branchPred.indirectMisses 97 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
|
|
@ -282,10 +282,10 @@ system.cpu.dtb.data_hits 1061 # DT
|
|||
system.cpu.dtb.data_misses 30 # DTB misses
|
||||
system.cpu.dtb.data_acv 1 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1091 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 878 # ITB hits
|
||||
system.cpu.itb.fetch_hits 877 # ITB hits
|
||||
system.cpu.itb.fetch_misses 32 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 910 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 909 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -299,53 +299,53 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 24820 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 25086 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 4371 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 6065 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1003 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 400 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 1173 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.icacheStallCycles 4377 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 6059 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 1001 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 399 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 1174 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 1146 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 878 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 6955 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.872035 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.274710 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.CacheLines 877 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 6970 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 0.869297 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 2.271813 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 5922 85.15% 85.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 27 0.39% 85.54% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 100 1.44% 86.97% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 87 1.25% 88.22% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 141 2.03% 90.25% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 81 1.16% 91.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 46 0.66% 92.08% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 76 1.09% 93.17% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 475 6.83% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 5938 85.19% 85.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 27 0.39% 85.58% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 100 1.43% 87.02% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 87 1.25% 88.26% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 141 2.02% 90.29% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 81 1.16% 91.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 45 0.65% 92.09% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 76 1.09% 93.19% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 475 6.81% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 6955 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.040411 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.244359 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5210 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 623 # Number of cycles decode is blocked
|
||||
system.cpu.fetch.rateDist::total 6970 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.039903 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.241529 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 5221 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 627 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 919 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 5285 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 327 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.IdleCycles 5296 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 881 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename
|
||||
|
|
@ -371,23 +371,23 @@ system.cpu.iq.iqSquashedInstsIssued 28 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 6955 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.540331 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.279888 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 6970 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 0.539168 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.278867 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 5508 79.19% 79.19% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 469 6.74% 85.94% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 342 4.92% 90.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 254 3.65% 94.51% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 193 2.77% 97.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 103 1.48% 98.76% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 56 0.81% 99.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 5524 79.25% 79.25% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 467 6.70% 85.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 343 4.92% 90.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 254 3.64% 94.52% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 193 2.77% 97.29% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 103 1.48% 98.77% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 56 0.80% 99.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 6955 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 6970 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available
|
||||
|
|
@ -457,10 +457,10 @@ system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 3758 # Type of FU issued
|
||||
system.cpu.iq.rate 0.151410 # Inst issue rate
|
||||
system.cpu.iq.rate 0.149805 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 61 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 14547 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 14562 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
||||
|
|
@ -480,7 +480,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 0 #
|
|||
system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 297 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewBlockCycles 299 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
|
||||
|
|
@ -501,33 +501,33 @@ system.cpu.iew.exec_nop 307 # nu
|
|||
system.cpu.iew.exec_refs 1093 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 599 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 366 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.146414 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.144862 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 3425 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1633 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2097 # num instructions consuming a value
|
||||
system.cpu.iew.wb_rate 0.137994 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.136530 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back
|
||||
system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 6540 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.393884 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.249766 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 6555 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 0.392982 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 1.248476 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 5669 86.68% 86.68% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 198 3.03% 89.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 318 4.86% 94.57% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 5684 86.71% 86.71% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 198 3.02% 89.73% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 318 4.85% 94.58% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 63 0.96% 97.34% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 63 0.96% 97.35% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 37 0.57% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 37 0.56% 98.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 6540 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 6555 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -574,38 +574,38 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 10930 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 10945 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 9815 # The number of ROB writes
|
||||
system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 17865 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 18116 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 10.397989 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 10.397989 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.096172 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.096172 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 10.509426 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 10.509426 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.095153 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.095153 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 4383 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2640 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
||||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 45.439304 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 45.419736 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 45.439304 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011094 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 45.419736 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011089 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011089 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
|
||||
|
|
@ -622,14 +622,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
|
|||
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 182 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6673500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6673500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5672000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5672000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12345500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12345500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12345500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12345500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6754500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6754500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5744000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5744000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12498500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12498500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12498500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -646,19 +646,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.198473
|
|||
system.cpu.dcache.demand_miss_rate::total 0.198473 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.198473 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.198473 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66074.257426 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66074.257426 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 67832.417582 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 67832.417582 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 256 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66876.237624 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66876.237624 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70913.580247 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 70913.580247 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 68673.076923 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 68673.076923 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 260 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
|
||||
|
|
@ -676,14 +676,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
|
|||
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4797000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4797000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6648000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6648000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6648000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6648000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4858000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4858000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6733000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6733000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6733000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6733000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.097913 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.097913 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -692,72 +692,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.092694
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.092694 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.092694 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78639.344262 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78639.344262 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79639.344262 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79639.344262 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78125 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78125 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 90.302659 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 624 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.342246 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 3.336898 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 90.399218 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.044140 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.044140 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 90.302659 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.044093 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.044093 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1943 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1943 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 625 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 625 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 625 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 625 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 625 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 625 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 1941 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1941 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 624 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 624 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 624 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 624 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 624 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 624 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 253 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18863999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18863999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18863999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18863999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18863999 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18863999 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 878 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 878 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 878 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 878 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 878 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 878 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288155 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.288155 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.288155 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.288155 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.288155 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.288155 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74561.260870 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 74561.260870 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 74561.260870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 74561.260870 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 19081499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 19081499 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 19081499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 19081499 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 19081499 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 19081499 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 877 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 877 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 877 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 877 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 877 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 877 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288483 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.288483 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.288483 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.288483 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.288483 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.288483 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75420.944664 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75420.944664 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75420.944664 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75420.944664 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
|
||||
|
|
@ -771,43 +771,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187
|
|||
system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14160499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14160499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14160499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14160499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14160499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14160499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.212984 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.212984 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.212984 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.593583 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.593583 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14560999 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14560999 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14560999 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14560999 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14560999 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14560999 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.213227 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.213227 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.213227 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77866.304813 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77866.304813 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 135.950101 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 272 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.557444 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.703859 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000876 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003640 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.459206 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 45.490894 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002761 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001388 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004149 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008301 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses
|
||||
|
|
@ -820,18 +820,18 @@ system.cpu.l2cache.demand_misses::total 272 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 272 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13879000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13879000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4705500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4705500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13879000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6519000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20398000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13879000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6519000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20398000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1837500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1837500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14279500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 14279500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4766500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4766500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14279500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6604000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20883500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14279500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6604000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20883500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -856,18 +856,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74219.251337 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74219.251337 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77139.344262 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77139.344262 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74992.647059 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74992.647059 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76562.500000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76562.500000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76360.962567 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76360.962567 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78139.344262 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78139.344262 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76777.573529 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76777.573529 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -886,18 +886,18 @@ system.cpu.l2cache.demand_mshr_misses::total 272
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12009000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12009000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4095500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4095500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12009000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5669000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17678000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12009000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5669000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17678000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1597500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1597500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12409500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12409500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4156500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4156500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12409500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5754000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18163500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12409500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5754000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18163500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -910,25 +910,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64219.251337 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64219.251337 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67139.344262 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67139.344262 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66562.500000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66562.500000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66360.962567 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66360.962567 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68139.344262 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68139.344262 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
|
||||
|
|
@ -956,10 +956,16 @@ system.cpu.toL2Bus.snoop_fanout::total 272 # Re
|
|||
system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 248 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
|
||||
|
|
@ -980,9 +986,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 272 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 11.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu
|
|||
sim_ticks 1297500 # Number of ticks simulated
|
||||
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 290379 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 289620 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 145475657 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238224 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 120967 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 120887 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 60829891 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241828 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 3000 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3000 # Transaction distribution
|
||||
|
|
@ -144,14 +150,14 @@ system.membus.pkt_size::total 15414 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 3294 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3294 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3294 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000018 # Number of seconds simulated
|
||||
sim_ticks 18239500 # Number of ticks simulated
|
||||
final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 18484500 # Number of ticks simulated
|
||||
final_tick 18484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 190443 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 190287 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1345802218 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247188 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 121029 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 120936 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 866943608 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250796 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 15680 # Number of bytes read from this memory
|
||||
|
|
@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 10432 # Nu
|
|||
system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 571945503 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 287727186 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 859672688 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 571945503 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 571945503 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_read::cpu.inst 564364738 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 283913549 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 848278287 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 564364738 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 564364738 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 564364738 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 283913549 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 848278287 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 36479 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 36969 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -85,7 +85,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 36479 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 36969 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -124,23 +124,23 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 47.258408 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.277997 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.258408 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011538 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011538 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
|
||||
|
|
@ -157,14 +157,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n
|
|||
system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 82 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1674000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1674000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 5084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 5084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 5084000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 5084000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1701000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1701000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 5166000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 5166000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 5166000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 5166000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656
|
|||
system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -203,14 +203,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82
|
|||
system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1647000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1647000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5002000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5002000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5002000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5002000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1674000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1674000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5084000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5084000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5084000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5084000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -219,31 +219,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 79.631047 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 79.677134 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.038905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.038905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 79.631047 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.038882 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.038882 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
|
||||
|
|
@ -256,12 +256,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n
|
|||
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 163 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10106500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 10106500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 10106500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 10106500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 10106500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 10106500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10269500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 10269500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 10269500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 10269500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 10269500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 10269500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
|
||||
|
|
@ -274,12 +274,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032
|
|||
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 63003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 63003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 63003.067485 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -292,43 +292,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163
|
|||
system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9943500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 9943500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9943500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 9943500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9943500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 9943500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10106500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 10106500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10106500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 10106500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10106500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 10106500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 127.028625 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 245 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.770969 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.878617 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002434 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000820 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003255 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.723638 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.304987 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001444 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003877 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 245 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007477 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses
|
||||
|
|
@ -341,18 +341,18 @@ system.cpu.l2cache.demand_misses::total 245 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 245 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1606500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1606500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9699000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 9699000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 9699000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4879000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 14578000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 9699000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4879000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 14578000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1633500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1633500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9862000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 9862000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 9862000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4961000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 14823000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 9862000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4961000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 14823000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -377,18 +377,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -407,18 +407,18 @@ system.cpu.l2cache.demand_mshr_misses::total 245
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1336500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1336500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8069000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8069000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8069000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4059000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12128000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8069000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4059000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12128000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1363500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1363500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8232000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8232000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4141000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12373000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8232000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4141000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12373000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -431,25 +431,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
|
|
@ -480,7 +480,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
|
||||
|
|
@ -504,6 +510,6 @@ system.membus.snoop_fanout::total 245 # Re
|
|||
system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.utilization 6.6 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000030 # Number of seconds simulated
|
||||
sim_ticks 30083500 # Number of ticks simulated
|
||||
final_tick 30083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 30404500 # Number of ticks simulated
|
||||
final_tick 30404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 80042 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 93682 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 522670316 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264608 # Number of bytes of host memory used
|
||||
host_inst_rate 82707 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 96800 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 545818868 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269760 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 4605 # Number of instructions simulated
|
||||
sim_ops 5391 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
|
||||
|
|
@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
|
|||
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 648860671 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 246779796 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 895640467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 648860671 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 648860671 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 648860671 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 246779796 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 895640467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 642010229 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 244174382 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 886184611 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 642010229 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 642010229 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 642010229 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 244174382 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 886184611 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 421 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 29992500 # Total gap between requests
|
||||
system.physmem.totGap 30312500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -187,71 +187,71 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 287.809352 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 328.256468 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 6 9.68% 69.35% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 3 4.84% 74.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2221000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10114750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 286.546821 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 324.800854 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 6 9.52% 71.43% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 2 3.17% 74.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 3 4.76% 79.37% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 2201250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 10095000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 5275.53 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 5228.62 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 24025.53 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 895.64 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 23978.62 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 886.18 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 895.64 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 886.18 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 7.00 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 7.00 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtil 6.92 # Data bus utilization in percentage
|
||||
system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 350 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 349 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 71241.09 # Average gap between requests
|
||||
system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
|
||||
system.physmem.avgGap 72001.19 # Average gap between requests
|
||||
system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1965600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 16103925 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 20064615 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 849.295873 # Core power per rank (mW)
|
||||
system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 848.348875 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 22845750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 15554160 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 527250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 18499935 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 783.273247 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 2015750 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 15442155 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 625500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 18486180 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 782.690871 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 2431750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 22043250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 21880250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.branchPred.lookups 1968 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1178 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
|
||||
|
|
@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 8 # Nu
|
|||
system.cpu.branchPred.indirectMisses 127 # Number of indirect misses.
|
||||
system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 60167 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 60809 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4605 # Number of instructions committed
|
||||
system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 13.065581 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.076537 # IPC: instructions per cycle
|
||||
system.cpu.cpi 13.204995 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.075729 # IPC: instructions per cycle
|
||||
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction
|
||||
system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction
|
||||
|
|
@ -432,25 +432,25 @@ system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Cl
|
|||
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.op_class_0::total 5391 # Class of committed instruction
|
||||
system.cpu.tickCycles 10719 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 49448 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.tickCycles 10721 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 50088 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 86.478936 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 86.589882 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.478936 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021113 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021113 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.589882 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021140 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021140 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
|
||||
|
|
@ -471,14 +471,14 @@ system.cpu.dcache.demand_misses::cpu.data 176 # n
|
|||
system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 176 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6690500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6690500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5002500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5002500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 11693000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 11693000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 11693000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 11693000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6774500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 6774500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5069500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5069500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 11844000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 11844000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 11844000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 11844000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -499,14 +499,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.084942
|
|||
system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66437.500000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66437.500000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 67295.454545 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 67295.454545 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -529,14 +529,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
|
|||
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6338000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6338000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3188000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3188000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9526000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9526000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9526000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9526000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3231000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3231000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9650000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9650000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9650000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9650000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -545,31 +545,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 4 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 161.834516 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 162.072741 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1963 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 6.096273 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 161.834516 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.079021 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.079021 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 162.072741 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.079137 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.079137 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4892 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4892 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1963 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1963 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1963 # number of demand (read+write) hits
|
||||
|
|
@ -582,12 +582,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n
|
|||
system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 322 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23678000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23678000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23678000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23678000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23678000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23678000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23964000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 23964000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 23964000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 23964000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 23964000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 23964000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2285 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2285 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2285 # number of demand (read+write) accesses
|
||||
|
|
@ -600,12 +600,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.140919
|
|||
system.cpu.icache.demand_miss_rate::total 0.140919 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.140919 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.140919 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 73534.161491 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 73534.161491 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 74422.360248 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 74422.360248 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -620,43 +620,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322
|
|||
system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23356000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23356000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23356000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23356000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23356000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23356000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23642000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 23642000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23642000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 23642000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23642000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 23642000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140919 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.140919 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.140919 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 195.879475 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 223.657376 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.111111 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.746810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 41.132665 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004722 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005978 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.975765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 68.681611 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002096 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006825 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
|
||||
|
|
@ -681,18 +681,18 @@ system.cpu.l2cache.demand_misses::total 429 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 429 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3123500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22677500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 22677500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5924000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5924000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22677500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9047500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 31725000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22677500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9047500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31725000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3166500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3166500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22963500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 22963500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6005000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 6005000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 22963500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9171500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32135000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22963500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9171500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32135000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -719,18 +719,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -755,18 +755,18 @@ system.cpu.l2cache.demand_mshr_misses::total 421
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2693500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2693500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19627500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19627500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4648000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4648000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19627500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7341500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26969000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19627500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7341500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26969000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2736500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2736500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19913500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19913500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4721000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4721000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19913500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7457500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 27371000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19913500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7457500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 27371000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -779,25 +779,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
|
|
@ -829,7 +829,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 483000 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 378 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
|
|
@ -852,7 +858,7 @@ system.membus.snoop_fanout::max_value 0 # Re
|
|||
system.membus.snoop_fanout::total 421 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2237750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 2695000 # Number of ticks simulated
|
||||
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 427598 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 499586 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 249859240 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254616 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 207093 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 242387 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 121392563 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259512 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -344,6 +344,12 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5391 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 5597 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 5608 # Transaction distribution
|
||||
|
|
@ -361,14 +367,14 @@ system.membus.pkt_size::total 26559 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 6532 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 2695000 # Number of ticks simulated
|
||||
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 433184 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 506134 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 253162440 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 254364 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 213878 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 250318 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 125362190 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 258232 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5391 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 5597 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 5608 # Transaction distribution
|
||||
|
|
@ -237,14 +243,14 @@ system.membus.pkt_size::total 26559 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 6532 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,19 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 28298500 # Number of ticks simulated
|
||||
final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000029 # Number of seconds simulated
|
||||
sim_ticks 28648500 # Number of ticks simulated
|
||||
final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 246555 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 287459 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1524533550 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264352 # Number of bytes of host memory used
|
||||
host_inst_rate 192730 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 224907 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1208517164 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267456 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 4566 # Number of instructions simulated
|
||||
sim_ops 5330 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
|
||||
|
|
@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 14400 # Nu
|
|||
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT
|
|||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 56597 # number of cpu cycles simulated
|
||||
system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.numCycles 57297 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4566 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 1965 # nu
|
|||
system.cpu.num_load_insts 1027 # Number of load instructions
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1008 # Number of branches fetched
|
||||
|
|
@ -214,23 +214,23 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5391 # Class of executed instruction
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
|
||||
|
|
@ -251,14 +251,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n
|
|||
system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 141 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -279,14 +279,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016
|
|||
system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -301,14 +301,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
|
|||
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -317,31 +317,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency
|
||||
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 9453 # Number of data accesses
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
|
||||
|
|
@ -354,12 +354,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n
|
|||
system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 241 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
|
||||
|
|
@ -372,12 +372,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323
|
|||
system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -392,43 +392,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241
|
|||
system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency
|
||||
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits
|
||||
|
|
@ -451,18 +451,18 @@ system.cpu.l2cache.demand_misses::total 350 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 350 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -487,18 +487,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -517,18 +517,18 @@ system.cpu.l2cache.demand_mshr_misses::total 350
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -541,25 +541,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
|
|
@ -591,7 +591,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La
|
|||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadResp 307 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
|
|
@ -613,8 +619,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 350 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.utilization 6.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
|
|||
sim_ticks 2820500 # Number of ticks simulated
|
||||
final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 890532 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 888973 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 443763917 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 236392 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 280567 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 280375 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 140096420 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 239748 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 5641 # Number of instructions simulated
|
||||
sim_ops 5641 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -116,6 +116,12 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5642 # Class of executed instruction
|
||||
system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.membus.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states
|
||||
system.membus.trans_dist::ReadReq 6777 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 6777 # Transaction distribution
|
||||
|
|
@ -130,14 +136,14 @@ system.membus.pkt_size::total 30470 # Cu
|
|||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
||||
system.membus.snoop_fanout::samples 7678 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0.734827 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.441454 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 2036 26.52% 26.52% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 5642 73.48% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 7678 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7678 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
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Reference in a new issue