1193 lines
138 KiB
Text
1193 lines
138 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.085052 # Number of seconds simulated
|
|
sim_ticks 85051506000 # Number of ticks simulated
|
|
final_tick 85051506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 137318 # Simulator instruction rate (inst/s)
|
|
host_op_rate 144756 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 67782320 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 272616 # Number of bytes of host memory used
|
|
host_seconds 1254.77 # Real time elapsed on the host
|
|
sim_insts 172303022 # Number of instructions simulated
|
|
sim_ops 181635954 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.physmem.bytes_read::cpu.inst 651584 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 192256 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 914880 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 651584 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 651584 # Number of instructions bytes read from this memory
|
|
system.physmem.num_reads::cpu.inst 10181 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 3004 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 14295 # Number of read requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 7661052 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 2260466 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.l2cache.prefetcher 835259 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 10756776 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 7661052 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 7661052 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 7661052 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 2260466 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.l2cache.prefetcher 835259 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 10756776 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 14295 # Number of read requests accepted
|
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
|
system.physmem.readBursts 14295 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 914880 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 914880 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 1374 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 495 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 5094 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 807 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 2274 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 424 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 384 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 621 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 270 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 230 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 354 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 348 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 319 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 267 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 239 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 795 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 85051447500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 14295 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 12841 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 1014 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 8758 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 104.242978 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 83.732821 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 121.093987 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 6415 73.25% 73.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 1879 21.45% 94.70% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 191 2.18% 96.88% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 97 1.11% 97.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 35 0.40% 98.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 31 0.35% 98.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 21 0.24% 98.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 17 0.19% 99.18% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 72 0.82% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 8758 # Bytes accessed per row activation
|
|
system.physmem.totQLat 205669486 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 473700736 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 71475000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 14387.51 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 33137.51 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 10.76 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 10.76 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.08 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 5530 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 38.68 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
|
system.physmem.avgGap 5949734.00 # Average gap between requests
|
|
system.physmem.pageHitRate 38.68 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 56571480 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 30867375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 89442600 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 17335593540 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 35823020250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 58890496125 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 692.426384 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 59484367239 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 2839980000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 22725351261 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 9616320 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 5247000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 21801000 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 4216606920 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 47330903250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 57139175370 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 671.834595 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 78723898183 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 2839980000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 3485604317 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.branchPred.lookups 85633597 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 68181299 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 5935035 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 39958046 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 38197568 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 95.594184 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 3683467 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 81914 # Number of incorrect RAS predictions.
|
|
system.cpu.branchPred.indirectLookups 681978 # Number of indirect predictor lookups.
|
|
system.cpu.branchPred.indirectHits 654112 # Number of indirect target hits.
|
|
system.cpu.branchPred.indirectMisses 27866 # Number of indirect misses.
|
|
system.cpu.branchPredindirectMispredicted 40296 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 400 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 170103013 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 5682904 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 347166765 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 85633597 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 42535147 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 157608501 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 11884039 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 2048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 3989 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 78333693 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 18018 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 169239484 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.146393 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.050401 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 17572638 10.38% 10.38% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 30072408 17.77% 28.15% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 31601234 18.67% 46.82% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 89993204 53.18% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 169239484 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.503422 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.040921 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 17519961 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 17356982 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 121861075 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 6734206 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 5767260 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 11064637 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 189821 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 304987544 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 27243895 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 5767260 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 37487022 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 8574296 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 598391 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 108353196 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 8459319 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 277412346 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 13179472 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 3059617 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 843440 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 2298708 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 38369 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.FullRegisterEvents 27077 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 481431446 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 1187749796 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 296450503 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 3005240 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 188454517 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 23636 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 23644 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13356506 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 33916395 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 14406588 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 2541453 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 1809916 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 263792468 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 45987 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 214404594 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 5189732 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 82202501 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 216956580 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 771 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 169239484 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.266871 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.018138 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 52525006 31.04% 31.04% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 35947009 21.24% 52.28% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 65510390 38.71% 90.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 13639375 8.06% 99.04% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 1570056 0.93% 99.97% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 47432 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 216 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 169239484 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 35663808 66.17% 66.17% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 153282 0.28% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 34308 0.06% 66.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 14056089 26.08% 92.66% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 3953676 7.34% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 166984371 77.88% 77.88% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 919276 0.43% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 460481 0.21% 78.77% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 206631 0.10% 78.87% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 31870339 14.86% 93.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 13371616 6.24% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 214404594 # Type of FU issued
|
|
system.cpu.iq.rate 1.260440 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 53899365 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.251391 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 653186184 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 344036614 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 204245973 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 3951585 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 2011286 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1806392 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 266171590 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 2132369 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1599233 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 6020251 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7425 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 7087 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1761954 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 25499 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 5767260 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 5621824 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 63176 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 263858489 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 33916395 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 14406588 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 23579 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 3874 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 56135 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 7087 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 3147809 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3246868 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 6394677 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 207120469 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 30635063 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 7284125 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 20034 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 43773548 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 44851099 # Number of branches executed
|
|
system.cpu.iew.exec_stores 13138485 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.217618 # Inst execution rate
|
|
system.cpu.iew.wb_sent 206362307 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 206052365 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 129396792 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 221653711 # num instructions consuming a value
|
|
system.cpu.iew.wb_rate 1.211339 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.583779 # average fanout of values written-back
|
|
system.cpu.commit.commitSquashedInsts 68665439 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 5760276 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 157944348 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.150091 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.652266 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 73354007 46.44% 46.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 41142542 26.05% 72.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 22532573 14.27% 86.76% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 9515365 6.02% 92.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 3551587 2.25% 95.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 2142504 1.36% 96.39% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1329210 0.84% 97.23% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 1010049 0.64% 97.87% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 3366511 2.13% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 157944348 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 172317410 # Number of instructions committed
|
|
system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 40540778 # Number of memory references committed
|
|
system.cpu.commit.loads 27896144 # Number of loads committed
|
|
system.cpu.commit.membars 22408 # Number of memory barriers committed
|
|
system.cpu.commit.branches 40300312 # Number of branches committed
|
|
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 143085667 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 3366511 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 404888417 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 511940612 # The number of ROB writes
|
|
system.cpu.timesIdled 9843 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 863529 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 172303022 # Number of Instructions Simulated
|
|
system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.987232 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.987232 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.012933 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.012933 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 218721236 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 114166498 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 2904044 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2441835 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 708181937 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 229500026 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 57441519 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 72593 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.410345 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 41032184 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 73105 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 561.277396 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 509673500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.410345 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.998848 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.998848 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 82362697 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 82362697 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 28645946 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 28645946 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 40987266 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 40987266 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 40987630 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 40987630 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 89269 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 89269 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 112236 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 112236 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 112352 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 112352 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1192862000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 1192862000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 244207999 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 244207999 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 2309000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 1437069999 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 1437069999 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 1437069999 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 1437069999 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 28735215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 28735215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 41099502 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 41099502 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 41099982 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 41099982 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003107 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003107 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8880.769231 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8880.769231 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 12804.002272 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 12790.782532 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 10626 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 868 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 12.241935 # average number of cycles each access was blocked
|
|
system.cpu.dcache.writebacks::writebacks 72593 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 72593 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24834 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 24834 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14410 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 14410 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 39244 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 39244 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 39244 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 39244 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64435 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 64435 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8557 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 8557 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 72992 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 72992 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 73105 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 73105 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 724757000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 724757000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85765499 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85765499 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 963000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 963000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 810522499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 810522499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 811485499 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 811485499 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.001779 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11247.877706 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11247.877706 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10022.846675 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10022.846675 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8522.123894 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8522.123894 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11104.264837 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11104.264837 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11100.273565 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11100.273565 # average overall mshr miss latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 53637 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.592571 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 78276090 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 54149 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 1445.568524 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 84288957500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.592571 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997251 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997251 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 156721475 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 156721475 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 78276090 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 78276090 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 78276090 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 78276090 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 78276090 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 78276090 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 57573 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 57573 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 57573 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 57573 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 57573 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 57573 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1245757924 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 1245757924 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1245757924 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 1245757924 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1245757924 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 1245757924 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 78333663 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 78333663 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 78333663 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 78333663 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 78333663 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 78333663 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21637.884494 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 21637.884494 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 21637.884494 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 21637.884494 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 76503 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 31 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 3201 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 23.899719 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 15.500000 # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 53637 # number of writebacks
|
|
system.cpu.icache.writebacks::total 53637 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3423 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 3423 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 3423 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 3423 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 3423 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 3423 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54150 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 54150 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 54150 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 54150 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 54150 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 54150 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1124811450 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1124811450 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1124811450 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1124811450 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1124811450 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1124811450 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20772.141274 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20772.141274 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20772.141274 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 20772.141274 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20772.141274 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 20772.141274 # average overall mshr miss latency
|
|
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 9324 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 9324 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 1388 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 1802.479960 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 99008 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 2827 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 35.022285 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 1726.446772 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 76.033188 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.105374 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004641 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.110015 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 121 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1125 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007385 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 4005348 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 4005348 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 64707 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 64707 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 51067 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 51067 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 8388 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 8388 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 43964 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 43964 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 61705 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 61705 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 43964 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 70093 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 114057 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 43964 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 70093 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 114057 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 236 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 236 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10186 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 10186 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2776 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 2776 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 10186 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3012 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 13198 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 10186 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3012 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 13198 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18599500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 18599500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 782334000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 782334000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 220076500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 220076500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 782334000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 238676000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1021010000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 782334000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 238676000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1021010000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 64707 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 64707 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 51067 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 51067 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 8624 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 8624 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54150 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 54150 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64481 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 64481 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 54150 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 73105 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 127255 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 54150 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 73105 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 127255 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027365 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.027365 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.188107 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.188107 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043051 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043051 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188107 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.041201 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.103713 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188107 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.041201 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.103713 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78811.440678 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78811.440678 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76804.830159 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76804.830159 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79278.278098 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79278.278098 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76804.830159 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79241.699867 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 77360.963782 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76804.830159 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79241.699867 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 77360.963782 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2014 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 2014 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 236 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 236 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10181 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10181 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2768 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2768 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10181 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3004 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 13185 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10181 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3004 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2014 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 15199 # number of overall MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 66910636 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17183500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17183500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 720935500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 720935500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 202978500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 202978500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 720935500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 220162000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 941097500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 720935500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 220162000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1008008136 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027365 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027365 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188015 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.042927 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.042927 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.103611 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188015 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041092 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.119437 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33222.758689 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72811.440678 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72811.440678 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940 # average overall mshr miss latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 253485 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 126250 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 904 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 903 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 118630 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 64707 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 61523 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 2352 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 8624 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 8624 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 54150 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 64481 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161936 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218803 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 380739 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6898304 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9324672 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 16222976 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 2352 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 129607 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.087812 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.283049 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 118227 91.22% 91.22% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 11379 8.78% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 129607 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 252972500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 81228989 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 109661492 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.snoop_filter.tot_requests 14295 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 10463 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadResp 14059 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 236 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 236 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 14059 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28590 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 28590 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 914880 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 914880 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 14295 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 14295 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 14295 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 18052130 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 77159307 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|