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stats: Update to reflect changes to PCI handling

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This commit is contained in:
Andreas Sandberg 2015-12-05 00:11:25 +00:00
parent 78275c9d2f
commit bbcbe028fe
155 changed files with 42507 additions and 43276 deletions
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69
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
View file

@ -15,10 +15,10 @@ boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
console=/scratch/nilay/GEM5/system/binaries/console
console=/work/gem5/dist/binaries/console
eventq_index=0
init_param=0
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
kernel=/work/gem5/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
@ -26,9 +26,10 @@ mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
pal=/work/gem5/dist/binaries/ts_osfpal
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
@ -146,6 +147,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -162,6 +164,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -569,6 +572,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -585,6 +589,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -618,6 +623,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -634,6 +640,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -649,12 +656,13 @@ size=4194304
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -662,6 +670,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@ -694,7 +709,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
image_file=/work/gem5/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -717,7 +732,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/work/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
@ -740,10 +755,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
@ -752,6 +766,7 @@ children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
@ -768,7 +783,8 @@ system=system
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
cpu_side=system.iobus.master[29]
writeback_clean=false
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@ -903,7 +919,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
image_file=/work/gem5/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@ -916,7 +932,7 @@ port=3456
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
eventq_index=0
intrctrl=system.intrctrl
system=system
@ -1029,12 +1045,12 @@ dma_write_delay=0
dma_write_factor=0
eventq_index=0
hardware_address=00:90:00:00:00:01
host=system.tsunami.pchip
intr_delay=10000000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
rx_fifo_size=524288
@ -1044,9 +1060,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.master[28]
dma=system.iobus.slave[2]
pio=system.iobus.master[27]
pio=system.iobus.master[26]
[system.tsunami.fake_OROM]
type=IsaFake
@ -1479,14 +1494,13 @@ config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
eventq_index=0
host=system.tsunami.pchip
io_shift=0
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
dma=system.iobus.slave[1]
pio=system.iobus.master[25]
@ -1506,25 +1520,20 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
clk_domain=system.clk_domain
conf_base=8804649402368
conf_device_bits=8
conf_size=16777216
eventq_index=0
pci_dma_base=0
pci_mem_base=8796093022208
pci_pio_base=8804615847936
pio_addr=8802535473152
pio_latency=100000
platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
eventq_index=0
pio_addr=0
pio_latency=30000
platform=system.tsunami
size=16777216
system=system
pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain

0
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr Normal file → Executable file
View file

13
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout Normal file → Executable file
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@ -1,12 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 29 2014 09:12:51
gem5 started Oct 29 2014 09:20:31
gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5.latest/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
gem5 compiled Dec 4 2015 10:28:58
gem5 started Dec 4 2015 10:29:11
gem5 executing on e104799-lin, pid 21295
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux
info: kernel located at: /work/gem5/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1883224346500 because m5_exit instruction encountered
Exiting @ tick 1906048606500 because m5_exit instruction encountered

398
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.906049 # Nu
sim_ticks 1906048606500 # Number of ticks simulated
final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 269376 # Simulator instruction rate (inst/s)
host_op_rate 269376 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9144869235 # Simulator tick rate (ticks/s)
host_mem_usage 376080 # Number of bytes of host memory used
host_seconds 208.43 # Real time elapsed on the host
host_inst_rate 268534 # Simulator instruction rate (inst/s)
host_op_rate 268534 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 9116285517 # Simulator tick rate (ticks/s)
host_mem_usage 332204 # Number of bytes of host memory used
host_seconds 209.08 # Real time elapsed on the host
sim_insts 56145568 # Number of instructions simulated
sim_ops 56145568 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -150,10 +150,10 @@ system.physmem.wrQLenPdf::13 1 # Wh
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5601 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6564 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6565 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see
@ -197,20 +197,20 @@ system.physmem.wrQLenPdf::60 53 # Wh
system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 64393 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 519.603311 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 318.318586 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 407.156918 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14830 23.03% 23.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11097 17.23% 40.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4950 7.69% 47.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3246 5.04% 52.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2531 3.93% 56.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1970 3.06% 59.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4174 6.48% 66.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1358 2.11% 68.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 20237 31.43% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64393 # Bytes accessed per row activation
system.physmem.bytesPerActivate::samples 64400 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 519.546832 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 318.268868 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 407.153797 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14837 23.04% 23.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11098 17.23% 40.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4944 7.68% 47.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3257 5.06% 53.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2526 3.92% 56.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1968 3.06% 59.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4176 6.48% 66.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1357 2.11% 68.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 20237 31.42% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64400 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes
@ -260,12 +260,12 @@ system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Wr
system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads
system.physmem.totQLat 2636864500 # Total ticks spent queuing
system.physmem.totMemAccLat 10223958250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 2637486000 # Total ticks spent queuing
system.physmem.totMemAccLat 10224579750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6516.49 # Average queueing delay per DRAM burst
system.physmem.avgQLat 6518.02 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25266.49 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 25268.02 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s
@ -276,39 +276,39 @@ system.physmem.busUtilRead 0.11 # Da
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing
system.physmem.readRowHits 362818 # Number of row buffer hits during reads
system.physmem.writeRowHits 95583 # Number of row buffer hits during writes
system.physmem.readRowHits 362820 # Number of row buffer hits during reads
system.physmem.writeRowHits 95574 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes
system.physmem.avgGap 3644923.65 # Average gap between requests
system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 237542760 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 129611625 # Energy for precharge commands per rank (pJ)
system.physmem_0.actEnergy 237573000 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 129628125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 67952834145 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1084018111500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1278788448510 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.912661 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1803102997000 # Time in different power states
system.physmem_0.actBackEnergy 67955758245 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1084015546500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1278788854350 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.912874 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1803098707000 # Time in different power states
system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 39293158000 # Time in different power states
system.physmem_0.memoryStateTime::ACT 39297448000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 249268320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 136009500 # Energy for precharge commands per rank (pJ)
system.physmem_1.actEnergy 249291000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 136021875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 68401366290 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1083624670500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1278869710170 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.955290 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1802449451000 # Time in different power states
system.physmem_1.actBackEnergy 68412640320 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1083614781000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1278871129755 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.956034 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1802432810250 # Time in different power states
system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 39946717750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 39963358500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 15009028 # Number of BP lookups
system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted
@ -375,10 +375,10 @@ system.cpu.kern.ipl_good::21 133 0.09% 49.41% # nu
system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1837271257000 96.39% 96.39% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::0 1837271633000 96.39% 96.39% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 67985555000 3.57% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 67985179000 3.57% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
@ -447,8 +447,8 @@ system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # nu
system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
system.cpu.tickCycles 84511190 # Number of cycles that the object actually ticked
system.cpu.idleCycles 137195507 # Total number of cycles that the object has spent stopped
system.cpu.tickCycles 84511215 # Number of cycles that the object actually ticked
system.cpu.idleCycles 137195482 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1395430 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks.
@ -487,16 +487,16 @@ system.cpu.dcache.demand_misses::cpu.data 1776836 # n
system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses
system.cpu.dcache.overall_misses::total 1776836 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974936500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 46974936500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956179000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 33956179000 # number of WriteReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974912500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 46974912500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956321000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 33956321000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 80931115500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 80931115500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 80931115500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 80931115500 # number of overall miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 80931233500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 80931233500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 80931233500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 80931233500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses)
@ -519,16 +519,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.117130
system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.646994 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.646994 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.177737 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.177737 # average WriteReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45547.881459 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.881459 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45547.881459 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 45547.947869 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 45547.947869 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -565,22 +565,22 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9624
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817588500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817588500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272399000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272399000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817391500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817391500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17272477000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 17272477000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 217466000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 217466000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089987500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 61089987500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089987500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 61089987500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1530266500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1530266500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61089868500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 61089868500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61089868500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 61089868500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529366500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529366500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162508500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162508500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3692775000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3692775000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691875000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691875000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119139 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119139 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049480 # mshr miss rate for WriteReq accesses
@ -591,28 +591,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090889
system.cpu.dcache.demand_mshr_miss_rate::total 0.090889 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090889 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.090889 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40785.018453 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40785.018453 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.508845 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.508845 # average WriteReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40784.835087 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40784.835087 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56741.765083 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56741.765083 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.919797 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.919797 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220690.294202 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220690.294202 # average ReadReq mshr uncacheable latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224699.553200 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224699.553200 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223020.594275 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223020.594275 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222966.239884 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222966.239884 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1460396 # number of replacements
system.cpu.icache.tags.tagsinuse 508.105648 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 18947784 # Total number of references to valid blocks.
system.cpu.icache.tags.total_refs 18947783 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1460907 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 12.969877 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 12.969876 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 50119711500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 508.105648 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.992394 # Average percentage of cache occupancy
@ -622,44 +622,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 103
system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 21869953 # Number of tag accesses
system.cpu.icache.tags.data_accesses 21869953 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 18947787 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 18947787 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 18947787 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 18947787 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 18947787 # number of overall hits
system.cpu.icache.overall_hits::total 18947787 # number of overall hits
system.cpu.icache.tags.tag_accesses 21869952 # Number of tag accesses
system.cpu.icache.tags.data_accesses 21869952 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 18947786 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 18947786 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 18947786 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 18947786 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 18947786 # number of overall hits
system.cpu.icache.overall_hits::total 18947786 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1461083 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1461083 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1461083 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1461083 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1461083 # number of overall misses
system.cpu.icache.overall_misses::total 1461083 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009217000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 21009217000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 21009217000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 21009217000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 21009217000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 21009217000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 20408870 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 20408870 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 20408870 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 20408870 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 20408870 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 20408870 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 21009954000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 21009954000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 21009954000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 21009954000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 21009954000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 21009954000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 20408869 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 20408869 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 20408869 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 20408869 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 20408869 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 20408869 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071591 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.071591 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.071591 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.071591 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.071591 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.071591 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.208436 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14379.208436 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14379.208436 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.208436 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14379.208436 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14379.712857 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14379.712857 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14379.712857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14379.712857 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14379.712857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -676,34 +676,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1461083
system.cpu.icache.demand_mshr_misses::total 1461083 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1461083 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1461083 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548134000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 19548134000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548134000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 19548134000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548134000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 19548134000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19548871000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 19548871000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19548871000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 19548871000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19548871000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 19548871000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071591 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.071591 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071591 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.071591 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.208436 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.208436 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.208436 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.208436 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13379.712857 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13379.712857 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13379.712857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13379.712857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 339568 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65260.797469 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 65260.797416 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4999517 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 404730 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 12.352722 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 9687465000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251550 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395782 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150137 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::writebacks 54046.251440 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 5724.395876 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5490.150100 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.824680 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087347 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.083773 # Average percentage of cache occupancy
@ -751,18 +751,18 @@ system.cpu.l2cache.overall_misses::cpu.data 388866 #
system.cpu.l2cache.overall_misses::total 405190 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 404000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 404000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837528000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 14837528000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2141943000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2141943000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680651000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680651000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2141943000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 48518179000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 50660122000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2141943000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 48518179000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 50660122000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14837606000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 14837606000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2142680000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2142680000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33680454000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 33680454000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2142680000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 48518060000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 50660740000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2142680000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 48518060000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 50660740000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 838232 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 838232 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1459802 # number of WritebackClean accesses(hits+misses)
@ -797,18 +797,18 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.278565
system.cpu.l2cache.overall_miss_rate::total 0.141825 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22444.444444 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22444.444444 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.169443 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.169443 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131214.346974 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131214.346974 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.759286 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.759286 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 125028.065846 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131214.346974 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.375224 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 125028.065846 # average overall miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127187.838058 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127187.838058 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131259.495222 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131259.495222 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123731.035572 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123731.035572 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 125029.591056 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131259.495222 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 124768.069206 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 125029.591056 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -841,24 +841,24 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13670938000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13670938000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978703000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978703000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960659500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960659500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978703000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631597500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 46610300500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978703000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631597500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 46610300500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1443571000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1443571000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13671016000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13671016000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1979440000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1979440000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960462500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960462500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1979440000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631478500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 46610918500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1979440000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631478500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 46610918500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442671000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442671000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3495402500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3495402500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494502500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494502500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses
@ -875,24 +875,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565
system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.169443 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.169443 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121214.346974 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121214.346974 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113739.395019 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113739.395019 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121214.346974 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.720253 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115033.195538 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208187.337756 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208187.337756 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211100.525426 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211100.525426 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data.
@ -958,40 +958,34 @@ system.iobus.trans_dist::ReadResp 7107 # Tr
system.iobus.trans_dist::WriteReq 51176 # Transaction distribution
system.iobus.trans_dist::WriteResp 51176 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5110 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116566 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20440 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 44381 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 386000 # Layer occupancy (ticks)
system.iobus.reqLayer1.occupancy 784500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
@ -1005,16 +999,10 @@ system.iobus.reqLayer24.occupancy 2308500 # La
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 224500 # Layer occupancy (ticks)
system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 98500 # Layer occupancy (ticks)
system.iobus.reqLayer27.occupancy 215092991 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 142500 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 215092991 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 31500 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks)
@ -1161,7 +1149,7 @@ system.membus.reqLayer1.occupancy 1319381154 # La
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 2160247074 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 2160244574 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
View file

@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0

73
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
View file

@ -15,10 +15,10 @@ boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
console=/scratch/nilay/GEM5/system/binaries/console
console=/work/gem5/dist/binaries/console
eventq_index=0
init_param=0
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
kernel=/work/gem5/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
@ -26,9 +26,10 @@ mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
pal=/work/gem5/dist/binaries/ts_osfpal
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
@ -171,6 +172,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -187,6 +189,7 @@ system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
@ -518,6 +521,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -534,6 +538,7 @@ system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
@ -676,6 +681,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -692,6 +698,7 @@ system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[3]
@ -1023,6 +1030,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -1039,6 +1047,7 @@ system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[2]
@ -1098,7 +1107,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
image_file=/work/gem5/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -1121,7 +1130,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/work/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
@ -1144,10 +1153,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
@ -1156,6 +1164,7 @@ children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
@ -1172,7 +1181,8 @@ system=system
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
cpu_side=system.iobus.master[29]
writeback_clean=false
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@ -1191,6 +1201,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -1207,6 +1218,7 @@ system=system
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -1342,7 +1354,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
image_file=/work/gem5/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@ -1355,12 +1367,13 @@ port=3456
[system.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -1368,9 +1381,16 @@ width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
[system.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
eventq_index=0
intrctrl=system.intrctrl
system=system
@ -1483,12 +1503,12 @@ dma_write_delay=0
dma_write_factor=0
eventq_index=0
hardware_address=00:90:00:00:00:01
host=system.tsunami.pchip
intr_delay=10000000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
rx_fifo_size=524288
@ -1498,9 +1518,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.master[28]
dma=system.iobus.slave[2]
pio=system.iobus.master[27]
pio=system.iobus.master[26]
[system.tsunami.fake_OROM]
type=IsaFake
@ -1933,14 +1952,13 @@ config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
eventq_index=0
host=system.tsunami.pchip
io_shift=0
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
dma=system.iobus.slave[1]
pio=system.iobus.master[25]
@ -1960,25 +1978,20 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
clk_domain=system.clk_domain
conf_base=8804649402368
conf_device_bits=8
conf_size=16777216
eventq_index=0
pci_dma_base=0
pci_mem_base=8796093022208
pci_pio_base=8804615847936
pio_addr=8802535473152
pio_latency=100000
platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
eventq_index=0
pio_addr=0
pio_latency=30000
platform=system.tsunami
size=16777216
system=system
pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain

14
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
View file

@ -1,14 +1,14 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Apr 22 2015 07:55:25
gem5 started Apr 22 2015 09:01:06
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
gem5 compiled Dec 4 2015 10:28:58
gem5 started Dec 4 2015 10:42:11
gem5 executing on e104799-lin, pid 22878
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
info: kernel located at: /work/gem5/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 133655000
Exiting @ tick 1904437574000 because m5_exit instruction encountered
info: Launching CPU 1 @ 179187500
Exiting @ tick 1922761887500 because m5_exit instruction encountered

498
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.922762 # Nu
sim_ticks 1922761887500 # Number of ticks simulated
final_tick 1922761887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 132982 # Simulator instruction rate (inst/s)
host_op_rate 132982 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4507220686 # Simulator tick rate (ticks/s)
host_mem_usage 384024 # Number of bytes of host memory used
host_seconds 426.60 # Real time elapsed on the host
host_inst_rate 136693 # Simulator instruction rate (inst/s)
host_op_rate 136693 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4632993573 # Simulator tick rate (ticks/s)
host_mem_usage 339884 # Number of bytes of host memory used
host_seconds 415.02 # Real time elapsed on the host
sim_insts 56729467 # Number of instructions simulated
sim_ops 56729467 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -111,8 +111,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 123171 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 317968 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 37909 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 317967 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 37910 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 29466 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 24871 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see
@ -168,14 +168,14 @@ system.physmem.wrQLenPdf::21 6400 # Wh
system.physmem.wrQLenPdf::22 6805 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8203 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8579 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9709 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9707 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8953 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 9138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 8272 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8747 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6928 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6099 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 325 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 232 # What write queue length does an incoming req see
@ -207,20 +207,20 @@ system.physmem.wrQLenPdf::60 52 # Wh
system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 45 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 65327 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 522.630582 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 319.337054 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 410.684018 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14917 22.83% 22.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11339 17.36% 40.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5448 8.34% 48.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::samples 65324 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 522.654583 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 319.374945 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 410.670236 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14914 22.83% 22.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11338 17.36% 40.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5449 8.34% 48.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2879 4.41% 52.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2603 3.98% 56.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1650 2.53% 59.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3828 5.86% 65.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2604 3.99% 56.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1649 2.52% 59.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3829 5.86% 65.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1203 1.84% 67.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 21460 32.85% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65327 # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 21459 32.85% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 65324 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5559 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 73.810757 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2831.423020 # Reads before turning the bus around for writes
@ -271,12 +271,12 @@ system.physmem.wrPerTurnAround::220-223 1 0.02% 99.96% # Wr
system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5559 # Writes before turning the bus around for reads
system.physmem.totQLat 4492977750 # Total ticks spent queuing
system.physmem.totMemAccLat 12186571500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 4493146250 # Total ticks spent queuing
system.physmem.totMemAccLat 12186740000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2051625000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10949.80 # Average queueing delay per DRAM burst
system.physmem.avgQLat 10950.21 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29699.80 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 29700.21 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.66 # Average system read bandwidth in MiByte/s
@ -287,39 +287,39 @@ system.physmem.busUtilRead 0.11 # Da
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.48 # Average write queue length when enqueuing
system.physmem.readRowHits 369433 # Number of row buffer hits during reads
system.physmem.writeRowHits 98707 # Number of row buffer hits during writes
system.physmem.readRowHits 369435 # Number of row buffer hits during reads
system.physmem.writeRowHits 98708 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 80.14 # Row buffer hit rate for writes
system.physmem.avgGap 3603301.16 # Average gap between requests
system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 247242240 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 134904000 # Energy for precharge commands per rank (pJ)
system.physmem_0.actEnergy 247227120 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 134895750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1602939000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 400671360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 63449600445 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1097998572000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1289419261125 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.608464 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1826410636250 # Time in different power states
system.physmem_0.actBackEnergy 63448746300 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1097999321250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1289419132860 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.608398 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1826411929500 # Time in different power states
system.physmem_0.memoryStateTime::REF 64205180000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 32144391250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 32143098000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 246629880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 134569875 # Energy for precharge commands per rank (pJ)
system.physmem_1.actEnergy 246622320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 134565750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1597596000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 397288800 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 62800369875 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1098568064250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1289329850760 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.561968 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1827364141250 # Time in different power states
system.physmem_1.actBackEnergy 62799950070 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1098568432500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1289329787520 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.561935 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1827364757000 # Time in different power states
system.physmem_1.memoryStateTime::REF 64205180000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 31190872500 # Time in different power states
system.physmem_1.memoryStateTime::ACT 31190256750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu0.branchPred.lookups 16164803 # Number of BP lookups
system.cpu0.branchPred.condPredicted 14134057 # Number of conditional branches predicted
@ -366,11 +366,11 @@ system.cpu0.itb.data_accesses 0 # DT
system.cpu0.numCycles 147492353 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 26474453 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.icacheStallCycles 26474452 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 70295181 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 16164803 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 6131250 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 112661982 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.Cycles 112660359 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1056864 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 660 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 29689 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
@ -378,12 +378,12 @@ system.cpu0.fetch.PendingTrapStallCycles 929577 # Nu
system.cpu0.fetch.PendingQuiesceStallCycles 461648 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 350 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 8123308 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 229144 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 141086791 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.498241 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.734215 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 141085167 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.498246 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.734224 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 127943316 90.68% 90.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 127941692 90.68% 90.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 834789 0.59% 91.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 1813592 1.29% 92.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 779670 0.55% 93.11% # Number of instructions fetched each cycle (Total)
@ -395,35 +395,35 @@ system.cpu0.fetch.rateDist::8 5070041 3.59% 100.00% # Nu
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 141086791 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 141085167 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.109598 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.476602 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 21397284 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 108971969 # Number of cycles decode is blocked
system.cpu0.decode.IdleCycles 21397283 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 108970346 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 8457985 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 1766417 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 493135 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 516601 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 35757 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 61523411 # Number of instructions handled by decode
system.cpu0.decode.DecodedInsts 61523415 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 108836 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 493135 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 22231623 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 77943277 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 19950150 # count of cycles rename stalled for serializing inst
system.cpu0.rename.IdleCycles 22231622 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 77943613 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 19948481 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 9304003 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 11164601 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 59421423 # Number of instructions processed by rename
system.cpu0.rename.UnblockCycles 11164311 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 59421431 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 199471 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 2023547 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 224739 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 7186522 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 39708138 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 72284773 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 72145342 # Number of integer rename lookups
system.cpu0.rename.LQFullEvents 224227 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 7186744 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 39708144 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 72284783 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 72145352 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 129802 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 34979364 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 4728766 # Number of HB maps that are undone due to squashing
system.cpu0.rename.UndoneMaps 4728772 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1463848 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 211077 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 12544775 # count of insts added to the skid buffer
@ -431,30 +431,30 @@ system.cpu0.memDep0.insertedLoads 9257817 # Nu
system.cpu0.memDep0.insertedStores 6153108 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1360057 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1005705 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 53010072 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsAdded 53010076 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1876155 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 52220775 # Number of instructions issued
system.cpu0.iq.iqInstsIssued 52220777 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 51551 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 6501427 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 2875305 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedInstsExamined 6501431 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 2875308 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 1291728 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 141086791 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.370132 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.087511 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::samples 141085167 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.370137 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.087516 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 119618317 84.78% 84.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 9300566 6.59% 91.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3865351 2.74% 94.12% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 119616695 84.78% 84.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 9300562 6.59% 91.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3865352 2.74% 94.12% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2730572 1.94% 96.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2821391 2.00% 98.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1375833 0.98% 99.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 902269 0.64% 99.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2821393 2.00% 98.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 1375831 0.98% 99.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 902270 0.64% 99.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 360488 0.26% 99.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 112004 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 141086791 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 141085167 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 182068 18.38% 18.38% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 2 0.00% 18.38% # attempts to use FU when none available
@ -490,7 +490,7 @@ system.cpu0.iq.fu_full::MemWrite 337015 34.02% 100.00% # at
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 35835166 68.62% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 35835168 68.62% 68.63% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 56519 0.11% 68.74% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 28571 0.05% 68.79% # Type of FU issued
@ -523,17 +523,17 @@ system.cpu0.iq.FU_type_0::MemRead 9523186 18.24% 87.03% # Ty
system.cpu0.iq.FU_type_0::MemWrite 5952100 11.40% 98.43% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 819570 1.57% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 52220775 # Type of FU issued
system.cpu0.iq.FU_type_0::total 52220777 # Type of FU issued
system.cpu0.iq.rate 0.354058 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 990706 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.018971 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 245999962 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 61137242 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_reads 245998342 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 61137250 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 50831283 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 570635 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 267757 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 262095 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 52900144 # Number of integer alu accesses
system.cpu0.iq.int_alu_accesses 52900146 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 307557 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 581308 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
@ -544,13 +544,13 @@ system.cpu0.iew.lsq.thread0.squashedStores 500436 #
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 18736 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 408208 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread0.cacheBlocked 408207 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 493135 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 74418027 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 1058724 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 58259516 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 116557 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispatchedInsts 58259520 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 116565 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 9257817 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 6153108 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 1657861 # Number of dispatched non-speculative instructions
@ -562,7 +562,7 @@ system.cpu0.iew.predictedNotTakenIncorrect 351909 #
system.cpu0.iew.branchMispredicts 505215 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 51717296 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 9230924 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 503478 # Number of squashed instructions skipped in execute
system.cpu0.iew.iewExecSquashedInsts 503480 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 3373289 # number of nop insts executed
system.cpu0.iew.exec_refs 15132335 # number of memory reference insts executed
@ -571,22 +571,22 @@ system.cpu0.iew.exec_stores 5901411 # Nu
system.cpu0.iew.exec_rate 0.350644 # Inst execution rate
system.cpu0.iew.wb_sent 51207379 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 51093378 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 26334207 # num instructions producing a value
system.cpu0.iew.wb_consumers 36473944 # num instructions consuming a value
system.cpu0.iew.wb_producers 26334208 # num instructions producing a value
system.cpu0.iew.wb_consumers 36473947 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.346414 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.722001 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 6824839 # The number of squashed insts skipped by commit
system.cpu0.commit.commitSquashedInsts 6824843 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 584427 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 463110 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 139882457 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.366962 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.256012 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::samples 139880833 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.366966 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.256019 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 121750983 87.04% 87.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 7187616 5.14% 92.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 121749360 87.04% 87.04% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 7187615 5.14% 92.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 3944064 2.82% 95.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2051217 1.47% 96.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1611428 1.15% 97.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 2051216 1.47% 96.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 1611429 1.15% 97.61% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 577022 0.41% 98.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 437359 0.31% 98.34% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 434985 0.31% 98.65% # Number of insts commited each cycle
@ -594,7 +594,7 @@ system.cpu0.commit.committed_per_cycle::8 1887783 1.35% 100.00% # N
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 139882457 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 139880833 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 51331530 # Number of instructions committed
system.cpu0.commit.committedOps 51331530 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
@ -641,10 +641,10 @@ system.cpu0.commit.op_class_0::IprAccess 819569 1.60% 100.00% # Cl
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 51331530 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1887783 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 195950193 # The number of ROB reads
system.cpu0.rob.rob_writes 117511428 # The number of ROB writes
system.cpu0.rob.rob_reads 195948573 # The number of ROB reads
system.cpu0.rob.rob_writes 117511436 # The number of ROB writes
system.cpu0.timesIdled 525574 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 6405562 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.idleCycles 6407186 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 3698031423 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 48384795 # Number of Instructions Simulated
system.cpu0.committedOps 48384795 # Number of Ops (including micro ops) Simulated
@ -659,12 +659,12 @@ system.cpu0.fp_regfile_writes 130249 # nu
system.cpu0.misc_regfile_reads 1711265 # number of misc regfile reads
system.cpu0.misc_regfile_writes 819270 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 1282737 # number of replacements
system.cpu0.dcache.tags.tagsinuse 506.160384 # Cycle average of tags in use
system.cpu0.dcache.tags.tagsinuse 506.160385 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 10524244 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1283249 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 8.201249 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.160384 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.160385 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988595 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.988595 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
@ -698,18 +698,18 @@ system.cpu0.dcache.demand_misses::cpu0.data 3363608 #
system.cpu0.dcache.demand_misses::total 3363608 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3363608 # number of overall misses
system.cpu0.dcache.overall_misses::total 3363608 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54837998000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 54837998000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114303059042 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114303059042 # number of WriteReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54836064000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 54836064000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114300477543 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 114300477543 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389087500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 389087500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45510000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 45510000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 169141057042 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 169141057042 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 169141057042 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 169141057042 # number of overall miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 169136541543 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 169136541543 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 169136541543 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 169136541543 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8078505 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8078505 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5447584 # number of WriteReq accesses(hits+misses)
@ -734,23 +734,23 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248676
system.cpu0.dcache.demand_miss_rate::total 0.248676 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248676 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.248676 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34387.118782 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 34387.118782 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64618.778654 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64618.778654 # average WriteReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34385.906034 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 34385.906034 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64617.319259 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64617.319259 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50285.603151 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 50285.603151 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50285.603151 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 50285.603151 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 6995611 # number of cycles access was blocked
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50284.260694 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 50284.260694 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50284.260694 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 50284.260694 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 6995201 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 14546 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 119540 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 119539 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 103 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.521089 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58.518149 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 141.223301 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
@ -784,24 +784,24 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10126
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10126 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17171 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17171 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43466083500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43466083500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18236016784 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18236016784 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43465523500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43465523500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18235926784 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18235926784 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 187455000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 187455000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42654000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42654000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61702100284 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 61702100284 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61702100284 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 61702100284 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563410000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563410000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61701450284 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 61701450284 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61701450284 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 61701450284 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1562510000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1562510000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2299016000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2299016000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3862426000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3862426000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3861526000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3861526000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125677 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125677 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048825 # mshr miss rate for WriteReq accesses
@ -814,24 +814,24 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094725
system.cpu0.dcache.demand_mshr_miss_rate::total 0.094725 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.094725 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.790900 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.790900 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.382401 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.382401 # average WriteReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.239329 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.239329 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.044026 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.044026 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48157.360945 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48157.360945 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48157.360945 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48157.360945 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221917.672108 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221917.672108 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48156.853632 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48156.853632 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48156.853632 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48156.853632 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221789.921930 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221789.921930 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224938.908625 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224938.908625 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224886.494671 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224886.494671 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 908501 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.069795 # Cycle average of tags in use
@ -861,12 +861,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 954611 #
system.cpu0.icache.demand_misses::total 954611 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 954611 # number of overall misses
system.cpu0.icache.overall_misses::total 954611 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14636609987 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14636609987 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14636609987 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14636609987 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14636609987 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14636609987 # number of overall miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14637521487 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 14637521487 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 14637521487 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 14637521487 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 14637521487 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 14637521487 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 8123307 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 8123307 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 8123307 # number of demand (read+write) accesses
@ -879,12 +879,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117515
system.cpu0.icache.demand_miss_rate::total 0.117515 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117515 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.117515 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15332.538581 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 15332.538581 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15332.538581 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 15332.538581 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15332.538581 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 15332.538581 # average overall miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15333.493420 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 15333.493420 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15333.493420 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 15333.493420 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15333.493420 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 15333.493420 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 8572 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 278 # number of cycles access was blocked
@ -907,24 +907,24 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 909320
system.cpu0.icache.demand_mshr_misses::total 909320 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 909320 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 909320 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12934939493 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12934939493 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12934939493 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 12934939493 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12934939493 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 12934939493 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12935759993 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12935759993 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12935759993 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 12935759993 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12935759993 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 12935759993 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111940 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.111940 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.111940 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14224.848780 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14224.848780 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14224.848780 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14224.848780 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14225.751103 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14225.751103 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14225.751103 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 3578846 # Number of BP lookups
system.cpu1.branchPred.condPredicted 3133511 # Number of conditional branches predicted
@ -1263,12 +1263,12 @@ system.cpu1.fp_regfile_writes 51516 # nu
system.cpu1.misc_regfile_reads 503472 # number of misc regfile reads
system.cpu1.misc_regfile_writes 210349 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 98962 # number of replacements
system.cpu1.dcache.tags.tagsinuse 486.970751 # Cycle average of tags in use
system.cpu1.dcache.tags.tagsinuse 486.970752 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 2466427 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 99271 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 24.845393 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 1048837181500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.970751 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.970752 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951115 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.951115 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 309 # Occupied blocks per task id
@ -1543,40 +1543,34 @@ system.iobus.trans_dist::ReadResp 7371 # Tr
system.iobus.trans_dist::WriteReq 54609 # Transaction distribution
system.iobus.trans_dist::WriteResp 54609 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 40504 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 123960 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 73842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2735474 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 12353500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 448000 # Layer occupancy (ticks)
system.iobus.reqLayer1.occupancy 827500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
@ -1590,16 +1584,10 @@ system.iobus.reqLayer24.occupancy 2829000 # La
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5954500 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 217500 # Layer occupancy (ticks)
system.iobus.reqLayer26.occupancy 87000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 87000 # Layer occupancy (ticks)
system.iobus.reqLayer27.occupancy 215061495 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 131500 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 215061495 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30500 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 27447000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks)
@ -1702,14 +1690,14 @@ system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955
system.iocache.overall_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 345304 # number of replacements
system.l2c.tags.tagsinuse 65190.216948 # Cycle average of tags in use
system.l2c.tags.tagsinuse 65190.216881 # Cycle average of tags in use
system.l2c.tags.total_refs 3990482 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 410468 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 9.721786 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 11177481000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 53120.456427 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5260.305215 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6531.960123 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::writebacks 53120.456317 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5260.305264 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 6531.960119 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 208.754945 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 68.740237 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.810554 # Average percentage of cache occupancy
@ -1787,25 +1775,25 @@ system.l2c.UpgradeReq_miss_latency::total 21371000 # n
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2842500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 568500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 3411000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 16040827500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 16040737500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1166717500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 17207545000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1816563500 # number of ReadCleanReq miss cycles
system.l2c.ReadExReq_miss_latency::total 17207455000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1817383500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 219865000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 2036428500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 33893464500 # number of ReadSharedReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 2037248500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 33892904500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 116817000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 34010281500 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1816563500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 49934292000 # number of demand (read+write) miss cycles
system.l2c.ReadSharedReq_miss_latency::total 34009721500 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1817383500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 49933642000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 219865000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1283534500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 53254255000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1816563500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 49934292000 # number of overall miss cycles
system.l2c.demand_miss_latency::total 53254425000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1817383500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 49933642000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 219865000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1283534500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 53254255000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 53254425000 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 820126 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 820126 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 859282 # number of WritebackClean accesses(hits+misses)
@ -1866,25 +1854,25 @@ system.l2c.UpgradeReq_avg_miss_latency::total 5500.900901
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6767.857143 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1289.115646 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 3961.672474 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139638.451695 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139637.668228 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 159170.190996 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 140809.998036 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133649.462919 # average ReadCleanReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 140809.261563 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133709.792525 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135052.211302 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133799.507227 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124162.800026 # average ReadSharedReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 133853.383706 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124160.748564 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140913.148372 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 124213.515093 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 133649.462919 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 128746.401960 # average overall miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 124211.469842 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 133709.792525 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 128744.726054 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135052.211302 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 157315.173428 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 129500.241958 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 133649.462919 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 128746.401960 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 129500.655353 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 133709.792525 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 128744.726054 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135052.211302 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 157315.173428 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 129500.241958 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 129500.655353 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@ -1946,34 +1934,34 @@ system.l2c.UpgradeReq_mshr_miss_latency::total 278688500
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 29951500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 31656500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 61608000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14892087500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 14891997500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1093417500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 15985505000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1680522000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 15985415000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1681342000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 201578500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 1882100500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31173569000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 1882920500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 31173009000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 108527000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 31282096000 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1680522000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 46065656500 # number of demand (read+write) MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 31281536000 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 1681342000 # number of demand (read+write) MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::cpu1.inst 201578500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1201944500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 49149701500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 1680522000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 46065656500 # number of overall MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 49149871500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 1681342000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 46065006500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 201578500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1201944500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 49149701500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1475287500 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_miss_latency::total 49149871500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1474387500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28274500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1503562000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1502662000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2182363000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 649671500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2832034500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3657650500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3656750500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 677946000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4335596500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4334696500 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941457 # mshr miss rate for UpgradeReq accesses
@ -2007,34 +1995,34 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129638.451695 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129637.668228 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.998036 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average ReadCleanReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.261563 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123814.255641 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114198.936903 # average ReadSharedReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123868.199461 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114196.885440 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114249.542558 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118771.835761 # average overall mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114247.497306 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118770.159856 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 119524.577467 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123649.621073 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118771.835761 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 119524.990881 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118770.159856 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 119524.577467 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209409.155429 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_miss_latency::total 119524.990881 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209281.405252 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208973.175817 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208848.088951 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213013.249083 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212960.835129 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 214082.386925 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 214037.946869 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 7195 # Transaction distribution
system.membus.trans_dist::ReadResp 296301 # Transaction distribution
@ -2082,7 +2070,7 @@ system.membus.reqLayer1.occupancy 1357207403 # La
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer2.occupancy 98500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 2187694355 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 2187691105 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 69834733 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
@ -2190,11 +2178,11 @@ system.cpu0.kern.ipl_good::22 1928 1.48% 50.79% # nu
system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 63870 49.07% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 130171 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1865607975500 97.03% 97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::0 1865608787500 97.03% 97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 63996500 0.00% 97.03% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 577908500 0.03% 97.06% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 88293000 0.00% 97.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 56422873000 2.93% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 56422061000 2.93% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1922761046500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
View file

@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0

69
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
View file

@ -15,10 +15,10 @@ boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
console=/scratch/nilay/GEM5/system/binaries/console
console=/work/gem5/dist/binaries/console
eventq_index=0
init_param=0
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
kernel=/work/gem5/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
@ -26,9 +26,10 @@ mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
pal=/work/gem5/dist/binaries/ts_osfpal
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
@ -171,6 +172,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -187,6 +189,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -518,6 +521,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -534,6 +538,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -567,6 +572,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -583,6 +589,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -598,12 +605,13 @@ size=4194304
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -611,6 +619,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@ -643,7 +658,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
image_file=/work/gem5/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -666,7 +681,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/work/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
@ -689,10 +704,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
@ -701,6 +715,7 @@ children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
@ -717,7 +732,8 @@ system=system
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
cpu_side=system.iobus.master[29]
writeback_clean=false
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@ -852,7 +868,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
image_file=/work/gem5/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@ -865,7 +881,7 @@ port=3456
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
eventq_index=0
intrctrl=system.intrctrl
system=system
@ -978,12 +994,12 @@ dma_write_delay=0
dma_write_factor=0
eventq_index=0
hardware_address=00:90:00:00:00:01
host=system.tsunami.pchip
intr_delay=10000000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
rx_fifo_size=524288
@ -993,9 +1009,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.master[28]
dma=system.iobus.slave[2]
pio=system.iobus.master[27]
pio=system.iobus.master[26]
[system.tsunami.fake_OROM]
type=IsaFake
@ -1428,14 +1443,13 @@ config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
eventq_index=0
host=system.tsunami.pchip
io_shift=0
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
dma=system.iobus.slave[1]
pio=system.iobus.master[25]
@ -1455,25 +1469,20 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
clk_domain=system.clk_domain
conf_base=8804649402368
conf_device_bits=8
conf_size=16777216
eventq_index=0
pci_dma_base=0
pci_mem_base=8796093022208
pci_pio_base=8804615847936
pio_addr=8802535473152
pio_latency=100000
platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
eventq_index=0
pio_addr=0
pio_latency=30000
platform=system.tsunami
size=16777216
system=system
pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain

12
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
View file

@ -1,13 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Apr 22 2015 07:55:25
gem5 started Apr 22 2015 08:27:15
gem5 executing on phenom
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
gem5 compiled Dec 4 2015 10:28:58
gem5 started Dec 4 2015 10:48:09
gem5 executing on e104799-lin, pid 23716
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
info: kernel located at: /work/gem5/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1861005569500 because m5_exit instruction encountered
Exiting @ tick 1875760362000 because m5_exit instruction encountered

732
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
View file

@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
4096K Bcache detected; load hit latency 30 cycles, load miss latency 255 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0

73
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
View file

@ -15,10 +15,10 @@ boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
console=/scratch/nilay/GEM5/system/binaries/console
console=/work/gem5/dist/binaries/console
eventq_index=0
init_param=0
kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
kernel=/work/gem5/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
@ -26,9 +26,10 @@ mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
pal=/work/gem5/dist/binaries/ts_osfpal
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
@ -103,6 +104,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -119,6 +121,7 @@ system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
@ -143,6 +146,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -159,6 +163,7 @@ system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
@ -204,7 +209,7 @@ dtb=system.cpu1.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=Null
interrupts=
isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
@ -283,7 +288,7 @@ iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=Null
interrupts=
isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
@ -697,7 +702,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
image_file=/work/gem5/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@ -720,7 +725,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/work/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
@ -743,10 +748,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
@ -755,6 +759,7 @@ children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
@ -771,7 +776,8 @@ system=system
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
cpu_side=system.iobus.master[29]
writeback_clean=false
cpu_side=system.iobus.master[27]
mem_side=system.membus.slave[2]
[system.iocache.tags]
@ -790,6 +796,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -806,6 +813,7 @@ system=system
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@ -941,7 +949,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
image_file=/work/gem5/dist/disks/linux-latest.img
read_only=true
[system.terminal]
@ -954,12 +962,13 @@ port=3456
[system.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -967,9 +976,16 @@ width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
[system.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
eventq_index=0
intrctrl=system.intrctrl
system=system
@ -1082,12 +1098,12 @@ dma_write_delay=0
dma_write_factor=0
eventq_index=0
hardware_address=00:90:00:00:00:01
host=system.tsunami.pchip
intr_delay=10000000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
rx_fifo_size=524288
@ -1097,9 +1113,8 @@ system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.master[28]
dma=system.iobus.slave[2]
pio=system.iobus.master[27]
pio=system.iobus.master[26]
[system.tsunami.fake_OROM]
type=IsaFake
@ -1532,14 +1547,13 @@ config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
eventq_index=0
host=system.tsunami.pchip
io_shift=0
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
dma=system.iobus.slave[1]
pio=system.iobus.master[25]
@ -1559,25 +1573,20 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
clk_domain=system.clk_domain
conf_base=8804649402368
conf_device_bits=8
conf_size=16777216
eventq_index=0
pci_dma_base=0
pci_mem_base=8796093022208
pci_pio_base=8804615847936
pio_addr=8802535473152
pio_latency=100000
platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
eventq_index=0
pio_addr=0
pio_latency=30000
platform=system.tsunami
size=16777216
system=system
pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain

8
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
View file

@ -43,11 +43,3 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 11394, Bank: 3
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0

10
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
View file

@ -1,12 +1,10 @@
Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Sep 14 2015 20:54:01
gem5 started Sep 14 2015 20:54:31
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
gem5 compiled Dec 4 2015 10:28:58
gem5 started Dec 4 2015 10:29:24
gem5 executing on e104799-lin, pid 21387
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009

28
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 1.843590 # Nu
sim_ticks 1843589966000 # Number of ticks simulated
final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 220463 # Simulator instruction rate (inst/s)
host_op_rate 220463 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5656183181 # Simulator tick rate (ticks/s)
host_mem_usage 378132 # Number of bytes of host memory used
host_seconds 325.94 # Real time elapsed on the host
host_inst_rate 221527 # Simulator instruction rate (inst/s)
host_op_rate 221527 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5683484333 # Simulator tick rate (ticks/s)
host_mem_usage 334252 # Number of bytes of host memory used
host_seconds 324.38 # Real time elapsed on the host
sim_insts 71858146 # Number of instructions simulated
sim_ops 71858146 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -1366,40 +1366,34 @@ system.iobus.trans_dist::ReadResp 7317 # Tr
system.iobus.trans_dist::WriteReq 51364 # Transaction distribution
system.iobus.trans_dist::WriteResp 51364 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5196 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33912 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 117362 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20784 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 45584 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2564500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 116500 # Layer occupancy (ticks)
system.iobus.reqLayer1.occupancy 118500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 55500 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
@ -1407,10 +1401,8 @@ system.iobus.reqLayer23.occupancy 6287500 # La
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 2121000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 84230549 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 84230549 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 16458000 # Layer occupancy (ticks)

2
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
View file

@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070
4096K Bcache detected; load hit latency 6 cycles, load miss latency 32 cycles
4096K Bcache detected; load hit latency 6 cycles, load miss latency 30 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -1615,10 +1615,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -1645,7 +1644,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1809,12 +1808,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
[system.realview.aaci_fake]
@ -1907,16 +1903,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1932,7 +1927,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -2095,13 +2090,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -2111,9 +2106,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -2155,7 +2149,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -2236,14 +2230,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -2260,7 +2253,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -2275,7 +2268,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -2398,17 +2391,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=16
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -2460,7 +2455,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -2475,7 +2470,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 17:55:15
gem5 executing on e104799-lin, pid 4773
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 12:40:05
gem5 executing on e104799-lin, pid 5560
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2848948370000 because m5_exit instruction encountered
Exiting @ tick 2848979128500 because m5_exit instruction encountered

4533
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -845,10 +845,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -875,7 +874,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1002,12 +1001,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
[system.realview.aaci_fake]
@ -1100,16 +1096,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1125,7 +1120,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1288,13 +1283,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1304,9 +1299,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1348,7 +1342,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1429,14 +1423,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1453,7 +1446,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1468,7 +1461,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1591,17 +1584,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=16
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1653,7 +1648,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1668,7 +1663,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 17:52:07
gem5 executing on e104799-lin, pid 4748
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 12:02:21
gem5 executing on e104799-lin, pid 1517
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2858554679500 because m5_exit instruction encountered
Exiting @ tick 2858558607500 because m5_exit instruction encountered

1779
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
View file

File diff suppressed because it is too large Load diff

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -901,10 +901,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -931,7 +930,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1058,12 +1057,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
[system.realview.aaci_fake]
@ -1156,16 +1152,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1181,7 +1176,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1344,13 +1339,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1360,9 +1355,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1404,7 +1398,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1485,14 +1479,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1509,7 +1502,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1524,7 +1517,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1647,17 +1640,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=16
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1709,7 +1704,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1724,7 +1719,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

2
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
View file

@ -42,6 +42,6 @@ warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: Ignoring write to miscreg pmcr
warn: 409464655500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
warn: 409464076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x80000001, checker: 0x80000000
warn: instruction 'mcr dcisw' unimplemented
warn: instruction 'mcr bpiall' unimplemented

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:04:32
gem5 executing on e104799-lin, pid 5292
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 12:53:29
gem5 executing on e104799-lin, pid 6838
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@ -42,4 +42,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2832917624000 because m5_exit instruction encountered
Exiting @ tick 2832912592000 because m5_exit instruction encountered

2198
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
View file

File diff suppressed because it is too large Load diff

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -1423,10 +1423,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -1453,7 +1452,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1617,12 +1616,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
[system.realview.aaci_fake]
@ -1715,16 +1711,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1740,7 +1735,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1903,13 +1898,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1919,9 +1914,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1963,7 +1957,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -2044,14 +2038,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -2068,7 +2061,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -2083,7 +2076,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -2206,17 +2199,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=16
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -2268,7 +2263,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -2283,7 +2278,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:09:43
gem5 executing on e104799-lin, pid 6272
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 11:33:05
gem5 executing on e104799-lin, pid 30938
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2837504217500 because m5_exit instruction encountered
Exiting @ tick 2827514981500 because m5_exit instruction encountered

5778
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -749,10 +749,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -779,7 +778,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -906,12 +905,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
[system.realview.aaci_fake]
@ -1004,16 +1000,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1029,7 +1024,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1192,13 +1187,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1208,9 +1203,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1252,7 +1246,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1333,14 +1327,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1357,7 +1350,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1372,7 +1365,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1495,17 +1488,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=16
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1557,7 +1552,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1572,7 +1567,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 17:56:31
gem5 executing on e104799-lin, pid 4788
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 13:05:09
gem5 executing on e104799-lin, pid 8022
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2832917624000 because m5_exit instruction encountered
Exiting @ tick 2832912592000 because m5_exit instruction encountered

2144
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -1612,10 +1612,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -1642,7 +1641,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1806,12 +1805,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
[system.realview.aaci_fake]
@ -1904,16 +1900,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1929,7 +1924,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -2092,13 +2087,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -2108,9 +2103,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -2152,7 +2146,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -2233,14 +2227,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -2257,7 +2250,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -2272,7 +2265,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -2395,17 +2388,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=16
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -2457,7 +2452,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -2472,7 +2467,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:10:16
gem5 executing on e104799-lin, pid 6288
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 13:54:35
gem5 executing on e104799-lin, pid 12868
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second

32
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 2.824799 # Nu
sim_ticks 2824799320500 # Number of ticks simulated
final_tick 2824799320500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 238793 # Simulator instruction rate (inst/s)
host_op_rate 289676 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5483857198 # Simulator tick rate (ticks/s)
host_mem_usage 587432 # Number of bytes of host memory used
host_seconds 515.11 # Real time elapsed on the host
host_inst_rate 252554 # Simulator instruction rate (inst/s)
host_op_rate 306369 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5799873287 # Simulator tick rate (ticks/s)
host_mem_usage 587696 # Number of bytes of host memory used
host_seconds 487.05 # Real time elapsed on the host
sim_insts 123005008 # Number of instructions simulated
sim_ops 149215388 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -2055,6 +2055,7 @@ system.iobus.trans_dist::WriteReq 59010 # Tr
system.iobus.trans_dist::WriteResp 59010 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
@ -2070,16 +2071,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
@ -2095,10 +2094,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
@ -2107,10 +2103,12 @@ system.iobus.reqLayer0.occupancy 27670500 # La
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 101500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
system.iobus.reqLayer2.occupancy 205000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 16500 # Layer occupancy (ticks)
system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 12500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks)
@ -2121,14 +2119,10 @@ system.iobus.reqLayer20.occupancy 9000 # La
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 3858000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 90500 # Layer occupancy (ticks)
system.iobus.reqLayer24.occupancy 22212000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 22212000 # Layer occupancy (ticks)
system.iobus.reqLayer25.occupancy 78391042 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 114500 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 78391042 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 48071000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 15512000 # Layer occupancy (ticks)

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -1261,10 +1261,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -1291,7 +1290,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1455,12 +1454,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=false
pci_io_base=0
system=system
[system.realview.aaci_fake]
@ -1553,16 +1549,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1578,7 +1573,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1741,13 +1736,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1757,9 +1752,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1801,7 +1795,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1882,14 +1876,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1906,7 +1899,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1921,7 +1914,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -2044,17 +2037,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=16
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=0
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -2106,7 +2101,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -2121,7 +2116,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
View file

@ -43,11 +43,17 @@ warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
warn: CP14 unimplemented crn[3], opc1[0], crm[0], opc2[0]
warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0]
warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[0]
warn: CP14 unimplemented crn[12], opc1[0], crm[12], opc2[1]
warn: CP14 unimplemented crn[12], opc1[0], crm[0], opc2[3]
warn: instruction 'mcr bpiall' unimplemented
warn: CP14 unimplemented crn[2], opc1[2], crm[4], opc2[1]
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
View file

@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:14:24
gem5 executing on e104799-lin, pid 6415
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 12:17:01
gem5 executing on e104799-lin, pid 3291
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second

3928
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -1615,10 +1615,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -1645,7 +1644,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1809,12 +1808,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -1907,16 +1903,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1932,7 +1927,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -2095,13 +2090,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -2111,9 +2106,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -2155,7 +2149,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -2236,14 +2230,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -2260,7 +2253,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -2275,7 +2268,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -2398,17 +2391,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -2460,7 +2455,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -2475,7 +2470,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:19:04
gem5 executing on e104799-lin, pid 6711
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 12:36:35
gem5 executing on e104799-lin, pid 5221
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 47381662864000 because m5_exit instruction encountered
Exiting @ tick 47381683294000 because m5_exit instruction encountered

5147
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

54
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
View file

@ -107,60 +107,60 @@
[ 2.145678] pci_bus 0000:00: bus scan returning with max=00
[ 2.145690] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.145712] pci 0000:00:00.0: fixup irq: got 33
[ 2.145721] pci 0000:00:00.0: assigning IRQ 33
[ 2.145720] pci 0000:00:00.0: assigning IRQ 33
[ 2.145731] pci 0000:00:01.0: fixup irq: got 34
[ 2.145740] pci 0000:00:01.0: assigning IRQ 34
[ 2.145752] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.145765] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 2.145779] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.145792] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.145778] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.145791] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.145803] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.145815] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.145814] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.145826] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.145838] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.146510] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.146790] ata_piix 0000:00:01.0: version 2.13
[ 2.146802] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.146834] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.147106] scsi0 : ata_piix
[ 2.147190] scsi1 : ata_piix
[ 2.147234] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.147247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.147374] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.146509] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.146789] ata_piix 0000:00:01.0: version 2.13
[ 2.146800] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.146833] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.147105] scsi0 : ata_piix
[ 2.147189] scsi1 : ata_piix
[ 2.147233] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.147246] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.147373] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.147386] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.147401] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.147413] e1000 0000:00:00.0: enabling bus mastering
[ 2.290900] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.290911] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290940] ata1.00: configured for UDMA/33
[ 2.147412] e1000 0000:00:00.0: enabling bus mastering
[ 2.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.290910] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290939] ata1.00: configured for UDMA/33
[ 2.291006] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.291133] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.291132] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.291158] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.291199] sd 0:0:0:0: [sda] Write Protect is off
[ 2.291208] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.291229] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.291366] sda: sda1
[ 2.291489] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.411160] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.411174] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.411161] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.411175] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.411196] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.411206] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.411207] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.411241] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.411314] usbcore: registered new interface driver usb-storage
[ 2.411381] mousedev: PS/2 mouse device common for all mice
[ 2.411382] mousedev: PS/2 mouse device common for all mice
[ 2.411554] usbcore: registered new interface driver usbhid
[ 2.411564] usbhid: USB HID core driver
[ 2.411598] TCP: cubic registered
[ 2.411599] TCP: cubic registered
[ 2.411606] NET: Registered protocol family 17
[ 2.412053] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.412103] devtmpfs: mounted
[ 2.412104] devtmpfs: mounted
[ 2.412177] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 2.450715] udevd[609]: starting version 182
[ 2.450669] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 2.523621] random: dd urandom read with 17 bits of entropy available
[ 2.523747] random: dd urandom read with 17 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
[ 2.651084] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
[ 2.651088] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -845,10 +845,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -875,7 +874,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1002,12 +1001,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -1100,16 +1096,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1125,7 +1120,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1288,13 +1283,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1304,9 +1299,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1348,7 +1342,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1429,14 +1423,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1453,7 +1446,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1468,7 +1461,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1591,17 +1584,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1653,7 +1648,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1668,7 +1663,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:17:11
gem5 executing on e104799-lin, pid 6674
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 13:24:25
gem5 executing on e104799-lin, pid 9941
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51667599599000 because m5_exit instruction encountered
Exiting @ tick 51667481628000 because m5_exit instruction encountered

2110
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
View file

File diff suppressed because it is too large Load diff

16
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
View file

@ -104,10 +104,10 @@
[ 3.139989] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.140001] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.140044] pci_bus 0000:00: fixups for bus
[ 3.140053] pci_bus 0000:00: bus scan returning with max=00
[ 3.140052] pci_bus 0000:00: bus scan returning with max=00
[ 3.140066] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.140090] pci 0000:00:00.0: fixup irq: got 33
[ 3.140099] pci 0000:00:00.0: assigning IRQ 33
[ 3.140089] pci 0000:00:00.0: fixup irq: got 33
[ 3.140098] pci 0000:00:00.0: assigning IRQ 33
[ 3.140110] pci 0000:00:01.0: fixup irq: got 34
[ 3.140119] pci 0000:00:01.0: assigning IRQ 34
[ 3.140132] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
@ -144,15 +144,15 @@
[ 3.421575] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 3.421589] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 3.421613] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.421624] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.421623] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.421648] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.421660] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.421747] usbcore: registered new interface driver usb-storage
[ 3.421815] mousedev: PS/2 mouse device common for all mice
[ 3.422010] usbcore: registered new interface driver usbhid
[ 3.422009] usbcore: registered new interface driver usbhid
[ 3.422020] usbhid: USB HID core driver
[ 3.422060] TCP: cubic registered
[ 3.422069] NET: Registered protocol family 17
[ 3.422068] NET: Registered protocol family 17
[ 3.422528] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 3.422570] devtmpfs: mounted
[ 3.422641] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
@ -160,7 +160,7 @@
Starting udev
[ 3.464661] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.594841] random: dd urandom read with 20 bits of entropy available
[ 3.594831] random: dd urandom read with 20 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
[ 3.761487] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
[ 3.761486] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -901,10 +901,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -931,7 +930,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1058,12 +1057,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -1156,16 +1152,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1181,7 +1176,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1344,13 +1339,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1360,9 +1355,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1404,7 +1398,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1485,14 +1479,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1509,7 +1502,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1524,7 +1517,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1647,17 +1640,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1709,7 +1704,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1724,7 +1719,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

174
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr
View file

@ -11,87 +11,93 @@ warn: 12469689449500: Instruction results do not match! (Values may not actually
warn: 12469692907500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: 13858044111500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13859619440500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13859918576500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13860513270500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13897357688500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13899290842000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13920553373000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13947589978000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13980155713500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 14222638356000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14222638963500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14222639213500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14222639459500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14222639675000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14230786818000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14230787024500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14238614478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14246439816000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14246440056000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14246440571500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14246440805500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14246441035500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14246441242000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14251755692500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14251756202000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14251756436000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14251756666000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14251756872500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14258214284500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14258214514500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14258214721000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14268021442500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14268021672500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14279273428000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14279273680000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14279274189500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14279274423500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14279274653500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14279274860000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14289078760000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14289078990000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14289079196500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14304548850000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14309612929000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14309613159000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14316607744000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14316607974000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14326722373000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14326723356500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14326723586500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14326723793000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14389661684500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14389661933000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14401989619000: Instruction results do not match! (Values may not actually be integers) Inst: 0x48, checker: 0x49
warn: 14447395786500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14447396035000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14573254812500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14573344689000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14573345167500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14573345456500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14573345979000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14573347046000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14573347537500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14573347856000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574083032500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574083293500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
warn: 14574083498000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574154242500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
warn: 14574154452500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574154723500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
warn: 14574155294000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574155549500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
warn: 14574155773000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574156062000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574156571000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574157634000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574158132000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14574158434000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14623142882500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
warn: 14623143173500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14623143425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14623143670000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14623143932500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14623144171500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
warn: 13859656146500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13859950489500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13860549714500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13861141715500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13861425606000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13887655302500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13887984972000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13888175197500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13888527468000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13926855654000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13927074222000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13927622636000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13927831908000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13928069949000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13928309196000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13944831907000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 13960769373500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 14182895786500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14182896036500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14182896282500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14191041595500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14198847599000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14198848114500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14198848578500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14206625430000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14206625664000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14206625894000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14211939480000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14211939710000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14218406091500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14218406321500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14228222612500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14228222857000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14228223366500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14228223600500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14228223830500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14228224037000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14239432062500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14239432572000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14239432806000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14239433036000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14239433242500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14249200202500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14249200432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14264670876000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14264671403500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14264671637500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14264671867500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14264672074000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14269733190000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14276719950000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14276720459500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14276720693500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14276720923500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14276721130000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14286856693000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14349944433000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14349944681500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14349944897000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14407864195500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14407864763000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14407865015500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14407865264000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
warn: 14407865479500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14533528504500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14533619061000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
warn: 14533620387500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14533622455000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14533622773500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534367031000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534367292000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
warn: 14534367496500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534438304500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
warn: 14534438514500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534438785500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
warn: 14534439356000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534439611500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
warn: 14534439835000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534440124000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534440633000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534441696000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534442194000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14534442496000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
warn: 14583340343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
warn: 14583519554000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
warn: 14583519838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14583520090000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14583520334500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14583520596500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
warn: 14583520826000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:31:30
gem5 executing on e104799-lin, pid 7980
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 14:35:47
gem5 executing on e104799-lin, pid 16996
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51331535316000 because m5_exit instruction encountered
Exiting @ tick 51291805611000 because m5_exit instruction encountered

2838
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt
View file

File diff suppressed because it is too large Load diff

32
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal
View file

@ -104,13 +104,13 @@
[ 3.136841] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.136885] pci_bus 0000:00: fixups for bus
[ 3.136894] pci_bus 0000:00: bus scan returning with max=00
[ 3.136893] pci_bus 0000:00: bus scan returning with max=00
[ 3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.136925] pci 0000:00:00.0: fixup irq: got 33
[ 3.136934] pci 0000:00:00.0: assigning IRQ 33
[ 3.136933] pci 0000:00:00.0: assigning IRQ 33
[ 3.136944] pci 0000:00:01.0: fixup irq: got 34
[ 3.136952] pci 0000:00:01.0: assigning IRQ 34
[ 3.136964] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.137002] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
@ -119,17 +119,17 @@
[ 3.137036] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.137048] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.137734] ata_piix 0000:00:01.0: version 2.13
[ 3.137745] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.137769] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.138034] scsi0 : ata_piix
[ 3.138126] scsi1 : ata_piix
[ 3.138154] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.138167] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.138266] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.138278] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.138293] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.138304] e1000 0000:00:00.0: enabling bus mastering
[ 3.137735] ata_piix 0000:00:01.0: version 2.13
[ 3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.137770] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.138035] scsi0 : ata_piix
[ 3.138128] scsi1 : ata_piix
[ 3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.138306] e1000 0000:00:00.0: enabling bus mastering
[ 3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.290924] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.290951] ata1.00: configured for UDMA/33
@ -160,7 +160,7 @@
Starting udev
[ 3.450398] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.543435] random: dd urandom read with 19 bits of entropy available
[ 3.533417] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... [ 3.671120] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Configuring network interfaces... [ 3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
udhcpc (v1.21.1) started
Sending discover...
Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -1423,10 +1423,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -1453,7 +1452,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1617,12 +1616,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -1715,16 +1711,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1740,7 +1735,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1903,13 +1898,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1919,9 +1914,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1963,7 +1957,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -2044,14 +2038,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -2068,7 +2061,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -2083,7 +2076,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -2206,17 +2199,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -2268,7 +2263,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -2283,7 +2278,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

1
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simerr
View file

@ -11,4 +11,3 @@ warn: allocating bonus target for snoop
warn: allocating bonus target for snoop
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: allocating bonus target for snoop

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:32:57
gem5 executing on e104799-lin, pid 8213
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 13:59:02
gem5 executing on e104799-lin, pid 13304
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 47314506373000 because m5_exit instruction encountered
Exiting @ tick 47393980707000 because m5_exit instruction encountered

6409
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

66
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/system.terminal
View file

@ -105,62 +105,62 @@
[ 2.144312] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.144339] pci_bus 0000:00: fixups for bus
[ 2.144347] pci_bus 0000:00: bus scan returning with max=00
[ 2.144359] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.144358] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.144376] pci 0000:00:00.0: fixup irq: got 33
[ 2.144384] pci 0000:00:00.0: assigning IRQ 33
[ 2.144394] pci 0000:00:01.0: fixup irq: got 34
[ 2.144402] pci 0000:00:01.0: assigning IRQ 34
[ 2.144413] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.144426] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 2.144439] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.144438] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.144451] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.144463] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.144474] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.144462] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.144473] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.144485] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.144496] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.144948] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.145138] ata_piix 0000:00:01.0: version 2.13
[ 2.145137] ata_piix 0000:00:01.0: version 2.13
[ 2.145148] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.145170] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.145355] scsi0 : ata_piix
[ 2.145414] scsi1 : ata_piix
[ 2.145435] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.145447] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.145523] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.145535] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.145548] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.145560] e1000 0000:00:00.0: enabling bus mastering
[ 2.145169] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.145354] scsi0 : ata_piix
[ 2.145413] scsi1 : ata_piix
[ 2.145434] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.145446] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.145522] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.145534] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.145547] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.145559] e1000 0000:00:00.0: enabling bus mastering
[ 2.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.290714] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290739] ata1.00: configured for UDMA/33
[ 2.290783] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.290882] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.290916] sd 0:0:0:0: [sda] Write Protect is off
[ 2.290925] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.290941] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.290995] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.291062] sda: sda1
[ 2.291150] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.290784] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.290883] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.290917] sd 0:0:0:0: [sda] Write Protect is off
[ 2.290926] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.290943] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.290996] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.291064] sda: sda1
[ 2.291152] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.410949] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.410962] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.410980] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.410990] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.411008] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.411020] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.411069] usbcore: registered new interface driver usb-storage
[ 2.411117] mousedev: PS/2 mouse device common for all mice
[ 2.411224] usbcore: registered new interface driver usbhid
[ 2.411234] usbhid: USB HID core driver
[ 2.411259] TCP: cubic registered
[ 2.411070] usbcore: registered new interface driver usb-storage
[ 2.411118] mousedev: PS/2 mouse device common for all mice
[ 2.411225] usbcore: registered new interface driver usbhid
[ 2.411235] usbhid: USB HID core driver
[ 2.411260] TCP: cubic registered
[ 2.411267] NET: Registered protocol family 17
[ 2.411574] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.411614] devtmpfs: mounted
[ 2.411651] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
[ 2.411579] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.411619] devtmpfs: mounted
[ 2.411656] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 2.447825] udevd[609]: starting version 182
[ 2.447817] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 2.512686] random: dd urandom read with 18 bits of entropy available
[ 2.532679] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
[ 2.620897] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
[ 2.640899] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -749,10 +749,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -779,7 +778,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -906,12 +905,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -1004,16 +1000,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1029,7 +1024,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1192,13 +1187,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1208,9 +1203,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1252,7 +1246,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1333,14 +1327,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1357,7 +1350,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1372,7 +1365,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1495,17 +1488,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1557,7 +1552,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1572,7 +1567,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:31:16
gem5 executing on e104799-lin, pid 7932
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 11:54:11
gem5 executing on e104799-lin, pid 641
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51331535316000 because m5_exit instruction encountered
Exiting @ tick 51291805611000 because m5_exit instruction encountered

2738
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

32
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/system.terminal
View file

@ -104,13 +104,13 @@
[ 3.136841] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.136852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.136885] pci_bus 0000:00: fixups for bus
[ 3.136894] pci_bus 0000:00: bus scan returning with max=00
[ 3.136893] pci_bus 0000:00: bus scan returning with max=00
[ 3.136906] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.136925] pci 0000:00:00.0: fixup irq: got 33
[ 3.136934] pci 0000:00:00.0: assigning IRQ 33
[ 3.136933] pci 0000:00:00.0: assigning IRQ 33
[ 3.136944] pci 0000:00:01.0: fixup irq: got 34
[ 3.136952] pci 0000:00:01.0: assigning IRQ 34
[ 3.136964] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.136963] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.136976] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.136989] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.137002] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
@ -119,17 +119,17 @@
[ 3.137036] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.137048] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.137493] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.137734] ata_piix 0000:00:01.0: version 2.13
[ 3.137745] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.137769] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.138034] scsi0 : ata_piix
[ 3.138126] scsi1 : ata_piix
[ 3.138154] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.138167] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.138266] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.138278] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.138293] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.138304] e1000 0000:00:00.0: enabling bus mastering
[ 3.137735] ata_piix 0000:00:01.0: version 2.13
[ 3.137746] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.137770] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.138035] scsi0 : ata_piix
[ 3.138128] scsi1 : ata_piix
[ 3.138156] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.138168] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.138267] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.138279] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.138294] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.138306] e1000 0000:00:00.0: enabling bus mastering
[ 3.290915] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.290924] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.290951] ata1.00: configured for UDMA/33
@ -160,7 +160,7 @@
Starting udev
[ 3.450398] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.543435] random: dd urandom read with 19 bits of entropy available
[ 3.533417] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -168,7 +168,7 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... [ 3.671120] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Configuring network interfaces... [ 3.661125] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
udhcpc (v1.21.1) started
Sending discover...
Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -419,10 +419,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -449,7 +448,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -512,12 +511,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -610,16 +606,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -635,7 +630,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -798,13 +793,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -814,9 +809,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -858,7 +852,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -939,14 +933,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -963,7 +956,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -978,7 +971,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1101,17 +1094,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1163,7 +1158,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1178,7 +1173,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

123
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json
View file

@ -19,10 +19,6 @@
"role": "SLAVE"
},
"name": "iobus",
"default": {
"peer": "system.realview.pciconfig.pio",
"role": "MASTER"
},
"forward_latency": 1,
"clk_domain": "system.clk_domain",
"width": 16,
@ -31,6 +27,7 @@
"peer": [
"system.realview.uart.pio",
"system.realview.realview_io.pio",
"system.realview.pci_host.pio",
"system.realview.timer0.pio",
"system.realview.timer1.pio",
"system.realview.clcd.pio",
@ -38,7 +35,6 @@
"system.realview.kmi0.pio",
"system.realview.kmi1.pio",
"system.realview.cf_ctrl.pio",
"system.realview.cf_ctrl.config",
"system.realview.rtc.pio",
"system.realview.vram.port",
"system.realview.l2x0_fake.pio",
@ -53,9 +49,7 @@
"system.realview.mmc_fake.pio",
"system.realview.energy_ctrl.pio",
"system.realview.ide.pio",
"system.realview.ide.config",
"system.realview.ethernet.pio",
"system.realview.ethernet.config",
"system.iocache.cpu_side"
],
"role": "MASTER"
@ -64,11 +58,11 @@
"cxx_class": "NoncoherentXBar",
"path": "system.iobus",
"type": "NoncoherentXBar",
"use_default_range": true,
"use_default_range": false,
"frontend_latency": 2
},
"symbolfile": "",
"readfile": "/work/gem5/outgoing/gem5/tests/halt.sh",
"readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh",
"have_large_asid_64": false,
"phys_addr_range_64": 40,
"have_lpae": false,
@ -115,7 +109,7 @@
"workaround_dma_line_count": true,
"amba_id": 1314816,
"pio": {
"peer": "system.iobus.master[5]",
"peer": "system.iobus.master[6]",
"role": "SLAVE"
},
"pio_latency": 10000,
@ -174,7 +168,23 @@
"pio_addr": 471269376,
"type": "PL031"
},
"pci_cfg_gen_offsets": true,
"watchdog_fake": {
"name": "watchdog_fake",
"pio": {
"peer": "system.iobus.master[17]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.watchdog_fake",
"pio_addr": 470745088,
"type": "AmbaFake"
},
"vgic": {
"system": "system",
"name": "vgic",
@ -348,7 +358,7 @@
"timer1": {
"name": "timer1",
"pio": {
"peer": "system.iobus.master[3]",
"peer": "system.iobus.master[4]",
"role": "SLAVE"
},
"amba_id": 1316868,
@ -369,7 +379,7 @@
"timer0": {
"name": "timer0",
"pio": {
"peer": "system.iobus.master[2]",
"peer": "system.iobus.master[3]",
"role": "SLAVE"
},
"amba_id": 1316868,
@ -422,6 +432,26 @@
"pio_addr": 470286336
},
"type": "RealView",
"pci_host": {
"conf_size": 268435456,
"name": "pci_host",
"conf_device_bits": 12,
"pio": {
"peer": "system.iobus.master[2]",
"role": "SLAVE"
},
"conf_base": 805306368,
"clk_domain": "system.clk_domain",
"system": "system",
"pci_dma_base": 0,
"platform": "system.realview",
"eventq_index": 0,
"cxx_class": "GenericPciHost",
"path": "system.realview.pci_host",
"pci_pio_base": 788529152,
"type": "GenericPciHost",
"pci_mem_base": 0
},
"lan_fake": {
"system": "system",
"ret_data8": 255,
@ -617,25 +647,6 @@
"type": "RealViewOsc"
}
},
"pciconfig": {
"name": "pciconfig",
"pio": {
"peer": "system.iobus.default",
"role": "SLAVE"
},
"bus": 0,
"pio_latency": 30000,
"clk_domain": "system.clk_domain",
"system": "system",
"platform": "system.realview",
"eventq_index": 0,
"cxx_class": "PciConfigAll",
"path": "system.realview.pciconfig",
"pio_addr": 0,
"type": "PciConfigAll",
"size": 268435456
},
"pci_cfg_base": 805306368,
"path": "system.realview",
"vram": {
"range": "402653184:436207615",
@ -656,7 +667,6 @@
},
"in_addr_map": true
},
"pci_io_base": 788529152,
"nvmem": {
"range": "0:67108863",
"latency": 30000,
@ -685,7 +695,7 @@
"vnc": "system.vncserver",
"name": "clcd",
"pio": {
"peer": "system.iobus.master[4]",
"peer": "system.iobus.master[5]",
"role": "SLAVE"
},
"amba_id": 1315089,
@ -723,30 +733,13 @@
"pio_addr": 470351872,
"type": "Pl011"
},
"watchdog_fake": {
"name": "watchdog_fake",
"pio": {
"peer": "system.iobus.master[17]",
"role": "SLAVE"
},
"amba_id": 0,
"ignore_access": false,
"pio_latency": 100000,
"clk_domain": "system.clk_domain",
"system": "system",
"eventq_index": 0,
"cxx_class": "AmbaFake",
"path": "system.realview.watchdog_fake",
"pio_addr": 470745088,
"type": "AmbaFake"
},
"intrctrl": "system.intrctrl",
"kmi1": {
"vnc": "system.vncserver",
"name": "kmi1",
"int_delay": 1000000,
"pio": {
"peer": "system.iobus.master[7]",
"peer": "system.iobus.master[8]",
"role": "SLAVE"
},
"amba_id": 1314896,
@ -767,7 +760,7 @@
"name": "kmi0",
"int_delay": 1000000,
"pio": {
"peer": "system.iobus.master[6]",
"peer": "system.iobus.master[7]",
"role": "SLAVE"
},
"amba_id": 1314896,
@ -794,7 +787,6 @@
"Revision": 0,
"LegacyIOBase": 0,
"pio_latency": 30000,
"platform": "system.realview",
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
@ -828,6 +820,7 @@
"PXCAPDevCap2": 0,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"host": "system.realview.pci_host",
"Command": 1,
"SubClassCode": 1,
"pci_func": 0,
@ -862,7 +855,7 @@
"config_latency": 20000,
"BAR1Size": 4096,
"pio": {
"peer": "system.iobus.master[8]",
"peer": "system.iobus.master[9]",
"role": "SLAVE"
},
"pci_dev": 0,
@ -871,10 +864,6 @@
"clk_domain": "system.clk_domain",
"SubsystemVendorID": 0,
"PMCAPBaseOffset": 0,
"config": {
"peer": "system.iobus.master[9]",
"role": "SLAVE"
},
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
@ -914,7 +903,6 @@
"hardware_address": "00:90:00:00:00:01",
"LegacyIOBase": 0,
"pio_latency": 30000,
"platform": "system.realview",
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
@ -949,6 +937,7 @@
"PXCAPDevCap2": 0,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"host": "system.realview.pci_host",
"Command": 0,
"SubClassCode": 0,
"pci_func": 0,
@ -986,7 +975,7 @@
"config_latency": 20000,
"BAR1Size": 0,
"pio": {
"peer": "system.iobus.master[25]",
"peer": "system.iobus.master[24]",
"role": "SLAVE"
},
"pci_dev": 0,
@ -997,10 +986,6 @@
"clk_domain": "system.clk_domain",
"SubsystemVendorID": 32902,
"PMCAPBaseOffset": 0,
"config": {
"peer": "system.iobus.master[26]",
"role": "SLAVE"
},
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
@ -1025,7 +1010,6 @@
"Revision": 0,
"LegacyIOBase": 0,
"pio_latency": 30000,
"platform": "system.realview",
"PXCAPLinkCap": 0,
"CapabilityPtr": 0,
"MSIXCAPBaseOffset": 0,
@ -1061,6 +1045,7 @@
"PXCAPDevCap2": 0,
"PXCAPDevCtrl": 0,
"MSICAPMaskBits": 0,
"host": "system.realview.pci_host",
"Command": 0,
"SubClassCode": 1,
"pci_func": 0,
@ -1104,10 +1089,6 @@
"clk_domain": "system.clk_domain",
"SubsystemVendorID": 0,
"PMCAPBaseOffset": 0,
"config": {
"peer": "system.iobus.master[24]",
"role": "SLAVE"
},
"MSICAPPendingBits": 0,
"MSIXTableOffset": 0,
"MSICAPMsgUpperAddr": 0,
@ -1187,7 +1168,7 @@
"eventq_index": 0,
"iocache": {
"cpu_side": {
"peer": "system.iobus.master[27]",
"peer": "system.iobus.master[25]",
"role": "SLAVE"
},
"clusivity": "mostly_incl",

18
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 436679 # Simulator instruction rate (inst/s)
host_op_rate 513170 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 22668960410 # Simulator tick rate (ticks/s)
host_mem_usage 677940 # Number of bytes of host memory used
host_seconds 2254.68 # Real time elapsed on the host
host_inst_rate 966487 # Simulator instruction rate (inst/s)
host_op_rate 1135781 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 50172400532 # Simulator tick rate (ticks/s)
host_mem_usage 679768 # Number of bytes of host memory used
host_seconds 1018.71 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -610,6 +610,7 @@ system.iobus.trans_dist::WriteReq 136515 # Tr
system.iobus.trans_dist::WriteResp 136515 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
@ -619,10 +620,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
@ -631,6 +629,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total 80
system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
@ -640,10 +639,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -763,10 +763,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -793,7 +792,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -893,12 +892,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -991,16 +987,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1016,7 +1011,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1179,13 +1174,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1195,9 +1190,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1239,7 +1233,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1320,14 +1314,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1344,7 +1337,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1359,7 +1352,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1482,17 +1475,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1544,7 +1539,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1559,7 +1554,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 19:23:36
gem5 executing on e104799-lin, pid 15250
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 13:36:23
gem5 executing on e104799-lin, pid 11118
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second

18
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 47.216814 # Nu
sim_ticks 47216814145000 # Number of ticks simulated
final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 564335 # Simulator instruction rate (inst/s)
host_op_rate 663890 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 27316522801 # Simulator tick rate (ticks/s)
host_mem_usage 691236 # Number of bytes of host memory used
host_seconds 1728.51 # Real time elapsed on the host
host_inst_rate 919960 # Simulator instruction rate (inst/s)
host_op_rate 1082251 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 44530469299 # Simulator tick rate (ticks/s)
host_mem_usage 691012 # Number of bytes of host memory used
host_seconds 1060.33 # Real time elapsed on the host
sim_insts 975457230 # Number of instructions simulated
sim_ops 1147538415 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -1178,6 +1178,7 @@ system.iobus.trans_dist::WriteReq 136634 # Tr
system.iobus.trans_dist::WriteResp 136634 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
@ -1187,10 +1188,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
@ -1199,6 +1197,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total 80
system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
@ -1208,10 +1207,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -419,10 +419,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -449,7 +448,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -512,12 +511,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -610,16 +606,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -635,7 +630,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -798,13 +793,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -814,9 +809,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -858,7 +852,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -939,14 +933,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -963,7 +956,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -978,7 +971,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1101,17 +1094,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1163,7 +1158,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1178,7 +1173,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 18:43:21
gem5 executing on e104799-lin, pid 8676
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 14:02:50
gem5 executing on e104799-lin, pid 13724
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second

18
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 940801 # Simulator instruction rate (inst/s)
host_op_rate 1105595 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 48838957578 # Simulator tick rate (ticks/s)
host_mem_usage 678172 # Number of bytes of host memory used
host_seconds 1046.52 # Real time elapsed on the host
host_inst_rate 958498 # Simulator instruction rate (inst/s)
host_op_rate 1126393 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 49757685011 # Simulator tick rate (ticks/s)
host_mem_usage 676912 # Number of bytes of host memory used
host_seconds 1027.20 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -610,6 +610,7 @@ system.iobus.trans_dist::WriteReq 136515 # Tr
system.iobus.trans_dist::WriteResp 136515 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
@ -619,10 +620,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
@ -631,6 +629,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total 80
system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
@ -640,10 +639,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -755,10 +755,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -785,7 +784,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -949,12 +948,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -1047,16 +1043,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1072,7 +1067,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1235,13 +1230,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1251,9 +1246,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1295,7 +1289,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1376,14 +1370,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1400,7 +1393,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1415,7 +1408,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1538,17 +1531,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1600,7 +1595,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1615,7 +1610,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 19:52:38
gem5 executing on e104799-lin, pid 27835
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 11:53:35
gem5 executing on e104799-lin, pid 548
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 47602567962500 because m5_exit instruction encountered
Exiting @ tick 47593744171500 because m5_exit instruction encountered

5191
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
View file

File diff suppressed because it is too large Load diff

71
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal
View file

@ -104,10 +104,10 @@
[ 2.139655] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 2.139667] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.139709] pci_bus 0000:00: fixups for bus
[ 2.139718] pci_bus 0000:00: bus scan returning with max=00
[ 2.139717] pci_bus 0000:00: bus scan returning with max=00
[ 2.139730] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.139753] pci 0000:00:00.0: fixup irq: got 33
[ 2.139762] pci 0000:00:00.0: assigning IRQ 33
[ 2.139752] pci 0000:00:00.0: fixup irq: got 33
[ 2.139761] pci 0000:00:00.0: assigning IRQ 33
[ 2.139773] pci 0000:00:01.0: fixup irq: got 34
[ 2.139782] pci 0000:00:01.0: assigning IRQ 34
[ 2.139794] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
@ -116,51 +116,51 @@
[ 2.139835] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.139847] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.139859] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.139871] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.139883] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.139870] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.139882] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.140477] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.140811] ata_piix 0000:00:01.0: version 2.13
[ 2.140822] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.140865] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.141220] scsi0 : ata_piix
[ 2.141324] scsi1 : ata_piix
[ 2.141362] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.141375] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.141526] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.141538] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.141554] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.141566] e1000 0000:00:00.0: enabling bus mastering
[ 2.140812] ata_piix 0000:00:01.0: version 2.13
[ 2.140823] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.140866] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.141222] scsi0 : ata_piix
[ 2.141325] scsi1 : ata_piix
[ 2.141364] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.141376] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.141528] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.141540] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.141556] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.141568] e1000 0000:00:00.0: enabling bus mastering
[ 2.301209] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.301219] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.301220] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.301250] ata1.00: configured for UDMA/33
[ 2.301329] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.301473] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.301485] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.301561] sd 0:0:0:0: [sda] Write Protect is off
[ 2.301570] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.301591] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.301765] sda: sda1
[ 2.301899] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.301486] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.301562] sd 0:0:0:0: [sda] Write Protect is off
[ 2.301571] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.301592] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.301766] sda: sda1
[ 2.301900] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.421494] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.421508] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.421532] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.421533] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.421543] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.421566] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.421578] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.421668] usbcore: registered new interface driver usb-storage
[ 2.421737] mousedev: PS/2 mouse device common for all mice
[ 2.421933] usbcore: registered new interface driver usbhid
[ 2.421567] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.421579] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.421669] usbcore: registered new interface driver usb-storage
[ 2.421738] mousedev: PS/2 mouse device common for all mice
[ 2.421934] usbcore: registered new interface driver usbhid
[ 2.421944] usbhid: USB HID core driver
[ 2.421984] TCP: cubic registered
[ 2.421992] NET: Registered protocol family 17
[ 2.422476] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.422517] devtmpfs: mounted
[ 2.422651] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
[ 2.422478] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.422519] devtmpfs: mounted
[ 2.422652] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 2.463113] udevd[609]: starting version 182
[ 2.463118] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 2.544458] random: dd urandom read with 18 bits of entropy available
[ 2.544444] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
[ 2.681395] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
[ 2.681396] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
@ -181,4 +181,3 @@ rpcbind: cannot get uid of '': Success
done.
creating NFS state directory: done
starting statd: done
Starting auto-serial-console: done

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -415,10 +415,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -445,7 +444,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -572,12 +571,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -670,16 +666,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -695,7 +690,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -858,13 +853,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -874,9 +869,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -918,7 +912,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -999,14 +993,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1023,7 +1016,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1038,7 +1031,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1161,17 +1154,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1223,7 +1218,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1238,7 +1233,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

10
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 19:39:30
gem5 executing on e104799-lin, pid 27757
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 14:13:19
gem5 executing on e104799-lin, pid 14780
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
@ -13,4 +13,4 @@ info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51811412441500 because m5_exit instruction encountered
Exiting @ tick 51811415265500 because m5_exit instruction encountered

2126
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

30
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal
View file

@ -110,26 +110,26 @@
[ 3.145140] pci 0000:00:00.0: assigning IRQ 33
[ 3.145154] pci 0000:00:01.0: fixup irq: got 34
[ 3.145164] pci 0000:00:01.0: assigning IRQ 34
[ 3.145179] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.145194] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.145178] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.145193] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.145208] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.145223] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.145222] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.145236] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.145249] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.145263] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.145262] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.145276] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.146194] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.146723] ata_piix 0000:00:01.0: version 2.13
[ 3.146724] ata_piix 0000:00:01.0: version 2.13
[ 3.146736] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.146781] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.147382] scsi0 : ata_piix
[ 3.147567] scsi1 : ata_piix
[ 3.147621] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.147634] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.147838] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.147851] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.147874] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.147887] e1000 0000:00:00.0: enabling bus mastering
[ 3.147384] scsi0 : ata_piix
[ 3.147568] scsi1 : ata_piix
[ 3.147622] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.147635] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.147840] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.147853] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.147876] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.147889] e1000 0000:00:00.0: enabling bus mastering
[ 3.301640] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.301651] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.301686] ata1.00: configured for UDMA/33
@ -160,7 +160,7 @@
Starting udev
[ 3.470418] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.586550] random: dd urandom read with 21 bits of entropy available
[ 3.586551] random: dd urandom read with 21 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
[ 3.791839] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
[ 3.791840] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -511,10 +511,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -541,7 +540,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -641,12 +640,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -739,16 +735,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -764,7 +759,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -927,13 +922,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -943,9 +938,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -987,7 +981,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1068,14 +1062,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1092,7 +1085,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1107,7 +1100,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1230,17 +1223,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1292,7 +1287,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1307,7 +1302,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 20:01:11
gem5 executing on e104799-lin, pid 27942
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 12:10:26
gem5 executing on e104799-lin, pid 2423
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second

18
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
View file

@ -4,11 +4,11 @@ sim_seconds 51.111153 # Nu
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 987530 # Simulator instruction rate (inst/s)
host_op_rate 1160510 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51264798094 # Simulator tick rate (ticks/s)
host_mem_usage 676380 # Number of bytes of host memory used
host_seconds 997.00 # Real time elapsed on the host
host_inst_rate 965225 # Simulator instruction rate (inst/s)
host_op_rate 1134298 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 50106889543 # Simulator tick rate (ticks/s)
host_mem_usage 675900 # Number of bytes of host memory used
host_seconds 1020.04 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@ -682,6 +682,7 @@ system.iobus.trans_dist::WriteReq 136515 # Tr
system.iobus.trans_dist::WriteResp 136515 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
@ -691,10 +692,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
@ -703,6 +701,7 @@ system.iobus.pkt_count_system.realview.ethernet.dma::total 80
system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
@ -712,10 +711,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -1612,10 +1612,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -1642,7 +1641,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1806,12 +1805,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -1904,16 +1900,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1929,7 +1924,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -2092,13 +2087,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -2108,9 +2103,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -2152,7 +2146,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -2233,14 +2227,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -2257,7 +2250,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -2272,7 +2265,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -2395,17 +2388,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -2457,7 +2452,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -2472,7 +2467,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

1580
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
View file

File diff suppressed because it is too large Load diff

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 20:04:32
gem5 executing on e104799-lin, pid 27965
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 13:54:27
gem5 executing on e104799-lin, pid 12846
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second

5143
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
View file

File diff suppressed because it is too large Load diff

24
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
View file

@ -103,33 +103,33 @@
[ 3.136511] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.136524] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.136537] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.136598] pci_bus 0000:00: fixups for bus
[ 3.136597] pci_bus 0000:00: fixups for bus
[ 3.136607] pci_bus 0000:00: bus scan returning with max=00
[ 3.136622] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.136649] pci 0000:00:00.0: fixup irq: got 33
[ 3.136659] pci 0000:00:00.0: assigning IRQ 33
[ 3.136673] pci 0000:00:01.0: fixup irq: got 34
[ 3.136683] pci 0000:00:01.0: assigning IRQ 34
[ 3.136672] pci 0000:00:01.0: fixup irq: got 34
[ 3.136682] pci 0000:00:01.0: assigning IRQ 34
[ 3.136697] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.136712] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.136726] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.136739] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.136751] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.136764] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.136776] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.136788] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.136763] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.136775] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.136787] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.137187] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.137353] ata_piix 0000:00:01.0: version 2.13
[ 3.137355] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.137360] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.137757] scsi0 : ata_piix
[ 3.137894] scsi1 : ata_piix
[ 3.137933] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.137932] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.137945] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.138020] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.138032] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.138031] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.138045] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.138056] e1000 0000:00:00.0: enabling bus mastering
[ 3.138055] e1000 0000:00:00.0: enabling bus mastering
[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.290901] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.290907] ata1.00: configured for UDMA/33
@ -158,9 +158,9 @@
[ 3.411950] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 3.450205] udevd[607]: starting version 182
[ 3.450204] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.533179] random: dd urandom read with 19 bits of entropy available
[ 3.543300] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
[ 3.671115] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
[ 3.681115] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -1261,10 +1261,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -1291,7 +1290,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -1455,12 +1454,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -1553,16 +1549,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -1578,7 +1573,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -1741,13 +1736,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -1757,9 +1752,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1801,7 +1795,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1882,14 +1876,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1906,7 +1899,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1921,7 +1914,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -2044,17 +2037,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -2106,7 +2101,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -2121,7 +2116,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

80
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr
View file

@ -461,3 +461,83 @@ warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 20:08:05
gem5 executing on e104799-lin, pid 28085
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 14:20:09
gem5 executing on e104799-lin, pid 15456
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second

4372
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
View file

File diff suppressed because it is too large Load diff

34
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal
View file

@ -106,15 +106,15 @@
[ 3.135048] pci_bus 0000:00: fixups for bus
[ 3.135056] pci_bus 0000:00: bus scan returning with max=00
[ 3.135067] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.135084] pci 0000:00:00.0: fixup irq: got 33
[ 3.135092] pci 0000:00:00.0: assigning IRQ 33
[ 3.135083] pci 0000:00:00.0: fixup irq: got 33
[ 3.135091] pci 0000:00:00.0: assigning IRQ 33
[ 3.135101] pci 0000:00:01.0: fixup irq: got 34
[ 3.135109] pci 0000:00:01.0: assigning IRQ 34
[ 3.135108] pci 0000:00:01.0: assigning IRQ 34
[ 3.135119] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.135131] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.135144] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.135143] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.135156] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.135167] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.135166] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.135177] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.135188] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.135199] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
@ -123,7 +123,7 @@
[ 3.135708] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.135730] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.135914] scsi0 : ata_piix
[ 3.135984] scsi1 : ata_piix
[ 3.135983] scsi1 : ata_piix
[ 3.136005] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.136017] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.136090] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
@ -133,9 +133,9 @@
[ 3.290704] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.290713] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.290737] ata1.00: configured for UDMA/33
[ 3.290779] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 3.290857] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 3.290877] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 3.290778] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 3.290856] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 3.290876] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 3.290908] sd 0:0:0:0: [sda] Write Protect is off
[ 3.290916] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.290933] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
@ -143,24 +143,24 @@
[ 3.291104] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.410957] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 3.410969] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 3.410986] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.410996] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.411012] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.410987] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.410997] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.411013] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.411024] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.411070] usbcore: registered new interface driver usb-storage
[ 3.411110] mousedev: PS/2 mouse device common for all mice
[ 3.411111] mousedev: PS/2 mouse device common for all mice
[ 3.411211] usbcore: registered new interface driver usbhid
[ 3.411220] usbhid: USB HID core driver
[ 3.411245] TCP: cubic registered
[ 3.411252] NET: Registered protocol family 17
[ 3.411253] NET: Registered protocol family 17
[ 3.411504] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 3.411533] devtmpfs: mounted
[ 3.411579] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 3.448025] udevd[607]: starting version 182
[ 3.448034] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.532647] random: dd urandom read with 19 bits of entropy available
[ 3.532645] random: dd urandom read with 19 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
[ 3.650912] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
[ 3.650911] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...

55
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
View file

@ -43,7 +43,7 @@ num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5/outgoing/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@ -503,10 +503,9 @@ eventq_index=0
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
use_default_range=false
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
[system.iocache]
@ -533,7 +532,7 @@ tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.iobus.master[27]
cpu_side=system.iobus.master[25]
mem_side=system.membus.slave[3]
[system.iocache.tags]
@ -697,12 +696,9 @@ port=system.membus.master[5]
[system.realview]
type=RealView
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
eventq_index=0
intrctrl=system.intrctrl
pci_cfg_base=805306368
pci_cfg_gen_offsets=true
pci_io_base=788529152
system=system
[system.realview.aaci_fake]
@ -795,16 +791,15 @@ config_latency=20000
ctrl_offset=2
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[9]
dma=system.iobus.slave[2]
pio=system.iobus.master[8]
pio=system.iobus.master[9]
[system.realview.clcd]
type=Pl111
@ -820,7 +815,7 @@ pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
pio=system.iobus.master[4]
pio=system.iobus.master[5]
[system.realview.dcc]
type=SubSystem
@ -983,13 +978,13 @@ eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
platform=system.realview
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@ -999,9 +994,8 @@ tx_fifo_size=393216
tx_read_delay=0
wb_comp_delay=10000
wb_delay=10000
config=system.iobus.master[26]
dma=system.iobus.slave[4]
pio=system.iobus.master[25]
pio=system.iobus.master[24]
[system.realview.generic_timer]
type=GenericTimer
@ -1043,7 +1037,7 @@ vnc=system.vncserver
workaround_dma_line_count=true
workaround_swap_rb=true
dma=system.membus.slave[0]
pio=system.iobus.master[5]
pio=system.iobus.master[6]
[system.realview.ide]
type=IdeController
@ -1124,14 +1118,13 @@ config_latency=20000
ctrl_offset=0
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.realview
system=system
config=system.iobus.master[24]
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@ -1148,7 +1141,7 @@ pio_addr=470155264
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[6]
pio=system.iobus.master[7]
[system.realview.kmi1]
type=Pl050
@ -1163,7 +1156,7 @@ pio_addr=470220800
pio_latency=100000
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
@ -1286,17 +1279,19 @@ null=false
range=0:67108863
port=system.membus.master[1]
[system.realview.pciconfig]
type=PciConfigAll
bus=0
[system.realview.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
size=268435456
system=system
pio=system.iobus.default
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
@ -1348,7 +1343,7 @@ int_num1=34
pio_addr=470876160
pio_latency=100000
system=system
pio=system.iobus.master[2]
pio=system.iobus.master[3]
[system.realview.timer1]
type=Sp804
@ -1363,7 +1358,7 @@ int_num1=35
pio_addr=470941696
pio_latency=100000
system=system
pio=system.iobus.master[3]
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011

48
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
View file

@ -1505,51 +1505,3 @@ warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout
View file

@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Dec 3 2015 15:48:05
gem5 started Dec 3 2015 20:16:56
gem5 executing on e104799-lin, pid 28142
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
gem5 compiled Dec 4 2015 11:13:17
gem5 started Dec 4 2015 11:31:31
gem5 executing on e104799-lin, pid 30776
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second

3137
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

18
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal
View file

@ -104,7 +104,7 @@
[ 3.145027] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.145041] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.145103] pci_bus 0000:00: fixups for bus
[ 3.145113] pci_bus 0000:00: bus scan returning with max=00
[ 3.145112] pci_bus 0000:00: bus scan returning with max=00
[ 3.145127] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.145154] pci 0000:00:00.0: fixup irq: got 33
[ 3.145164] pci 0000:00:00.0: assigning IRQ 33
@ -113,19 +113,19 @@
[ 3.145202] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.145217] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.145232] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.145247] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.145246] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.145260] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.145273] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.145286] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.145300] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.146217] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.146746] ata_piix 0000:00:01.0: version 2.13
[ 3.146758] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.146802] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.147407] scsi0 : ata_piix
[ 3.146216] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.146745] ata_piix 0000:00:01.0: version 2.13
[ 3.146757] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.146801] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.147406] scsi0 : ata_piix
[ 3.147592] scsi1 : ata_piix
[ 3.147648] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.147662] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.147661] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.147864] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.147877] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.147899] e1000 0000:00:00.0: enabling device (0000 -> 0002)
@ -158,7 +158,7 @@
[ 3.423483] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 3.470486] udevd[607]: starting version 182
[ 3.470485] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.586582] random: dd urandom read with 21 bits of entropy available
Populating dev cache

84
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
View file

@ -20,7 +20,7 @@ eventq_index=0
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
@ -28,8 +28,9 @@ mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
@ -207,6 +208,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -223,6 +225,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@ -257,6 +260,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
@ -273,6 +277,7 @@ system=system
tags=system.cpu.dtb_walker_cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dtb.walker.port
mem_side=system.cpu.toL2Bus.slave[3]
@ -599,6 +604,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -615,6 +621,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@ -665,6 +672,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
@ -681,6 +689,7 @@ system=system
tags=system.cpu.itb_walker_cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.itb.walker.port
mem_side=system.cpu.toL2Bus.slave[2]
@ -700,6 +709,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
@ -716,6 +726,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[2]
@ -731,12 +742,13 @@ size=4194304
[system.cpu.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@ -744,6 +756,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
[system.cpu.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@ -1197,8 +1216,8 @@ frontend_latency=2
response_latency=2
use_default_range=false
width=16
default=system.pc.pciconfig.pio
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
default=system.pc.pci_host.pio
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
[system.iocache]
@ -1207,6 +1226,7 @@ children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
@ -1223,7 +1243,8 @@ system=system
tags=system.iocache.tags
tgts_per_mshr=12
write_buffers=8
cpu_side=system.iobus.master[19]
writeback_clean=false
cpu_side=system.iobus.master[18]
mem_side=system.membus.slave[4]
[system.iocache.tags]
@ -1273,7 +1294,7 @@ pio=system.membus.default
[system.pc]
type=Pc
children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge
children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
eventq_index=0
intrctrl=system.intrctrl
system=system
@ -1294,7 +1315,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[13]
pio=system.iobus.master[12]
[system.pc.com_1]
type=Uart8250
@ -1306,7 +1327,7 @@ pio_latency=100000
platform=system.pc
system=system
terminal=system.pc.com_1.terminal
pio=system.iobus.master[14]
pio=system.iobus.master[13]
[system.pc.com_1.terminal]
type=Terminal
@ -1332,7 +1353,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[15]
pio=system.iobus.master[14]
[system.pc.fake_com_3]
type=IsaFake
@ -1350,7 +1371,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[16]
pio=system.iobus.master[15]
[system.pc.fake_com_4]
type=IsaFake
@ -1368,7 +1389,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[17]
pio=system.iobus.master[16]
[system.pc.fake_floppy]
type=IsaFake
@ -1386,7 +1407,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[18]
pio=system.iobus.master[17]
[system.pc.i_dont_exist1]
type=IsaFake
@ -1404,7 +1425,7 @@ ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[11]
pio=system.iobus.master[10]
[system.pc.i_dont_exist2]
type=IsaFake
@ -1422,17 +1443,19 @@ ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[12]
pio=system.iobus.master[11]
[system.pc.pciconfig]
type=PciConfigAll
bus=0
[system.pc.pci_host]
type=GenericPciHost
clk_domain=system.clk_domain
conf_base=13835058055282163712
conf_device_bits=8
conf_size=16777216
eventq_index=0
pio_addr=0
pio_latency=30000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=9223372036854775808
platform=system.pc
size=16777216
system=system
pio=system.iobus.default
@ -1555,14 +1578,13 @@ config_latency=20000
ctrl_offset=0
disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
eventq_index=0
host=system.pc.pci_host
io_shift=0
pci_bus=0
pci_dev=4
pci_func=0
pio_latency=30000
platform=system.pc
system=system
config=system.iobus.master[4]
dma=system.iobus.slave[1]
pio=system.iobus.master[3]
@ -1586,7 +1608,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
image_file=/work/gem5/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@ -1609,7 +1631,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
image_file=/work/gem5/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
@ -1714,7 +1736,7 @@ pio_addr=4273995776
pio_latency=100000
system=system
int_master=system.iobus.slave[2]
pio=system.iobus.master[10]
pio=system.iobus.master[9]
[system.pc.south_bridge.keyboard]
type=I8042
@ -1728,7 +1750,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0
pio_latency=100000
system=system
pio=system.iobus.master[5]
pio=system.iobus.master[4]
[system.pc.south_bridge.keyboard.keyboard_int_pin]
type=X86IntSourcePin
@ -1749,7 +1771,7 @@ pio_addr=9223372036854775840
pio_latency=100000
slave=system.pc.south_bridge.pic2
system=system
pio=system.iobus.master[6]
pio=system.iobus.master[5]
[system.pc.south_bridge.pic1.output]
type=X86IntSourcePin
@ -1766,7 +1788,7 @@ pio_addr=9223372036854775968
pio_latency=100000
slave=Null
system=system
pio=system.iobus.master[7]
pio=system.iobus.master[6]
[system.pc.south_bridge.pic2.output]
type=X86IntSourcePin
@ -1781,7 +1803,7 @@ int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872
pio_latency=100000
system=system
pio=system.iobus.master[8]
pio=system.iobus.master[7]
[system.pc.south_bridge.pit.int_pin]
type=X86IntSourcePin
@ -1795,7 +1817,7 @@ i8254=system.pc.south_bridge.pit
pio_addr=9223372036854775905
pio_latency=100000
system=system
pio=system.iobus.master[9]
pio=system.iobus.master[8]
[system.physmem]
type=DRAMCtrl

10
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -1,13 +1,13 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jul 6 2015 14:29:04
gem5 started Jul 6 2015 20:46:38
gem5 executing on e104799-lin
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5/outgoing/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
gem5 compiled Dec 4 2015 15:10:31
gem5 started Dec 4 2015 15:13:28
gem5 executing on e104799-lin, pid 29885
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5130108675000 because m5_exit instruction encountered
Exiting @ tick 5144274809000 because m5_exit instruction encountered

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