stats: Update stats to reflect changes to cache and crossbar
This commit is contained in:
Andreas Hansson
parent
83a5977481
commit
c6cede244b
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@ -4,11 +4,11 @@ sim_seconds 5.221334 # Nu
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sim_ticks 5221333868500 # Number of ticks simulated
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final_tick 5221333868500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 155160 # Simulator instruction rate (inst/s)
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host_op_rate 301283 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5363173075 # Simulator tick rate (ticks/s)
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host_mem_usage 777200 # Number of bytes of host memory used
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host_seconds 973.55 # Real time elapsed on the host
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host_inst_rate 231127 # Simulator instruction rate (inst/s)
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host_op_rate 448792 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 7989012150 # Simulator tick rate (ticks/s)
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host_mem_usage 840496 # Number of bytes of host memory used
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host_seconds 653.56 # Real time elapsed on the host
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sim_insts 151056351 # Number of instructions simulated
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sim_ops 293314763 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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@ -568,37 +568,37 @@ system.ruby.delayHist::mean 0.431734 # de
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system.ruby.delayHist::stdev 1.809496 # delay histogram for all message
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system.ruby.delayHist | 10578004 94.61% 94.61% | 2065 0.02% 94.63% | 600258 5.37% 99.99% | 191 0.00% 100.00% | 301 0.00% 100.00% | 12 0.00% 100.00% | 64 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
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system.ruby.delayHist::total 11180898 # delay histogram for all message
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system.ruby.outstanding_req_hist::bucket_size 1
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system.ruby.outstanding_req_hist::max_bucket 9
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system.ruby.outstanding_req_hist::samples 197955008
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system.ruby.outstanding_req_hist::mean 1.000129
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system.ruby.outstanding_req_hist::gmean 1.000089
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system.ruby.outstanding_req_hist::stdev 0.011356
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system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 197929478 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.outstanding_req_hist::total 197955008
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system.ruby.latency_hist::bucket_size 128
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system.ruby.latency_hist::max_bucket 1279
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system.ruby.latency_hist::samples 197955007
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system.ruby.latency_hist::mean 1.340882
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system.ruby.latency_hist::gmean 1.042158
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system.ruby.latency_hist::stdev 5.088799
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system.ruby.latency_hist | 197919440 99.98% 99.98% | 26716 0.01% 100.00% | 2921 0.00% 100.00% | 3323 0.00% 100.00% | 1640 0.00% 100.00% | 892 0.00% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00%
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system.ruby.latency_hist::total 197955007
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system.ruby.hit_latency_hist::bucket_size 1
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system.ruby.hit_latency_hist::max_bucket 9
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system.ruby.hit_latency_hist::samples 195243038
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system.ruby.hit_latency_hist::mean 1
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system.ruby.hit_latency_hist::gmean 1
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system.ruby.hit_latency_hist | 0 0.00% 0.00% | 195243038 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.hit_latency_hist::total 195243038
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||||
system.ruby.miss_latency_hist::bucket_size 128
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system.ruby.miss_latency_hist::max_bucket 1279
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system.ruby.miss_latency_hist::samples 2711969
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system.ruby.miss_latency_hist::mean 25.882013
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system.ruby.miss_latency_hist::gmean 20.371762
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system.ruby.miss_latency_hist::stdev 35.771321
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system.ruby.miss_latency_hist | 2676402 98.69% 98.69% | 26716 0.99% 99.67% | 2921 0.11% 99.78% | 3323 0.12% 99.90% | 1640 0.06% 99.96% | 892 0.03% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00%
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system.ruby.miss_latency_hist::total 2711969
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system.ruby.outstanding_req_hist_seqr::bucket_size 1
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system.ruby.outstanding_req_hist_seqr::max_bucket 9
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system.ruby.outstanding_req_hist_seqr::samples 197955008
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system.ruby.outstanding_req_hist_seqr::mean 1.000129
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system.ruby.outstanding_req_hist_seqr::gmean 1.000089
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system.ruby.outstanding_req_hist_seqr::stdev 0.011356
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system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 197929478 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.outstanding_req_hist_seqr::total 197955008
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system.ruby.latency_hist_seqr::bucket_size 128
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system.ruby.latency_hist_seqr::max_bucket 1279
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system.ruby.latency_hist_seqr::samples 197955007
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system.ruby.latency_hist_seqr::mean 1.340882
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system.ruby.latency_hist_seqr::gmean 1.042158
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system.ruby.latency_hist_seqr::stdev 5.088799
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system.ruby.latency_hist_seqr | 197919440 99.98% 99.98% | 26716 0.01% 100.00% | 2921 0.00% 100.00% | 3323 0.00% 100.00% | 1640 0.00% 100.00% | 892 0.00% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00%
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system.ruby.latency_hist_seqr::total 197955007
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system.ruby.hit_latency_hist_seqr::bucket_size 1
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system.ruby.hit_latency_hist_seqr::max_bucket 9
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system.ruby.hit_latency_hist_seqr::samples 195243038
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system.ruby.hit_latency_hist_seqr::mean 1
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system.ruby.hit_latency_hist_seqr::gmean 1
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system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 195243038 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.hit_latency_hist_seqr::total 195243038
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system.ruby.miss_latency_hist_seqr::bucket_size 128
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system.ruby.miss_latency_hist_seqr::max_bucket 1279
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system.ruby.miss_latency_hist_seqr::samples 2711969
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system.ruby.miss_latency_hist_seqr::mean 25.882013
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system.ruby.miss_latency_hist_seqr::gmean 20.371762
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system.ruby.miss_latency_hist_seqr::stdev 35.771321
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system.ruby.miss_latency_hist_seqr | 2676402 98.69% 98.69% | 26716 0.99% 99.67% | 2921 0.11% 99.78% | 3323 0.12% 99.90% | 1640 0.06% 99.96% | 892 0.03% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00%
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system.ruby.miss_latency_hist_seqr::total 2711969
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system.ruby.l1_cntrl0.L1Dcache.demand_hits 16386626 # Number of cache demand hits
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system.ruby.l1_cntrl0.L1Dcache.demand_misses 1208734 # Number of cache demand misses
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system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17595360 # Number of cache demand accesses
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@ -895,135 +895,135 @@ system.ruby.delayVCHist.vnet_2::mean 0.000069 # de
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system.ruby.delayVCHist.vnet_2::stdev 0.011745 # delay histogram for vnet_2
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system.ruby.delayVCHist.vnet_2 | 86983 100.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
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system.ruby.delayVCHist.vnet_2::total 86986 # delay histogram for vnet_2
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system.ruby.LD.latency_hist::bucket_size 128
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system.ruby.LD.latency_hist::max_bucket 1279
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system.ruby.LD.latency_hist::samples 15432045
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system.ruby.LD.latency_hist::mean 2.853347
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system.ruby.LD.latency_hist::gmean 1.313273
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system.ruby.LD.latency_hist::stdev 9.004183
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system.ruby.LD.latency_hist | 15417229 99.90% 99.90% | 12840 0.08% 99.99% | 810 0.01% 99.99% | 753 0.00% 100.00% | 313 0.00% 100.00% | 86 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00%
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system.ruby.LD.latency_hist::total 15432045
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system.ruby.LD.hit_latency_hist::bucket_size 1
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system.ruby.LD.hit_latency_hist::max_bucket 9
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system.ruby.LD.hit_latency_hist::samples 13998259
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system.ruby.LD.hit_latency_hist::mean 1
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system.ruby.LD.hit_latency_hist::gmean 1
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system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 13998259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.hit_latency_hist::total 13998259
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system.ruby.LD.miss_latency_hist::bucket_size 128
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system.ruby.LD.miss_latency_hist::max_bucket 1279
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system.ruby.LD.miss_latency_hist::samples 1433786
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system.ruby.LD.miss_latency_hist::mean 20.947839
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system.ruby.LD.miss_latency_hist::gmean 18.787632
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system.ruby.LD.miss_latency_hist::stdev 22.620333
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system.ruby.LD.miss_latency_hist | 1418970 98.97% 98.97% | 12840 0.90% 99.86% | 810 0.06% 99.92% | 753 0.05% 99.97% | 313 0.02% 99.99% | 86 0.01% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00%
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system.ruby.LD.miss_latency_hist::total 1433786
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system.ruby.ST.latency_hist::bucket_size 128
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system.ruby.ST.latency_hist::max_bucket 1279
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system.ruby.ST.latency_hist::samples 9612989
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system.ruby.ST.latency_hist::mean 3.237898
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system.ruby.ST.latency_hist::gmean 1.143931
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system.ruby.ST.latency_hist::stdev 17.979843
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system.ruby.ST.latency_hist | 9598427 99.85% 99.85% | 8665 0.09% 99.94% | 1602 0.02% 99.96% | 2295 0.02% 99.98% | 1192 0.01% 99.99% | 757 0.01% 100.00% | 4 0.00% 100.00% | 23 0.00% 100.00% | 18 0.00% 100.00% | 6 0.00% 100.00%
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system.ruby.ST.latency_hist::total 9612989
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system.ruby.ST.hit_latency_hist::bucket_size 1
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system.ruby.ST.hit_latency_hist::max_bucket 9
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system.ruby.ST.hit_latency_hist::samples 9259401
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system.ruby.ST.hit_latency_hist::mean 1
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system.ruby.ST.hit_latency_hist::gmean 1
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system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 9259401 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.hit_latency_hist::total 9259401
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||||
system.ruby.ST.miss_latency_hist::bucket_size 128
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system.ruby.ST.miss_latency_hist::max_bucket 1279
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system.ruby.ST.miss_latency_hist::samples 353588
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system.ruby.ST.miss_latency_hist::mean 61.841694
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system.ruby.ST.miss_latency_hist::gmean 38.700068
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system.ruby.ST.miss_latency_hist::stdev 72.272561
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system.ruby.ST.miss_latency_hist | 339026 95.88% 95.88% | 8665 2.45% 98.33% | 1602 0.45% 98.79% | 2295 0.65% 99.43% | 1192 0.34% 99.77% | 757 0.21% 99.99% | 4 0.00% 99.99% | 23 0.01% 99.99% | 18 0.01% 100.00% | 6 0.00% 100.00%
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system.ruby.ST.miss_latency_hist::total 353588
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system.ruby.IFETCH.latency_hist::bucket_size 128
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system.ruby.IFETCH.latency_hist::max_bucket 1279
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system.ruby.IFETCH.latency_hist::samples 171728771
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system.ruby.IFETCH.latency_hist::mean 1.087728
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system.ruby.IFETCH.latency_hist::gmean 1.013814
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system.ruby.IFETCH.latency_hist::stdev 1.877484
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system.ruby.IFETCH.latency_hist | 171723029 100.00% 100.00% | 4832 0.00% 100.00% | 479 0.00% 100.00% | 259 0.00% 100.00% | 120 0.00% 100.00% | 42 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.IFETCH.latency_hist::total 171728771
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system.ruby.IFETCH.hit_latency_hist::bucket_size 1
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system.ruby.IFETCH.hit_latency_hist::max_bucket 9
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system.ruby.IFETCH.hit_latency_hist::samples 170908500
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system.ruby.IFETCH.hit_latency_hist::mean 1
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system.ruby.IFETCH.hit_latency_hist::gmean 1
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system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 170908500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.IFETCH.hit_latency_hist::total 170908500
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system.ruby.IFETCH.miss_latency_hist::bucket_size 128
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system.ruby.IFETCH.miss_latency_hist::max_bucket 1279
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system.ruby.IFETCH.miss_latency_hist::samples 820271
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system.ruby.IFETCH.miss_latency_hist::mean 19.366341
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system.ruby.IFETCH.miss_latency_hist::gmean 17.675078
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system.ruby.IFETCH.miss_latency_hist::stdev 20.056386
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system.ruby.IFETCH.miss_latency_hist | 814529 99.30% 99.30% | 4832 0.59% 99.89% | 479 0.06% 99.95% | 259 0.03% 99.98% | 120 0.01% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.IFETCH.miss_latency_hist::total 820271
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||||
system.ruby.RMW_Read.latency_hist::bucket_size 128
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system.ruby.RMW_Read.latency_hist::max_bucket 1279
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system.ruby.RMW_Read.latency_hist::samples 500824
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system.ruby.RMW_Read.latency_hist::mean 4.015135
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system.ruby.RMW_Read.latency_hist::gmean 1.504010
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system.ruby.RMW_Read.latency_hist::stdev 10.229460
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system.ruby.RMW_Read.latency_hist | 500636 99.96% 99.96% | 143 0.03% 99.99% | 19 0.00% 99.99% | 10 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.RMW_Read.latency_hist::total 500824
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system.ruby.RMW_Read.hit_latency_hist::bucket_size 1
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system.ruby.RMW_Read.hit_latency_hist::max_bucket 9
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||||
system.ruby.RMW_Read.hit_latency_hist::samples 434822
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system.ruby.RMW_Read.hit_latency_hist::mean 1
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||||
system.ruby.RMW_Read.hit_latency_hist::gmean 1
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system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 434822 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.hit_latency_hist::total 434822
|
||||
system.ruby.RMW_Read.miss_latency_hist::bucket_size 128
|
||||
system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279
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||||
system.ruby.RMW_Read.miss_latency_hist::samples 66002
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||||
system.ruby.RMW_Read.miss_latency_hist::mean 23.878882
|
||||
system.ruby.RMW_Read.miss_latency_hist::gmean 22.130008
|
||||
system.ruby.RMW_Read.miss_latency_hist::stdev 18.427339
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system.ruby.RMW_Read.miss_latency_hist | 65814 99.72% 99.72% | 143 0.22% 99.93% | 19 0.03% 99.96% | 10 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.miss_latency_hist::total 66002
|
||||
system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64
|
||||
system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639
|
||||
system.ruby.Locked_RMW_Read.latency_hist::samples 340189
|
||||
system.ruby.Locked_RMW_Read.latency_hist::mean 3.322221
|
||||
system.ruby.Locked_RMW_Read.latency_hist::gmean 1.405053
|
||||
system.ruby.Locked_RMW_Read.latency_hist::stdev 8.368395
|
||||
system.ruby.Locked_RMW_Read.latency_hist | 339841 99.90% 99.90% | 89 0.03% 99.92% | 235 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00%
|
||||
system.ruby.Locked_RMW_Read.latency_hist::total 340189
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9
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||||
system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301867
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||||
system.ruby.Locked_RMW_Read.hit_latency_hist::mean 1
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||||
system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 1
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||||
system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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||||
system.ruby.Locked_RMW_Read.hit_latency_hist::total 301867
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38322
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist::mean 21.614634
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 20.468455
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.638998
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist | 37974 99.09% 99.09% | 89 0.23% 99.32% | 235 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00%
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist::total 38322
|
||||
system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1
|
||||
system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9
|
||||
system.ruby.Locked_RMW_Write.latency_hist::samples 340189
|
||||
system.ruby.Locked_RMW_Write.latency_hist::mean 1
|
||||
system.ruby.Locked_RMW_Write.latency_hist::gmean 1
|
||||
system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Locked_RMW_Write.latency_hist::total 340189
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist::samples 340189
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist::mean 1
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 1
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist::total 340189
|
||||
system.ruby.LD.latency_hist_seqr::bucket_size 128
|
||||
system.ruby.LD.latency_hist_seqr::max_bucket 1279
|
||||
system.ruby.LD.latency_hist_seqr::samples 15432045
|
||||
system.ruby.LD.latency_hist_seqr::mean 2.853347
|
||||
system.ruby.LD.latency_hist_seqr::gmean 1.313273
|
||||
system.ruby.LD.latency_hist_seqr::stdev 9.004183
|
||||
system.ruby.LD.latency_hist_seqr | 15417229 99.90% 99.90% | 12840 0.08% 99.99% | 810 0.01% 99.99% | 753 0.00% 100.00% | 313 0.00% 100.00% | 86 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist_seqr::total 15432045
|
||||
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist_seqr::samples 13998259
|
||||
system.ruby.LD.hit_latency_hist_seqr::mean 1
|
||||
system.ruby.LD.hit_latency_hist_seqr::gmean 1
|
||||
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 13998259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist_seqr::total 13998259
|
||||
system.ruby.LD.miss_latency_hist_seqr::bucket_size 128
|
||||
system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279
|
||||
system.ruby.LD.miss_latency_hist_seqr::samples 1433786
|
||||
system.ruby.LD.miss_latency_hist_seqr::mean 20.947839
|
||||
system.ruby.LD.miss_latency_hist_seqr::gmean 18.787632
|
||||
system.ruby.LD.miss_latency_hist_seqr::stdev 22.620333
|
||||
system.ruby.LD.miss_latency_hist_seqr | 1418970 98.97% 98.97% | 12840 0.90% 99.86% | 810 0.06% 99.92% | 753 0.05% 99.97% | 313 0.02% 99.99% | 86 0.01% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist_seqr::total 1433786
|
||||
system.ruby.ST.latency_hist_seqr::bucket_size 128
|
||||
system.ruby.ST.latency_hist_seqr::max_bucket 1279
|
||||
system.ruby.ST.latency_hist_seqr::samples 9612989
|
||||
system.ruby.ST.latency_hist_seqr::mean 3.237898
|
||||
system.ruby.ST.latency_hist_seqr::gmean 1.143931
|
||||
system.ruby.ST.latency_hist_seqr::stdev 17.979843
|
||||
system.ruby.ST.latency_hist_seqr | 9598427 99.85% 99.85% | 8665 0.09% 99.94% | 1602 0.02% 99.96% | 2295 0.02% 99.98% | 1192 0.01% 99.99% | 757 0.01% 100.00% | 4 0.00% 100.00% | 23 0.00% 100.00% | 18 0.00% 100.00% | 6 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist_seqr::total 9612989
|
||||
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
|
||||
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
|
||||
system.ruby.ST.hit_latency_hist_seqr::samples 9259401
|
||||
system.ruby.ST.hit_latency_hist_seqr::mean 1
|
||||
system.ruby.ST.hit_latency_hist_seqr::gmean 1
|
||||
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259401 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist_seqr::total 9259401
|
||||
system.ruby.ST.miss_latency_hist_seqr::bucket_size 128
|
||||
system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279
|
||||
system.ruby.ST.miss_latency_hist_seqr::samples 353588
|
||||
system.ruby.ST.miss_latency_hist_seqr::mean 61.841694
|
||||
system.ruby.ST.miss_latency_hist_seqr::gmean 38.700068
|
||||
system.ruby.ST.miss_latency_hist_seqr::stdev 72.272561
|
||||
system.ruby.ST.miss_latency_hist_seqr | 339026 95.88% 95.88% | 8665 2.45% 98.33% | 1602 0.45% 98.79% | 2295 0.65% 99.43% | 1192 0.34% 99.77% | 757 0.21% 99.99% | 4 0.00% 99.99% | 23 0.01% 99.99% | 18 0.01% 100.00% | 6 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist_seqr::total 353588
|
||||
system.ruby.IFETCH.latency_hist_seqr::bucket_size 128
|
||||
system.ruby.IFETCH.latency_hist_seqr::max_bucket 1279
|
||||
system.ruby.IFETCH.latency_hist_seqr::samples 171728771
|
||||
system.ruby.IFETCH.latency_hist_seqr::mean 1.087728
|
||||
system.ruby.IFETCH.latency_hist_seqr::gmean 1.013814
|
||||
system.ruby.IFETCH.latency_hist_seqr::stdev 1.877484
|
||||
system.ruby.IFETCH.latency_hist_seqr | 171723029 100.00% 100.00% | 4832 0.00% 100.00% | 479 0.00% 100.00% | 259 0.00% 100.00% | 120 0.00% 100.00% | 42 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist_seqr::total 171728771
|
||||
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
|
||||
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
|
||||
system.ruby.IFETCH.hit_latency_hist_seqr::samples 170908500
|
||||
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
|
||||
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
|
||||
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 170908500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist_seqr::total 170908500
|
||||
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128
|
||||
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279
|
||||
system.ruby.IFETCH.miss_latency_hist_seqr::samples 820271
|
||||
system.ruby.IFETCH.miss_latency_hist_seqr::mean 19.366341
|
||||
system.ruby.IFETCH.miss_latency_hist_seqr::gmean 17.675078
|
||||
system.ruby.IFETCH.miss_latency_hist_seqr::stdev 20.056386
|
||||
system.ruby.IFETCH.miss_latency_hist_seqr | 814529 99.30% 99.30% | 4832 0.59% 99.89% | 479 0.06% 99.95% | 259 0.03% 99.98% | 120 0.01% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist_seqr::total 820271
|
||||
system.ruby.RMW_Read.latency_hist_seqr::bucket_size 128
|
||||
system.ruby.RMW_Read.latency_hist_seqr::max_bucket 1279
|
||||
system.ruby.RMW_Read.latency_hist_seqr::samples 500824
|
||||
system.ruby.RMW_Read.latency_hist_seqr::mean 4.015135
|
||||
system.ruby.RMW_Read.latency_hist_seqr::gmean 1.504010
|
||||
system.ruby.RMW_Read.latency_hist_seqr::stdev 10.229460
|
||||
system.ruby.RMW_Read.latency_hist_seqr | 500636 99.96% 99.96% | 143 0.03% 99.99% | 19 0.00% 99.99% | 10 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.latency_hist_seqr::total 500824
|
||||
system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1
|
||||
system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9
|
||||
system.ruby.RMW_Read.hit_latency_hist_seqr::samples 434822
|
||||
system.ruby.RMW_Read.hit_latency_hist_seqr::mean 1
|
||||
system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1
|
||||
system.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 434822 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.hit_latency_hist_seqr::total 434822
|
||||
system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 128
|
||||
system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 1279
|
||||
system.ruby.RMW_Read.miss_latency_hist_seqr::samples 66002
|
||||
system.ruby.RMW_Read.miss_latency_hist_seqr::mean 23.878882
|
||||
system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 22.130008
|
||||
system.ruby.RMW_Read.miss_latency_hist_seqr::stdev 18.427339
|
||||
system.ruby.RMW_Read.miss_latency_hist_seqr | 65814 99.72% 99.72% | 143 0.22% 99.93% | 19 0.03% 99.96% | 10 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.RMW_Read.miss_latency_hist_seqr::total 66002
|
||||
system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 64
|
||||
system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 639
|
||||
system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 340189
|
||||
system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 3.322221
|
||||
system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 1.405053
|
||||
system.ruby.Locked_RMW_Read.latency_hist_seqr::stdev 8.368395
|
||||
system.ruby.Locked_RMW_Read.latency_hist_seqr | 339841 99.90% 99.90% | 89 0.03% 99.92% | 235 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00%
|
||||
system.ruby.Locked_RMW_Read.latency_hist_seqr::total 340189
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::bucket_size 1
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::max_bucket 9
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::samples 301867
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::mean 1
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::gmean 1
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::total 301867
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 64
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 639
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 38322
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 21.614634
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 20.468455
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::stdev 15.638998
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 37974 99.09% 99.09% | 89 0.23% 99.32% | 235 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00%
|
||||
system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 38322
|
||||
system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1
|
||||
system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9
|
||||
system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 340189
|
||||
system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 1
|
||||
system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 1
|
||||
system.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Locked_RMW_Write.latency_hist_seqr::total 340189
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::bucket_size 1
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::max_bucket 9
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::samples 340189
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::mean 1
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::gmean 1
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::total 340189
|
||||
system.ruby.Directory_Controller.Fetch 181234 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Data 103288 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 181708 0.00% 0.00%
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.061241 # Nu
|
|||
sim_ticks 61241011500 # Number of ticks simulated
|
||||
final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 266495 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 267822 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 180131185 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 451088 # Number of bytes of host memory used
|
||||
host_seconds 339.98 # Real time elapsed on the host
|
||||
host_inst_rate 253883 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 255147 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 171606317 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 452068 # Number of bytes of host memory used
|
||||
host_seconds 356.87 # Real time elapsed on the host
|
||||
sim_insts 90602850 # Number of instructions simulated
|
||||
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -791,18 +791,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2670 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2848092 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 121233792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 950995 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.361598 # Nu
|
|||
sim_ticks 361597758500 # Number of ticks simulated
|
||||
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1135132 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1135179 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1683423955 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 429008 # Number of bytes of host memory used
|
||||
host_seconds 214.80 # Real time elapsed on the host
|
||||
host_inst_rate 1193747 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1193796 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1770350920 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 429888 # Number of bytes of host memory used
|
||||
host_seconds 204.25 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -473,14 +473,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 208 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.061602 # Nu
|
|||
sim_ticks 61602281500 # Number of ticks simulated
|
||||
final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 108860 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 191684 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42446103 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 458164 # Number of bytes of host memory used
|
||||
host_seconds 1451.31 # Real time elapsed on the host
|
||||
host_inst_rate 110070 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 193816 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42918086 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 460124 # Number of bytes of host memory used
|
||||
host_seconds 1435.35 # Real time elapsed on the host
|
||||
sim_insts 157988547 # Number of instructions simulated
|
||||
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 1947008 # To
|
|||
system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 24 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 1928 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 2059 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 2023 # Per bank write bursts
|
||||
|
|
@ -343,15 +343,15 @@ system.cpu.rename.tempSerializingInsts 490 # co
|
|||
system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 49402348 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 322302018 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 63884608 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 63882730 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle
|
||||
|
|
@ -467,7 +467,7 @@ system.cpu.iew.iewDispatchedInsts 322303732 # Nu
|
|||
system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 1101 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations
|
||||
|
|
@ -486,9 +486,9 @@ system.cpu.iew.exec_rate 2.476830 # In
|
|||
system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 230213909 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 333860979 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value
|
||||
system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back
|
||||
system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back
|
||||
system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted
|
||||
|
|
@ -956,7 +956,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 5974 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6015 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution
|
||||
|
|
@ -964,8 +964,8 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # T
|
|||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225133 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6227214 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.412076 # Nu
|
|||
sim_ticks 412076211500 # Number of ticks simulated
|
||||
final_tick 412076211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 332870 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 332870 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 224166223 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300688 # Number of bytes of host memory used
|
||||
host_seconds 1838.26 # Real time elapsed on the host
|
||||
host_inst_rate 319842 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 319842 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 215393213 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301832 # Number of bytes of host memory used
|
||||
host_seconds 1913.13 # Real time elapsed on the host
|
||||
sim_insts 611901617 # Number of instructions simulated
|
||||
sim_ops 611901617 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 24299648 # To
|
|||
system.physmem.bytesWrittenSys 18790784 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 352 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 51706 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 23686 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 23158 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 23442 # Per bank write bursts
|
||||
|
|
@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 17195 # Pe
|
|||
system.physmem.perBankWrBursts::15 17131 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 412076182000 # Total gap between requests
|
||||
system.physmem.totGap 412076123500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -256,7 +256,7 @@ system.physmem.readRowHits 314253 # Nu
|
|||
system.physmem.writeRowHits 216307 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 73.67 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 612035.54 # Average gap between requests
|
||||
system.physmem.avgGap 612035.45 # Average gap between requests
|
||||
system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 548334360 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 299190375 # Energy for precharge commands per rank (pJ)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.363578 # Nu
|
|||
sim_ticks 363578056500 # Number of ticks simulated
|
||||
final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 237399 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 257134 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 170382928 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 321244 # Number of bytes of host memory used
|
||||
host_seconds 2133.89 # Real time elapsed on the host
|
||||
host_inst_rate 233007 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 252377 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 167231069 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 322224 # Number of bytes of host memory used
|
||||
host_seconds 2174.11 # Real time elapsed on the host
|
||||
sim_insts 506582156 # Number of instructions simulated
|
||||
sim_ops 548695379 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 9212032 # To
|
|||
system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 12571 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 9337 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 8920 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 8993 # Per bank write bursts
|
||||
|
|
@ -835,18 +835,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 17475 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 82243 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 17711 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 86920 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56641 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423464 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3480105 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2371712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56877 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3428141 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3485018 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2386816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 143961216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 143976320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 112366 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.708526 # Nu
|
|||
sim_ticks 708526400500 # Number of ticks simulated
|
||||
final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 974268 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1055088 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1366955379 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319428 # Number of bytes of host memory used
|
||||
host_seconds 518.32 # Real time elapsed on the host
|
||||
host_inst_rate 942956 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1021179 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1323022561 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 320452 # Number of bytes of host memory used
|
||||
host_seconds 535.54 # Real time elapsed on the host
|
||||
sim_insts 504986854 # Number of instructions simulated
|
||||
sim_ops 546878105 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -608,18 +608,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 9751 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 80784 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 84208 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1361408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3412658 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3445488 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 142391552 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 142393920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.215512 # Nu
|
|||
sim_ticks 215512229500 # Number of ticks simulated
|
||||
final_tick 215512229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 175368 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 210548 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 138419960 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 326400 # Number of bytes of host memory used
|
||||
host_seconds 1556.94 # Real time elapsed on the host
|
||||
host_inst_rate 167901 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 201584 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 132526721 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 327404 # Number of bytes of host memory used
|
||||
host_seconds 1626.18 # Real time elapsed on the host
|
||||
sim_insts 273037857 # Number of instructions simulated
|
||||
sim_ops 327812214 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -795,18 +795,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 40448 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 21970 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 36871 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 344 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 38808 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99585 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 109845 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3889728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 114486 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10376 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 124862 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4843392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 4243072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 5196736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 43319 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.349062 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.116576 # Nu
|
|||
sim_ticks 116576497500 # Number of ticks simulated
|
||||
final_tick 116576497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 122787 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 147419 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 52425325 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 336136 # Number of bytes of host memory used
|
||||
host_seconds 2223.67 # Real time elapsed on the host
|
||||
host_inst_rate 117910 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 141564 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 50343079 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 339456 # Number of bytes of host memory used
|
||||
host_seconds 2315.64 # Real time elapsed on the host
|
||||
sim_insts 273037220 # Number of instructions simulated
|
||||
sim_ops 327811602 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -44,7 +44,7 @@ system.physmem.bytesReadSys 5414912 # To
|
|||
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 955 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 811 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 833 # Per bank write bursts
|
||||
|
|
@ -204,12 +204,12 @@ system.physmem.bytesPerActivate::768-895 32 0.14% 98.92% # By
|
|||
system.physmem.bytesPerActivate::896-1023 31 0.14% 99.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 209 0.94% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 22133 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 841966540 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 2428366540 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 841969540 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 2428369540 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 423040000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 9951.38 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 9951.42 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28701.38 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28701.42 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 46.45 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 46.45 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -231,28 +231,28 @@ system.physmem_0.preEnergy 78007875 # En
|
|||
system.physmem_0.readEnergy 595896600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 63983016135 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 13820144250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 86234192340 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 739.725124 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 22625694019 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 63983019555 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 13820141250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 86234192760 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 739.725127 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 22625688019 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 3892720000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 90057594731 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 90057600731 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 24358320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 13290750 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 63999000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 11183516280 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 60135495000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 79034819670 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 677.968219 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 99984327847 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 11183518845 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 60135492750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 79034819985 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 677.968221 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 99984324847 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 3892720000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 12698960903 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 12698963903 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 37744347 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 20165678 # Number of conditional branches predicted
|
||||
|
|
@ -388,29 +388,29 @@ system.cpu.fetch.icacheStallCycles 12613908 # Nu
|
|||
system.cpu.fetch.Insts 334078036 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 37744347 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 24523917 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 217730983 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.Cycles 217730977 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 3511013 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.MiscStallCycles 1155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 1 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 89097958 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 22048 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 232104146 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 232104140 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 1.745924 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 1.249191 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 58364727 25.15% 25.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 58364721 25.15% 25.15% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 42980177 18.52% 43.66% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 30021674 12.93% 56.60% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 100737568 43.40% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 232104146 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 232104140 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.161887 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.432870 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 28023980 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 70770838 # Number of cycles decode is blocked
|
||||
system.cpu.decode.BlockedCycles 70770832 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 108573375 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 23115192 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1620761 # Number of cycles decode is squashing
|
||||
|
|
@ -421,7 +421,7 @@ system.cpu.decode.SquashedInsts 6170266 # Nu
|
|||
system.cpu.rename.SquashCycles 1620761 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 45363672 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 24814789 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 341990 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.serializeStallCycles 341984 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 113350212 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 46612722 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 355770088 # Number of instructions processed by rename
|
||||
|
|
@ -451,11 +451,11 @@ system.cpu.iq.iqSquashedInstsIssued 2301561 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 25470529 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 73751649 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 5712 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 232104146 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 232104140 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 1.492598 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.113201 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 47511470 20.47% 20.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 47511464 20.47% 20.47% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 78618745 33.87% 54.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 60884809 26.23% 80.57% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 34936770 15.05% 95.63% # Number of insts issued each cycle
|
||||
|
|
@ -467,7 +467,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu
|
|||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 232104146 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 232104140 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 9573854 7.69% 7.69% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 7345 0.01% 7.69% # attempts to use FU when none available
|
||||
|
|
@ -540,7 +540,7 @@ system.cpu.iq.FU_type_0::total 346438253 # Ty
|
|||
system.cpu.iq.rate 1.485884 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 124543678 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.359497 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 764166784 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_reads 764166778 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 251741027 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 223260031 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 287659107 # Number of floating instruction queue reads
|
||||
|
|
@ -591,11 +591,11 @@ system.cpu.iew.wb_fanout 0.576282 # av
|
|||
system.cpu.commit.commitSquashedInsts 23083392 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1611406 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 228378919 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 228378913 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.435387 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.036441 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 94653053 41.45% 41.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 94653047 41.45% 41.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 70419351 30.83% 72.28% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 20855772 9.13% 81.41% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 13391170 5.86% 87.28% # Number of insts commited each cycle
|
||||
|
|
@ -607,7 +607,7 @@ system.cpu.commit.committed_per_cycle::8 10359612 4.54% 100.00% # Nu
|
|||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 228378919 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 228378913 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 273037832 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -654,10 +654,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
||||
system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction
|
||||
system.cpu.commit.bw_lim_events 10359612 # number cycles where commit BW limit reached
|
||||
system.cpu.rob.rob_reads 568912390 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 568912384 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 705520379 # The number of ROB writes
|
||||
system.cpu.timesIdled 58444 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 1048850 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 1048856 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 273037220 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 0.853924 # CPI: Cycles Per Instruction
|
||||
|
|
@ -717,14 +717,14 @@ system.cpu.dcache.overall_misses::cpu.data 3911467 #
|
|||
system.cpu.dcache.overall_misses::total 3911467 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31000710000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31000710000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8973516996 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8973516996 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8973513996 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8973513996 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 39974226996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 39974226996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 39974226996 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 39974226996 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 39974223996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 39974223996 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 39974223996 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 39974223996 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 85407824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 85407824 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -753,14 +753,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.023348
|
|||
system.cpu.dcache.overall_miss_rate::total 0.023348 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11074.775169 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 11074.775169 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8068.033525 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 8068.033525 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8068.030828 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 8068.030828 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.800129 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 10219.800129 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.753099 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 10219.753099 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.799362 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 10219.799362 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.752332 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 10219.752332 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 1061203 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -793,14 +793,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1534352
|
|||
system.cpu.dcache.overall_mshr_misses::total 1534352 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15231288500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 15231288500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828351773 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828351773 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828348773 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828348773 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17059640273 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 17059640273 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17060321773 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 17060321773 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17059637273 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 17059637273 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17060318773 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 17060318773 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015381 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015381 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -813,14 +813,14 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11594.314395 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11594.314395 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.020136 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.020136 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.006540 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.006540 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61954.545455 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61954.545455 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.545534 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.545534 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.909985 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.909985 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.543579 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.543579 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.908030 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.908030 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 715978 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.829667 # Cycle average of tags in use
|
||||
|
|
@ -852,12 +852,12 @@ system.cpu.icache.demand_misses::cpu.inst 722244 # n
|
|||
system.cpu.icache.demand_misses::total 722244 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 722244 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 722244 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 6486041445 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 6486041445 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 6486041445 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 6486041445 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 6486041445 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 6486041445 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 6486047445 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 6486047445 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 6486047445 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 6486047445 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 6486047445 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 6486047445 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 89097944 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 89097944 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 89097944 # number of demand (read+write) accesses
|
||||
|
|
@ -870,12 +870,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.008106
|
|||
system.cpu.icache.demand_miss_rate::total 0.008106 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.008106 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.008106 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8980.401976 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 8980.401976 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8980.401976 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 8980.401976 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8980.401976 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 8980.401976 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8980.410284 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 8980.410284 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8980.410284 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 8980.410284 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8980.410284 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 8980.410284 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 66919 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 2190 # number of cycles access was blocked
|
||||
|
|
@ -898,38 +898,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 716491
|
|||
system.cpu.icache.demand_mshr_misses::total 716491 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 716491 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 716491 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6035132455 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 6035132455 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6035132455 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 6035132455 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6035132455 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 6035132455 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6035135455 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 6035135455 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6035135455 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 6035135455 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6035135455 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 6035135455 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008042 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.008042 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.008042 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8423.179712 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8423.179712 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8423.179712 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 8423.179712 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8423.179712 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 8423.179712 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8423.183899 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8423.183899 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8423.183899 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 8423.183899 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8423.183899 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 8423.183899 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 404824 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 404865 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_issued 404830 # number of hwpf issued
|
||||
system.cpu.l2cache.prefetcher.pfIdentified 404871 # number of prefetch candidates identified
|
||||
system.cpu.l2cache.prefetcher.pfBufferHit 38 # number of redundant prefetches already in prefetch queue
|
||||
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
||||
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
||||
system.cpu.l2cache.prefetcher.pfSpanPage 28167 # number of prefetches not generated due to page crossing
|
||||
system.cpu.l2cache.prefetcher.pfSpanPage 28177 # number of prefetches not generated due to page crossing
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 5610.545510 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 5610.545509 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3011470 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 6745 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 446.474426 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 5502.326452 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 5502.326450 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 108.219059 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.335835 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006605 # Average percentage of cache occupancy
|
||||
|
|
@ -982,20 +982,20 @@ system.cpu.l2cache.demand_misses::total 82055 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 9709 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 72346 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 82055 # number of overall misses
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 19500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 19500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55912000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 55912000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 697537000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 697537000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 697540000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 697540000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5069165500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5069165500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 697537000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 697540000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 5125077500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 5822614500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 697537000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 5822617500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 697540000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 5125077500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 5822614500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 5822617500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 965413 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 965413 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1035068 # number of WritebackClean accesses(hits+misses)
|
||||
|
|
@ -1028,20 +1028,20 @@ system.cpu.l2cache.demand_miss_rate::total 0.036464 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013561 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.047151 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.036464 # miss rate for overall accesses
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22500 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22500 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19500 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19500 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72424.870466 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72424.870466 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71844.371202 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71844.371202 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71844.680194 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71844.680194 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70824.119094 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70824.119094 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71844.371202 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71844.680194 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70841.200619 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70959.898848 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.371202 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 70959.935409 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.680194 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70841.200619 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70959.898848 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 70959.935409 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -1062,8 +1062,8 @@ system.cpu.l2cache.demand_mshr_hits::total 89 #
|
|||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 77 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 89 # number of overall MSHR hits
|
||||
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51607 # number of HardPFReq MSHR misses
|
||||
system.cpu.l2cache.HardPFReq_mshr_misses::total 51607 # number of HardPFReq MSHR misses
|
||||
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51610 # number of HardPFReq MSHR misses
|
||||
system.cpu.l2cache.HardPFReq_mshr_misses::total 51610 # number of HardPFReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 728 # number of ReadExReq MSHR misses
|
||||
|
|
@ -1077,25 +1077,25 @@ system.cpu.l2cache.demand_mshr_misses::cpu.data 72269
|
|||
system.cpu.l2cache.demand_mshr_misses::total 81966 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 9697 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 72269 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51607 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 133573 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51610 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 133576 # number of overall MSHR misses
|
||||
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of HardPFReq MSHR miss cycles
|
||||
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180856312 # number of HardPFReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50141500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50141500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 638751500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 638751500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 638754500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 638754500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4638052000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4638052000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 638751500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 638754500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4688193500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5326945000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 638751500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5326948000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 638754500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4688193500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5507801312 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5507804312 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
||||
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
|
||||
|
|
@ -1112,60 +1112,60 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.036424
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059358 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.491871 # average HardPFReq mshr miss latency
|
||||
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3504.491871 # average HardPFReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.059359 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.288161 # average HardPFReq mshr miss latency
|
||||
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3504.288161 # average HardPFReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13500 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13500 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68875.686813 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68875.686813 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.042590 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.042590 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.351965 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.351965 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64830.684503 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64830.684503 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.042590 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.351965 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.690847 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.042590 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.727448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.351965 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.491871 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41234.391022 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.288161 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41233.487393 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4500659 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249836 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249343 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 130203 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52857 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 130206 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52860 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77346 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2030188 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 965413 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1035068 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1284403 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 81238 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::HardPFReq 52995 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::HardPFReq 52998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 716491 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313697 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2123993 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377646 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6501639 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 90080128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 181970688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 272050816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 134761 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2385076 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.191571 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2148432 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4602542 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6750974 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91644224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 196364032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 288008256 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 134764 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2385079 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.191572 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.468754 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2005511 84.09% 84.09% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 302219 12.67% 96.76% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 302222 12.67% 96.76% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 77346 3.24% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2385076 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2385079 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4500145500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 3.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1075017936 # Layer occupancy (ticks)
|
||||
|
|
@ -1174,12 +1174,11 @@ system.cpu.toL2Bus.respLayer1.occupancy 2302043463 # La
|
|||
system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 83880 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 728 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 728 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 83880 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169218 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 169218 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169217 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 169217 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5414912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 5414912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
|
|
@ -1195,7 +1194,7 @@ system.membus.snoop_fanout::max_value 0 # Re
|
|||
system.membus.snoop_fanout::total 84609 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 103435410 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 446650667 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 446648668 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.517291 # Nu
|
|||
sim_ticks 517291025500 # Number of ticks simulated
|
||||
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 635145 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 762516 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1204648551 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323584 # Number of bytes of host memory used
|
||||
host_seconds 429.41 # Real time elapsed on the host
|
||||
host_inst_rate 634406 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 761628 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1203245454 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 324572 # Number of bytes of host memory used
|
||||
host_seconds 429.91 # Real time elapsed on the host
|
||||
sim_insts 272739286 # Number of instructions simulated
|
||||
sim_ops 327433744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -602,18 +602,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 6212 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 253 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37418 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10207 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 47625 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1396160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 1746624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.560955 # Nu
|
|||
sim_ticks 560955232000 # Number of ticks simulated
|
||||
final_tick 560955232000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 340981 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 340981 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 205940379 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308844 # Number of bytes of host memory used
|
||||
host_seconds 2723.87 # Real time elapsed on the host
|
||||
host_inst_rate 326346 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 326346 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 197101410 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309500 # Number of bytes of host memory used
|
||||
host_seconds 2846.02 # Real time elapsed on the host
|
||||
sim_insts 928789150 # Number of instructions simulated
|
||||
sim_ops 928789150 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18704768 # To
|
|||
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 191173 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18033 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18359 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18394 # Per bank write bursts
|
||||
|
|
@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe
|
|||
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 560955208000 # Total gap between requests
|
||||
system.physmem.totGap 560955150000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -248,7 +248,7 @@ system.physmem.readRowHits 202530 # Nu
|
|||
system.physmem.writeRowHits 52011 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 69.37 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 78.00 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1562788.75 # Average gap between requests
|
||||
system.physmem.avgGap 1562788.59 # Average gap between requests
|
||||
system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 392416920 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 214116375 # Energy for precharge commands per rank (pJ)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.276414 # Nu
|
|||
sim_ticks 276414065500 # Number of ticks simulated
|
||||
final_tick 276414065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 180346 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 180346 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59177560 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308352 # Number of bytes of host memory used
|
||||
host_seconds 4670.93 # Real time elapsed on the host
|
||||
host_inst_rate 168860 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 168860 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55408638 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309496 # Number of bytes of host memory used
|
||||
host_seconds 4988.65 # Real time elapsed on the host
|
||||
sim_insts 842382029 # Number of instructions simulated
|
||||
sim_ops 842382029 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18696320 # To
|
|||
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 191079 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18006 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18321 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18379 # Per bank write bursts
|
||||
|
|
@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe
|
|||
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 276414034500 # Total gap between requests
|
||||
system.physmem.totGap 276413976000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -247,7 +247,7 @@ system.physmem.readRowHits 207034 # Nu
|
|||
system.physmem.writeRowHits 52000 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 70.95 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 770356.80 # Average gap between requests
|
||||
system.physmem.avgGap 770356.64 # Average gap between requests
|
||||
system.physmem.pageHitRate 72.26 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 374197320 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 204175125 # Energy for precharge commands per rank (pJ)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.542265 # Nu
|
|||
sim_ticks 542265386500 # Number of ticks simulated
|
||||
final_tick 542265386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 179877 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 221452 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 152251725 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325476 # Number of bytes of host memory used
|
||||
host_seconds 3561.64 # Real time elapsed on the host
|
||||
host_inst_rate 173269 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 213317 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 146659072 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 328008 # Number of bytes of host memory used
|
||||
host_seconds 3697.46 # Real time elapsed on the host
|
||||
sim_insts 640655085 # Number of instructions simulated
|
||||
sim_ops 788730744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18637888 # To
|
|||
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 190686 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18283 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18129 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
|
||||
|
|
@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe
|
|||
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 542265360500 # Total gap between requests
|
||||
system.physmem.totGap 542265292000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -243,7 +243,7 @@ system.physmem.readRowHits 194203 # Nu
|
|||
system.physmem.writeRowHits 51643 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 66.76 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1517611.52 # Average gap between requests
|
||||
system.physmem.avgGap 1517611.33 # Average gap between requests
|
||||
system.physmem.pageHitRate 68.86 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 420789600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 229597500 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -818,18 +818,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 154791 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 22257 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880344 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 23591 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 882361 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 25343 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 713113 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72942 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341192 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2414134 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3046336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343209 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2417485 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3131712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 58798528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 58883904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258813 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1066591 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.005113 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 1.045756 # Nu
|
|||
sim_ticks 1045756396500 # Number of ticks simulated
|
||||
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 734670 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 902587 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1201635964 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323928 # Number of bytes of host memory used
|
||||
host_seconds 870.28 # Real time elapsed on the host
|
||||
host_inst_rate 725560 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 891395 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1186735876 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325196 # Number of bytes of host memory used
|
||||
host_seconds 881.20 # Real time elapsed on the host
|
||||
sim_insts 639366787 # Number of instructions simulated
|
||||
sim_ops 785501035 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -609,18 +609,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 8752 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 879632 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1213440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56966208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 257772 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.059474 # Nu
|
|||
sim_ticks 59473862000 # Number of ticks simulated
|
||||
final_tick 59473862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 342067 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 342067 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 230037089 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 307480 # Number of bytes of host memory used
|
||||
host_seconds 258.54 # Real time elapsed on the host
|
||||
host_inst_rate 330532 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 330532 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 222279677 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308876 # Number of bytes of host memory used
|
||||
host_seconds 267.56 # Real time elapsed on the host
|
||||
sim_insts 88438073 # Number of instructions simulated
|
||||
sim_ops 88438073 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 10581824 # To
|
|||
system.physmem.bytesWrittenSys 7325760 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 14983 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 10312 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 10359 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 10206 # Per bank write bursts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.022297 # Nu
|
|||
sim_ticks 22296591500 # Number of ticks simulated
|
||||
final_tick 22296591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 221726 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 221726 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 62113736 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308500 # Number of bytes of host memory used
|
||||
host_seconds 358.96 # Real time elapsed on the host
|
||||
host_inst_rate 210659 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 210659 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59013272 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309644 # Number of bytes of host memory used
|
||||
host_seconds 377.82 # Real time elapsed on the host
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_ops 79591756 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 10563200 # To
|
|||
system.physmem.bytesWrittenSys 7322432 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 14730 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 10292 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 10329 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 10209 # Per bank write bursts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.056961 # Nu
|
|||
sim_ticks 56960656500 # Number of ticks simulated
|
||||
final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 199606 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 255266 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 160327771 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325784 # Number of bytes of host memory used
|
||||
host_seconds 355.28 # Real time elapsed on the host
|
||||
host_inst_rate 189048 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 241764 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 151847358 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 327812 # Number of bytes of host memory used
|
||||
host_seconds 375.12 # Real time elapsed on the host
|
||||
sim_insts 70915128 # Number of instructions simulated
|
||||
sim_ops 90690084 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 8209792 # To
|
|||
system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 6908 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 8061 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 8314 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 8233 # Per bank write bursts
|
||||
|
|
@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 5703 # Pe
|
|||
system.physmem.perBankWrBursts::15 5432 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 56960630500 # Total gap between requests
|
||||
system.physmem.totGap 56960624500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -247,7 +247,7 @@ system.physmem.readRowHits 111810 # Nu
|
|||
system.physmem.writeRowHits 63793 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 265564.34 # Average gap between requests
|
||||
system.physmem.avgGap 265564.32 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -825,18 +825,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 39288 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 34000 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 42868 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 38234 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129109 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473266 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 602375 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5388672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132689 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477500 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 610189 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5617792 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 23878848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 24107968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 96386 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 1.208729 # Nu
|
|||
sim_ticks 1208728699500 # Number of ticks simulated
|
||||
final_tick 1208728699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 339450 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 339450 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 224654099 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 299384 # Number of bytes of host memory used
|
||||
host_seconds 5380.40 # Real time elapsed on the host
|
||||
host_inst_rate 330067 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 330067 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 218444071 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300788 # Number of bytes of host memory used
|
||||
host_seconds 5533.36 # Real time elapsed on the host
|
||||
sim_insts 1826378509 # Number of instructions simulated
|
||||
sim_ops 1826378509 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 125030976 # To
|
|||
system.physmem.bytesWrittenSys 65416576 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 1301 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 897725 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 118310 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 113529 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 115745 # Per bank write bursts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.669525 # Nu
|
|||
sim_ticks 669525393000 # Number of ticks simulated
|
||||
final_tick 669525393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 166227 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 166227 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 64107392 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 299384 # Number of bytes of host memory used
|
||||
host_seconds 10443.81 # Real time elapsed on the host
|
||||
host_inst_rate 161577 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 161577 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 62314021 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 300544 # Number of bytes of host memory used
|
||||
host_seconds 10744.38 # Real time elapsed on the host
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_ops 1736043781 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 125551424 # To
|
|||
system.physmem.bytesWrittenSys 65555904 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 1298 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 903686 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 118677 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 113900 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 116118 # Per bank write bursts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.116861 # Nu
|
|||
sim_ticks 1116860578500 # Number of ticks simulated
|
||||
final_tick 1116860578500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 237615 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 255994 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 171817202 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317996 # Number of bytes of host memory used
|
||||
host_seconds 6500.28 # Real time elapsed on the host
|
||||
host_inst_rate 228405 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 246072 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 165157932 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318996 # Number of bytes of host memory used
|
||||
host_seconds 6762.38 # Real time elapsed on the host
|
||||
sim_insts 1544563088 # Number of instructions simulated
|
||||
sim_ops 1664032481 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -47,7 +47,7 @@ system.physmem.bytesReadSys 130981888 # To
|
|||
system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 962724 # Number of requests that are neither read nor write
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 127279 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 124661 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 121601 # Per bank write bursts
|
||||
|
|
@ -833,14 +833,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 7335104 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4734689 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6498678 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6500272 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669721 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27671390 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27672984 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.377030 # Nu
|
|||
sim_ticks 2377029670500 # Number of ticks simulated
|
||||
final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 970948 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1046333 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1499891883 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 316204 # Number of bytes of host memory used
|
||||
host_seconds 1584.80 # Real time elapsed on the host
|
||||
host_inst_rate 872363 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 940093 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1347600333 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317216 # Number of bytes of host memory used
|
||||
host_seconds 1763.90 # Real time elapsed on the host
|
||||
sim_insts 1538759602 # Number of instructions simulated
|
||||
sim_ops 1658228915 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -606,14 +606,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6326510 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.130773 # Nu
|
|||
sim_ticks 130772642500 # Number of ticks simulated
|
||||
final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 246902 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 260275 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 187375043 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 321308 # Number of bytes of host memory used
|
||||
host_seconds 697.92 # Real time elapsed on the host
|
||||
host_inst_rate 239563 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 252538 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 181805529 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 322304 # Number of bytes of host memory used
|
||||
host_seconds 719.30 # Real time elapsed on the host
|
||||
sim_insts 172317810 # Number of instructions simulated
|
||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -795,18 +795,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2566 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 20 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2888 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12257 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 15919 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 484608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 580864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 601472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.085490 # Nu
|
|||
sim_ticks 85490431000 # Number of ticks simulated
|
||||
final_tick 85490431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 129805 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 136836 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 64404554 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317332 # Number of bytes of host memory used
|
||||
host_seconds 1327.40 # Real time elapsed on the host
|
||||
host_inst_rate 128362 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 135315 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63688458 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319620 # Number of bytes of host memory used
|
||||
host_seconds 1342.32 # Real time elapsed on the host
|
||||
sim_insts 172303022 # Number of instructions simulated
|
||||
sim_ops 181635954 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -1118,19 +1118,19 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 51941 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 62415 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 11001 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::HardPFReq 2383 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 8640 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 8640 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 54914 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 64726 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155926 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217414 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 373340 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6464768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9219072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 15683840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 164228 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 219586 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 383814 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6996096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9358080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 16354176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 13384 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 141664 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.218517 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,51 +1,51 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.829332 # Number of seconds simulated
|
||||
sim_ticks 1829332273500 # Number of ticks simulated
|
||||
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1829331993500 # Number of ticks simulated
|
||||
final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 996309 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 996308 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 30356892493 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311076 # Number of bytes of host memory used
|
||||
host_seconds 60.26 # Real time elapsed on the host
|
||||
sim_insts 60038341 # Number of instructions simulated
|
||||
sim_ops 60038341 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1828258 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1828257 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55705727715 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 331420 # Number of bytes of host memory used
|
||||
host_seconds 32.84 # Real time elapsed on the host
|
||||
sim_insts 60038469 # Number of instructions simulated
|
||||
sim_ops 60038469 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66835456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 67686912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7416128 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7416128 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044304 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1057608 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115877 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115877 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36535438 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37000884 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4054008 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4054008 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4054008 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36535438 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41054893 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 9710422 # DTB read hits
|
||||
system.cpu.dtb.read_hits 9710423 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||
|
|
@ -53,14 +53,14 @@ system.cpu.dtb.write_hits 6352496 # DT
|
|||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 16062918 # DTB hits
|
||||
system.cpu.dtb.data_hits 16062919 # DTB hits
|
||||
system.cpu.dtb.data_misses 11471 # DTB misses
|
||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1020787 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 4974648 # ITB hits
|
||||
system.cpu.itb.fetch_hits 4974637 # ITB hits
|
||||
system.cpu.itb.fetch_misses 5006 # ITB misses
|
||||
system.cpu.itb.fetch_acv 184 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 4979654 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 4979643 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -73,32 +73,32 @@ system.cpu.itb.data_hits 0 # DT
|
|||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3658670905 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3658670345 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||
system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
|
||||
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811929473000 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17302245000 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829332066000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
||||
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
||||
|
|
@ -137,7 +137,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu
|
|||
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
|
||||
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
||||
|
|
@ -146,43 +146,43 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu
|
|||
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192180 # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192179 # number of callpals executed
|
||||
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
||||
system.cpu.kern.mode_good::kernel 1909
|
||||
system.cpu.kern.mode_good::user 1738
|
||||
system.cpu.kern.mode_good::kernel 1908
|
||||
system.cpu.kern.mode_good::user 1737
|
||||
system.cpu.kern.mode_good::idle 171
|
||||
system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.cpu.committedInsts 60038341 # Number of instructions committed
|
||||
system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 60038469 # Number of instructions committed
|
||||
system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913563 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913692 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115702 # number of memory refs
|
||||
system.cpu.num_load_insts 9747508 # Number of load instructions
|
||||
system.cpu.num_mem_refs 16115703 # number of memory refs
|
||||
system.cpu.num_load_insts 9747509 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368194 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064400 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.Branches 9064428 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
||||
|
|
@ -211,16 +211,16 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050179 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2042728 # number of replacements
|
||||
system.cpu.op_class::total 60050307 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2042707 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2043240 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.870655 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
|
|
@ -230,52 +230,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 66369797 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 66369797 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807758 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807758 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848202 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848202 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655960 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655960 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655960 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655960 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721724 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721724 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17163 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17163 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026094 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026094 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026094 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026094 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529482 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529482 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655981 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682054 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682054 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682054 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682054 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180673 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180673 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085685 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085685 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129198 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129198 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129198 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129198 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -284,16 +284,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833492 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833492 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833475 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 919605 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59129947 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.263509 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 919603 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215260 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
|
|
@ -301,26 +301,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 60970411 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 60970411 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59129947 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59129947 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59129947 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59129947 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59129947 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59129947 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920232 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050179 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050179 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050179 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050179 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59130077 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920230 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
||||
|
|
@ -335,18 +335,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 919605 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 919605 # number of writebacks
|
||||
system.cpu.icache.writebacks::writebacks 919603 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 919603 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 992425 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374115 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4560164 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057588 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.311853 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 992419 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057582 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.311847 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.320500 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.498040 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.327000 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.506195 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy
|
||||
|
|
@ -355,75 +355,75 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3046 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54052 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 48754034 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48754034 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 833492 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 833492 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits
|
||||
system.cpu.l2cache.tags.tag_accesses 48753652 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48753652 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 833475 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 833475 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 919351 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 919351 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811243 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 811243 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998531 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905456 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998531 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905456 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187286 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187286 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906923 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 906923 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906923 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998516 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905439 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906923 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998516 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905439 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117060 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117060 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044710 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1057999 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044704 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1057993 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044710 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1057999 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 833492 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 833492 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044704 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1057993 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 833475 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 833475 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 919351 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 919351 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738887 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1738887 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920212 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 920212 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384628 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384628 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533470 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533470 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357015 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511303 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357016 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357015 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511303 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357016 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -432,46 +432,46 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74365 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74365 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74359 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 833492 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 919353 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1207667 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 833475 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 919603 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117733440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157038 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 301890478 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1075994 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7018681 # Request fanout histogram
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 920230 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760063 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8923286 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154606 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 301903918 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1075988 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7018629 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7013458 99.93% 99.93% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7013406 99.93% 99.93% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7018681 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7018629 # Request fanout histogram
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -515,12 +515,12 @@ system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 26616
|
|||
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.replacements 41686 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.225572 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225572 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
|
|
@ -567,39 +567,39 @@ system.membus.trans_dist::ReadReq 7184 # Tr
|
|||
system.membus.trans_dist::ReadResp 948291 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 115877 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917027 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917188 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 147 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 147 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116931 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 116931 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116925 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 116925 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107401 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141445 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266422 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107383 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141427 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266565 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72462656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508782 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 75176686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2149824 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2149812 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2149824 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2149812 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2149824 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2149812 # Request fanout histogram
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.783867 # Number of seconds simulated
|
||||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.783855 # Number of seconds simulated
|
||||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 624684 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 760453 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 12180447765 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 563036 # Number of bytes of host memory used
|
||||
host_seconds 228.55 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1852974 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2255698 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 36130480826 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581484 # Number of bytes of host memory used
|
||||
host_seconds 77.05 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
||||
|
|
@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide 960 # Nu
|
|||
system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 10029 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walks 10028 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 31526223 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8581 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23124452 # DTB write hits
|
||||
system.cpu.dtb.read_hits 31525949 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8580 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23124104 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1448 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
|
|
@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 31534804 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125900 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 31534529 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125552 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 54650675 # DTB hits
|
||||
system.cpu.dtb.misses 10029 # DTB misses
|
||||
system.cpu.dtb.accesses 54660704 # DTB accesses
|
||||
system.cpu.dtb.hits 54650053 # DTB hits
|
||||
system.cpu.dtb.misses 10028 # DTB misses
|
||||
system.cpu.dtb.accesses 54660081 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
|||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 147039346 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 147038166 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -202,40 +202,40 @@ system.cpu.itb.domain_faults 0 # Nu
|
|||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
|
||||
system.cpu.itb.hits 147039346 # DTB hits
|
||||
system.cpu.itb.inst_accesses 147042928 # ITB inst accesses
|
||||
system.cpu.itb.hits 147038166 # DTB hits
|
||||
system.cpu.itb.misses 4762 # DTB misses
|
||||
system.cpu.itb.accesses 147044108 # DTB accesses
|
||||
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
|
||||
system.cpu.itb.accesses 147042928 # DTB accesses
|
||||
system.cpu.numCycles 5567712151 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142772879 # Number of instructions committed
|
||||
system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
|
||||
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142771651 # Number of instructions committed
|
||||
system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 16873899 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153162683 # number of integer instructions
|
||||
system.cpu.num_func_calls 16873962 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153161279 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11484 # number of float instructions
|
||||
system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55939276 # number of memory refs
|
||||
system.cpu.num_load_insts 31855884 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083392 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55938616 # number of memory refs
|
||||
system.cpu.num_load_insts 31855585 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083031 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
||||
system.cpu.Branches 36396981 # Number of branches fetched
|
||||
system.cpu.Branches 36396978 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
||||
|
|
@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177219912 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu.op_class::total 177218432 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 819392 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
|
|
@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52863656 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814074 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814065 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
|
||||
|
|
@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682040 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682017 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1699214 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 1698998 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
|
|
@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145342721 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699732 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
|
||||
system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145341757 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699516 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1699214 # number of writebacks
|
||||
system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698998 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
|
|
@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
|
||||
|
|
@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 181651 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101950 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182974 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182975 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
|
|
@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321
|
|||
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.replacements 36430 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
|
|
@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq 40087 # Tr
|
|||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8203 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
|
|
@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 434821 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.783867 # Number of seconds simulated
|
||||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.783855 # Number of seconds simulated
|
||||
sim_ticks 2783854535000 # Number of ticks simulated
|
||||
final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 540254 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 657673 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 10534181577 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 560556 # Number of bytes of host memory used
|
||||
host_seconds 264.27 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1173204 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1428188 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22875895912 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 581200 # Number of bytes of host memory used
|
||||
host_seconds 121.69 # Real time elapsed on the host
|
||||
sim_insts 142771651 # Number of instructions simulated
|
||||
sim_ops 173801592 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
||||
|
|
@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide 960 # Nu
|
|||
system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
|
|||
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.walker.walks 10029 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walks 10028 # Table walker walks requested
|
||||
system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
|
||||
system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency
|
||||
system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 31526223 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8581 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23124452 # DTB write hits
|
||||
system.cpu.dtb.read_hits 31525949 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8580 # DTB read misses
|
||||
system.cpu.dtb.write_hits 23124104 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1448 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
||||
|
|
@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu
|
|||
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 31534804 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125900 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 31534529 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 23125552 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 54650675 # DTB hits
|
||||
system.cpu.dtb.misses 10029 # DTB misses
|
||||
system.cpu.dtb.accesses 54660704 # DTB accesses
|
||||
system.cpu.dtb.hits 54650053 # DTB hits
|
||||
system.cpu.dtb.misses 10028 # DTB misses
|
||||
system.cpu.dtb.accesses 54660081 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
|
|||
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
||||
system.cpu.itb.inst_hits 147039346 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 147038166 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
|
|
@ -202,40 +202,40 @@ system.cpu.itb.domain_faults 0 # Nu
|
|||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
|
||||
system.cpu.itb.hits 147039346 # DTB hits
|
||||
system.cpu.itb.inst_accesses 147042928 # ITB inst accesses
|
||||
system.cpu.itb.hits 147038166 # DTB hits
|
||||
system.cpu.itb.misses 4762 # DTB misses
|
||||
system.cpu.itb.accesses 147044108 # DTB accesses
|
||||
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
|
||||
system.cpu.itb.accesses 147042928 # DTB accesses
|
||||
system.cpu.numCycles 5567712151 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142772879 # Number of instructions committed
|
||||
system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
|
||||
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142771651 # Number of instructions committed
|
||||
system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 16873899 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153162683 # number of integer instructions
|
||||
system.cpu.num_func_calls 16873962 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 153161279 # number of integer instructions
|
||||
system.cpu.num_fp_insts 11484 # number of float instructions
|
||||
system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55939276 # number of memory refs
|
||||
system.cpu.num_load_insts 31855884 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083392 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 55938616 # number of memory refs
|
||||
system.cpu.num_load_insts 31855585 # Number of load instructions
|
||||
system.cpu.num_store_insts 24083031 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
|
||||
system.cpu.Branches 36396981 # Number of branches fetched
|
||||
system.cpu.Branches 36396978 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
||||
|
|
@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177219912 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu.op_class::total 177218432 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 819392 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
|
|
@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 52863656 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814074 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 814065 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
|
||||
|
|
@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682040 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 682017 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1699214 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 1698998 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
|
|
@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145342721 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699732 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
|
||||
system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 145341757 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1699516 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1699214 # number of writebacks
|
||||
system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1698998 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
||||
|
|
@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
|
||||
|
|
@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 181651 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101949 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 101950 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182974 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182975 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
|
|
@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321
|
|||
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.replacements 36430 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
|
|
@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq 40087 # Tr
|
|||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8203 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
||||
|
|
@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port
|
|||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 434821 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112152 # Number of seconds simulated
|
||||
sim_ticks 5112152301500 # Number of ticks simulated
|
||||
final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 5112151729000 # Number of ticks simulated
|
||||
final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 646932 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1324411 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 16530551683 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 604676 # Number of bytes of host memory used
|
||||
host_seconds 309.26 # Real time elapsed on the host
|
||||
sim_insts 200066731 # Number of instructions simulated
|
||||
sim_ops 409580371 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1266983 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2593792 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32374197845 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 659352 # Number of bytes of host memory used
|
||||
host_seconds 157.91 # Real time elapsed on the host
|
||||
sim_insts 200067055 # Number of instructions simulated
|
||||
sim_ops 409581065 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
||||
|
|
@ -21,16 +21,16 @@ system.physmem.bytes_read::pc.south_bridge.ide 28352
|
|||
system.physmem.bytes_read::total 11490752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 9270016 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9270016 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 9269888 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9269888 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 179543 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144844 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144844 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144842 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144842 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s)
|
||||
|
|
@ -39,48 +39,48 @@ system.physmem.bw_read::pc.south_bridge.ide 5546 #
|
|||
system.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1813329 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813329 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1813329 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1813305 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813305 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1813305 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4061062 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4061038 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.numCycles 10224308568 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 10224307424 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 200066731 # Number of instructions committed
|
||||
system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 200067055 # Number of instructions committed
|
||||
system.cpu.committedOps 409581065 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374584177 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2308877 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 40001070 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374583495 # number of integer instructions
|
||||
system.cpu.num_func_calls 2308905 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 40001120 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374584177 # number of integer instructions
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_int_register_reads 682689563 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 323557658 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 682690924 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 323558192 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 233837318 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 157316420 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 35667022 # number of memory refs
|
||||
system.cpu.num_load_insts 27243255 # Number of load instructions
|
||||
system.cpu.num_store_insts 8423767 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770324721.656570 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453983846.343430 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 233837631 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 157316591 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 35667176 # number of memory refs
|
||||
system.cpu.num_load_insts 27243343 # Number of load instructions
|
||||
system.cpu.num_store_insts 8423833 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770322790.617842 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453984633.382158 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955598 # Percentage of idle cycles
|
||||
system.cpu.Branches 43152159 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 172754 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 373476545 91.18% 91.23% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 144577 0.04% 91.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 123078 0.03% 91.29% # Class of executed instruction
|
||||
system.cpu.Branches 43152262 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 172765 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 373477070 91.18% 91.23% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 144574 0.04% 91.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 123086 0.03% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction
|
||||
|
|
@ -107,16 +107,16 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl
|
|||
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27240665 6.65% 97.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27240752 6.65% 97.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 8423833 2.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 409581402 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1621902 # number of replacements
|
||||
system.cpu.op_class::total 409582096 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1621909 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622414 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.438984 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 20181333 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622421 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.439024 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
|
|
@ -126,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 282
|
|||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 88836888 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88836888 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12023339 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12023339 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8096662 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8096662 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 58900 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 58900 # number of SoftPFReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20120001 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20120001 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20178901 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20178901 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 905249 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 905249 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316707 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316707 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 402757 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 402757 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1221956 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1221956 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624713 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624713 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 12928588 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 12928588 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8413369 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8413369 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.tags.tag_accesses 88837527 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88837527 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12023410 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12023410 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8096819 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8096819 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 58904 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 58904 # number of SoftPFReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20120229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20120229 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20179133 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20179133 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 905268 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 905268 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316618 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316618 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 402753 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 402753 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1221886 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1221886 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624639 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624639 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 12928678 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 12928678 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8413437 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8413437 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21341957 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21341957 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21803614 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21803614 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070019 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.070019 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037643 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037643 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872416 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872416 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.057256 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.057256 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074516 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074516 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21342115 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21342115 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21803772 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21803772 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037632 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037632 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872407 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872407 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.057252 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.057252 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074512 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074512 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -176,16 +176,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1535779 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535779 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535790 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.013997 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12940 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.666881 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454141000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013997 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.666366 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100450626500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014001 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
|
||||
|
|
@ -193,32 +193,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5
|
|||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
|
||||
system.cpu.dtb_walker_cache.tags.tag_accesses 52753 # Number of tag accesses
|
||||
system.cpu.dtb_walker_cache.tags.data_accesses 52753 # Number of data accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12941 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12941 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12941 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12941 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12941 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12941 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.tags.tag_accesses 52745 # Number of tag accesses
|
||||
system.cpu.dtb_walker_cache.tags.data_accesses 52745 # Number of data accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12937 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12937 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12937 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12937 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12937 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12937 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21898 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21898 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21898 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21898 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409033 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409033 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409033 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409033 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409033 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409033 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409108 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409108 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409108 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409108 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409108 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409108 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -227,14 +227,14 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2453 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2453 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 792216 # number of replacements
|
||||
system.cpu.icache.tags.replacements 792340 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 243675150 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 792728 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.388095 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 792852 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.340390 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
|
||||
|
|
@ -245,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 130
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 245260620 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 245260620 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243675150 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243675150 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243675150 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243675150 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243675150 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243675150 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 792735 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 792735 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 792735 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 792735 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 792735 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 792735 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244467885 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244467885 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244467885 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244467885 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244467885 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244467885 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 245261161 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 245261161 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243675443 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243675443 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243675443 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243675443 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243675443 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243675443 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 792859 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 792859 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 792859 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 792859 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 792859 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 792859 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244468302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244468302 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244468302 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244468302 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244468302 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244468302 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses
|
||||
|
|
@ -279,18 +279,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 792216 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 792216 # number of writebacks
|
||||
system.cpu.icache.writebacks::writebacks 792340 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 792340 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102144896000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026546 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189159 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189159 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102137159500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026555 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189160 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189160 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
|
||||
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
||||
|
|
@ -334,61 +334,61 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 106204 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.931309 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4340224 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 106202 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.506423 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.509391 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51928.965552 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51928.967732 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135113 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.314401 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.513764 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135114 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.317021 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.512729 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 39255979 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39255979 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1538777 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1538777 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 792205 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 792205 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179774 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179774 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779488 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 779488 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6656 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2896 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275198 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1284750 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 779488 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1454972 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2244012 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 779488 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1454972 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2244012 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20880 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39442 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 39254568 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39254568 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1539387 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1539387 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 792329 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 792329 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179766 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179766 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779612 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 779612 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6533 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2871 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275070 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1284474 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6533 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2871 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 779612 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1454836 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2243852 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6533 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2871 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 779612 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1454836 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2243852 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1349 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1349 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses
|
||||
|
|
@ -407,50 +407,50 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 5
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 180051 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1538777 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1538777 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 792205 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 792205 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314421 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792722 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 792722 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6657 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2901 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307362 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1316920 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6657 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2901 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 792722 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621783 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2424063 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6657 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2901 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 792722 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621783 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428238 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428238 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016694 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016694 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024602 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024428 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016694 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074277 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016694 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074277 # miss rate for overall accesses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1539387 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1539387 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 792329 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 792329 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1661 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1661 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314413 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314413 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792846 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 792846 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6534 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2876 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307234 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1316644 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6534 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2876 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 792846 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621647 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2423903 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6534 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2876 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 792846 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621647 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2423903 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.812161 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.812161 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428249 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428249 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016692 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016692 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000153 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001739 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024605 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024433 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000153 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001739 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016692 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102865 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074281 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000153 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001739 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016692 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102865 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074281 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -459,44 +459,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98177 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98177 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98175 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 15971629 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1538777 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 792205 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 88200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377675 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613331 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101436160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 330036665 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 203470 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18930684 # Request fanout histogram
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1539387 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 792340 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 93857 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 314418 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 314418 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 792859 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321433 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378058 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613747 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 35029964 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101452736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551417 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 329920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 758656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 330092729 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 203468 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18930863 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18911125 99.90% 99.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18911304 99.90% 99.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
|
||||
|
|
@ -504,7 +504,7 @@ system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re
|
|||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18930684 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18930863 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
|
||||
|
|
@ -558,14 +558,14 @@ system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbrid
|
|||
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iobus.pkt_size::total 13062828 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.iocache.tags.replacements 47568 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.042441 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.042439 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042439 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002652 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.002652 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
|
|
@ -610,11 +610,11 @@ system.membus.trans_dist::ReadReq 13857337 # Tr
|
|||
system.membus.trans_dist::ReadResp 13903644 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 144844 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8271 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2561 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 2109 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134351 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 144842 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8802 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2189 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 1650 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134346 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 134346 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution
|
||||
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||
|
|
@ -625,32 +625,32 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav
|
|||
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470253 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28212813 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28358488 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 469415 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28211975 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28358181 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43212089 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43211961 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46263353 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46263225 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 14256561 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 14256182 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.010907 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14254865 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14254486 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14256561 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14256182 # Request fanout histogram
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000121 # Nu
|
|||
sim_ticks 121460 # Number of ticks simulated
|
||||
final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 19821 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19819 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 376677 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 390876 # Number of bytes of host memory used
|
||||
host_seconds 0.32 # Real time elapsed on the host
|
||||
host_inst_rate 58804 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 58798 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1117518 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 412400 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000109 # Nu
|
|||
sim_ticks 108694 # Number of ticks simulated
|
||||
final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 18329 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 18327 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 311726 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 397240 # Number of bytes of host memory used
|
||||
host_seconds 0.35 # Real time elapsed on the host
|
||||
host_inst_rate 71872 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 71865 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1222276 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 417856 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu
|
|||
sim_ticks 86673 # Number of ticks simulated
|
||||
final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 26202 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 26199 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 355322 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 391844 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_inst_rate 58973 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 58962 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 799609 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 411856 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu
|
|||
sim_ticks 107210 # Number of ticks simulated
|
||||
final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 29228 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 29224 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 490268 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 394320 # Number of bytes of host memory used
|
||||
host_seconds 0.22 # Real time elapsed on the host
|
||||
host_inst_rate 108799 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 108769 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1824399 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 416280 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000046 # Nu
|
|||
sim_ticks 45733 # Number of ticks simulated
|
||||
final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 16358 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 16355 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 290200 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 389816 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 42490 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 42477 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 753627 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 411088 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu
|
|||
sim_ticks 41712 # Number of ticks simulated
|
||||
final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 12099 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12098 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 195791 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 393888 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
host_inst_rate 38081 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 38070 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 616024 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 414508 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu
|
|||
sim_ticks 32936 # Number of ticks simulated
|
||||
final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 22566 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 22561 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 288279 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 390660 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 52774 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 52753 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 673978 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 411572 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu
|
|||
sim_ticks 41659 # Number of ticks simulated
|
||||
final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 23573 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 23567 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 380874 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 390976 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_inst_rate 41992 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 41979 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 678429 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 412928 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu
|
|||
sim_ticks 29949500 # Number of ticks simulated
|
||||
final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 25443 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 29781 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 165422007 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247956 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_inst_rate 167534 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 196036 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1088591965 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269228 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 4605 # Number of instructions simulated
|
||||
sim_ops 5391 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -755,17 +755,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 17170000 # Number of ticks simulated
|
||||
final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 24070 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 28186 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 89974051 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 249040 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
host_inst_rate 56453 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 66106 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 211025109 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270504 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -1167,16 +1167,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 587 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
|
|||
sim_ticks 18741000 # Number of ticks simulated
|
||||
final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 27191 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 31839 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 110934081 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245436 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_inst_rate 84742 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 99228 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 345728368 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 266024 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -1082,19 +1082,19 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 409 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 913 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 636 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 924 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 452 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
|
|||
sim_ticks 28298500 # Number of ticks simulated
|
||||
final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 76228 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 88939 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 471979620 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 246976 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 286813 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 333728 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1769783602 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267436 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
sim_insts 4566 # Number of instructions simulated
|
||||
sim_ops 5330 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -556,16 +556,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000050 # Nu
|
|||
sim_ticks 49855000 # Number of ticks simulated
|
||||
final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 93266 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 107828 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 931188295 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 634440 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_inst_rate 411650 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 475781 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4107877451 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 655016 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4988 # Number of instructions simulated
|
||||
sim_ops 5770 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -629,13 +629,13 @@ system.l2bus.snoop_filter.tot_snoops 0 # To
|
|||
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.l2bus.trans_dist::ReadResp 348 # Transaction distribution
|
||||
system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution
|
||||
system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution
|
||||
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count::total 842 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu
|
|||
sim_ticks 53334000 # Number of ticks simulated
|
||||
final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 45290 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45279 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 435170568 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 616512 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_inst_rate 486070 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 485474 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4661655450 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 680524 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5548 # Number of instructions simulated
|
||||
sim_ops 5548 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -508,13 +508,13 @@ system.l2bus.snoop_filter.tot_snoops 0 # To
|
|||
system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.l2bus.trans_dist::ReadResp 315 # Transaction distribution
|
||||
system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution
|
||||
system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution
|
||||
system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution
|
||||
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count::total 864 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.147149 # Nu
|
|||
sim_ticks 147148719500 # Number of ticks simulated
|
||||
final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 392484 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 394434 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 637618235 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 382304 # Number of bytes of host memory used
|
||||
host_seconds 230.78 # Real time elapsed on the host
|
||||
host_inst_rate 1174056 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1179890 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1907338487 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 402756 # Number of bytes of host memory used
|
||||
host_seconds 77.15 # Real time elapsed on the host
|
||||
sim_insts 90576862 # Number of instructions simulated
|
||||
sim_ops 91026991 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -600,18 +600,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 255 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120942848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu
|
|||
sim_ticks 87707000 # Number of ticks simulated
|
||||
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 140858 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 140857 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 18239325 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 243264 # Number of bytes of host memory used
|
||||
host_seconds 4.81 # Real time elapsed on the host
|
||||
host_inst_rate 1830828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1830758 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 237054275 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306784 # Number of bytes of host memory used
|
||||
host_seconds 0.37 # Real time elapsed on the host
|
||||
sim_insts 677333 # Number of instructions simulated
|
||||
sim_ops 677333 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -750,14 +750,14 @@ system.cpu3.icache.writebacks::writebacks 279 # n
|
|||
system.cpu3.icache.writebacks::total 279 # number of writebacks
|
||||
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 0 # number of replacements
|
||||
system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use
|
||||
system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 4.076010 # Average number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
|
||||
|
|
@ -766,18 +766,18 @@ system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Av
|
|||
system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 19424 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 19424 # Number of data accesses
|
||||
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
|
||||
|
|
@ -944,24 +944,24 @@ system.l2c.no_allocate_misses 0 # Nu
|
|||
system.membus.trans_dist::ReadResp 423 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 412 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 183 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 136 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 1108 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 879 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 1108 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 879 # Request fanout histogram
|
||||
system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -970,7 +970,7 @@ system.toL2Bus.snoop_filter.hit_single_snoops 0
|
|||
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
|
||||
|
|
@ -978,24 +978,24 @@ system.toL2Bus.trans_dist::ReadExReq 412 # Tr
|
|||
system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 838 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 830 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 30400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 197568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,9 +4,9 @@ sim_seconds 0.010022 # Nu
|
|||
sim_ticks 10021833 # Number of ticks simulated
|
||||
final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 66575 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 401248 # Number of bytes of host memory used
|
||||
host_seconds 150.54 # Real time elapsed on the host
|
||||
host_tick_rate 141404 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 425972 # Number of bytes of host memory used
|
||||
host_seconds 70.87 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.004723 # Nu
|
|||
sim_ticks 4722948 # Number of ticks simulated
|
||||
final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 22839 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 403984 # Number of bytes of host memory used
|
||||
host_seconds 206.79 # Real time elapsed on the host
|
||||
host_tick_rate 43612 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 429416 # Number of bytes of host memory used
|
||||
host_seconds 108.30 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.007679 # Nu
|
|||
sim_ticks 7678882 # Number of ticks simulated
|
||||
final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 60394 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 401808 # Number of bytes of host memory used
|
||||
host_seconds 127.15 # Real time elapsed on the host
|
||||
host_tick_rate 131227 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 425824 # Number of bytes of host memory used
|
||||
host_seconds 58.52 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.128077 # Nu
|
|||
sim_ticks 128076812500 # Number of ticks simulated
|
||||
final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 329011 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 420055 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 598785355 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 256952 # Number of bytes of host memory used
|
||||
host_seconds 213.89 # Real time elapsed on the host
|
||||
host_inst_rate 887065 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1132533 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1614418321 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277452 # Number of bytes of host memory used
|
||||
host_seconds 79.33 # Real time elapsed on the host
|
||||
sim_insts 70373629 # Number of instructions simulated
|
||||
sim_ops 89847363 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -612,18 +612,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 15790 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 34314 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2220672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 20663744 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 95333 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.203116 # Nu
|
|||
sim_ticks 203115876500 # Number of ticks simulated
|
||||
final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 563415 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 570710 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 851483432 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 239344 # Number of bytes of host memory used
|
||||
host_seconds 238.54 # Real time elapsed on the host
|
||||
host_inst_rate 1130669 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1145309 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1708768878 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305928 # Number of bytes of host memory used
|
||||
host_seconds 118.87 # Real time elapsed on the host
|
||||
sim_insts 134398962 # Number of instructions simulated
|
||||
sim_ops 136139190 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -485,18 +485,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 184923 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 36455 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 36468 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558971 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447925 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1006896 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23804608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447938 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1006962 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 41375360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 41378752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 99021 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 436723 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000043 # Nu
|
|||
sim_ticks 43191 # Number of ticks simulated
|
||||
final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 247811 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 388428 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
host_tick_rate 428274 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410016 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000054 # Nu
|
|||
sim_ticks 54211 # Number of ticks simulated
|
||||
final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 192824 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 389940 # Number of bytes of host memory used
|
||||
host_seconds 0.28 # Real time elapsed on the host
|
||||
host_tick_rate 316777 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410608 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000030 # Nu
|
|||
sim_ticks 29561 # Number of ticks simulated
|
||||
final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 198957 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 389156 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_tick_rate 334780 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 410240 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.000038 # Nu
|
|||
sim_ticks 37741 # Number of ticks simulated
|
||||
final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 330031 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 387076 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_tick_rate 544029 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 408776 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.230198 # Nu
|
|||
sim_ticks 230197694500 # Number of ticks simulated
|
||||
final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 435347 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 458966 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 583184688 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 252480 # Number of bytes of host memory used
|
||||
host_seconds 394.73 # Real time elapsed on the host
|
||||
host_inst_rate 1151849 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1214340 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1543000471 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272972 # Number of bytes of host memory used
|
||||
host_seconds 149.19 # Real time elapsed on the host
|
||||
sim_insts 171842484 # Number of instructions simulated
|
||||
sim_ops 181165371 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -596,18 +596,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
|
|||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1448 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 18 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 287936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 403456 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram
|
||||
|
|
|
|||
Loading…
Reference in a new issue