2185 lines
258 KiB
Plaintext
2185 lines
258 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 51.771727 # Number of seconds simulated
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sim_ticks 51771726701500 # Number of ticks simulated
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final_tick 51771726701500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 821234 # Simulator instruction rate (inst/s)
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host_op_rate 965096 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 51452236494 # Simulator tick rate (ticks/s)
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host_mem_usage 677452 # Number of bytes of host memory used
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host_seconds 1006.21 # Real time elapsed on the host
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sim_insts 826333887 # Number of instructions simulated
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sim_ops 971088679 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu0.dtb.walker 69952 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 75072 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.inst 2290776 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 31969648 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 59200 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 65024 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 2387996 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 32286808 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 387264 # Number of bytes read from this memory
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system.physmem.bytes_read::total 69591740 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 2290776 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 2387996 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 4678772 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 60611648 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 15860 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 4720 # Number of bytes written to this memory
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system.physmem.bytes_written::total 60632228 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 1093 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 1173 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.inst 56454 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 499529 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 925 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 1016 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 57059 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 504491 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6051 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1127791 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 947057 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 1983 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 590 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 949630 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.dtb.walker 1351 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 1450 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 44248 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 617512 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 1143 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 1256 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 46125 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 623638 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 7480 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1344204 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 44248 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 46125 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 90373 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1170748 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1171146 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1170748 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 1351 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 1450 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 44248 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 617818 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 1143 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.itb.walker 1256 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 46125 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 623729 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 7480 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2515349 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 1127791 # Number of read requests accepted
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system.physmem.writeReqs 949630 # Number of write requests accepted
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system.physmem.readBursts 1127791 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 949630 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 72133184 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 45440 # Total number of bytes read from write queue
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system.physmem.bytesWritten 60631936 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 69591740 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 60632228 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 710 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 72704 # Per bank write bursts
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system.physmem.perBankRdBursts::1 73689 # Per bank write bursts
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system.physmem.perBankRdBursts::2 70161 # Per bank write bursts
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system.physmem.perBankRdBursts::3 65996 # Per bank write bursts
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system.physmem.perBankRdBursts::4 66834 # Per bank write bursts
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system.physmem.perBankRdBursts::5 71242 # Per bank write bursts
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system.physmem.perBankRdBursts::6 65196 # Per bank write bursts
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system.physmem.perBankRdBursts::7 62079 # Per bank write bursts
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system.physmem.perBankRdBursts::8 64428 # Per bank write bursts
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system.physmem.perBankRdBursts::9 108710 # Per bank write bursts
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system.physmem.perBankRdBursts::10 67339 # Per bank write bursts
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system.physmem.perBankRdBursts::11 66743 # Per bank write bursts
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system.physmem.perBankRdBursts::12 64268 # Per bank write bursts
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system.physmem.perBankRdBursts::13 71345 # Per bank write bursts
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system.physmem.perBankRdBursts::14 65944 # Per bank write bursts
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system.physmem.perBankRdBursts::15 70403 # Per bank write bursts
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system.physmem.perBankWrBursts::0 59852 # Per bank write bursts
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system.physmem.perBankWrBursts::1 61594 # Per bank write bursts
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system.physmem.perBankWrBursts::2 59825 # Per bank write bursts
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system.physmem.perBankWrBursts::3 58084 # Per bank write bursts
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system.physmem.perBankWrBursts::4 58217 # Per bank write bursts
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system.physmem.perBankWrBursts::5 60425 # Per bank write bursts
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system.physmem.perBankWrBursts::6 57000 # Per bank write bursts
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system.physmem.perBankWrBursts::7 56382 # Per bank write bursts
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system.physmem.perBankWrBursts::8 57853 # Per bank write bursts
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system.physmem.perBankWrBursts::9 59874 # Per bank write bursts
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system.physmem.perBankWrBursts::10 59285 # Per bank write bursts
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system.physmem.perBankWrBursts::11 60081 # Per bank write bursts
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system.physmem.perBankWrBursts::12 57131 # Per bank write bursts
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system.physmem.perBankWrBursts::13 62251 # Per bank write bursts
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system.physmem.perBankWrBursts::14 58136 # Per bank write bursts
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system.physmem.perBankWrBursts::15 61384 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 47 # Number of times write queue was full causing retry
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system.physmem.totGap 51771723764500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 43101 # Read request sizes (log2)
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system.physmem.readPktSize::3 13 # Read request sizes (log2)
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system.physmem.readPktSize::4 2 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 1084675 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 1 # Write request sizes (log2)
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system.physmem.writePktSize::3 2572 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 947057 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1101525 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 20079 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 401 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 446 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 533 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 506 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1087 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 624 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 265 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 323 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 167 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 114 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1567 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1516 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1491 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1477 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1452 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1441 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1422 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1410 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1392 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1376 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1369 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1356 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1334 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1323 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1312 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 13771 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 18027 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 54758 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 54058 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 55508 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 54068 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 53991 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 55072 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 55232 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 54714 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 55832 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 58265 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 55672 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 55559 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 58031 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 54737 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 53792 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 53604 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 2557 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 827 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 727 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 552 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 468 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 458 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 425 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 332 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 264 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 267 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 310 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 303 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::46 257 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::47 308 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::48 190 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 276 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::50 316 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::51 191 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 258 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::56 171 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 227 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::59 140 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 127 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 210 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::62 116 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 143 # What write queue length does an incoming req see
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|
system.physmem.bytesPerActivate::samples 442864 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::mean 299.787276 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::gmean 172.663870 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 330.837689 # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::0-127 176801 39.92% 39.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 107708 24.32% 64.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 38340 8.66% 72.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 22096 4.99% 77.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 15589 3.52% 81.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 11707 2.64% 84.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 10190 2.30% 86.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 8599 1.94% 88.30% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::1024-1151 51834 11.70% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 442864 # Bytes accessed per row activation
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|
system.physmem.rdPerTurnAround::samples 52780 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 21.354225 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 295.252681 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-2047 52773 99.99% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2048-4095 3 0.01% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::6144-8191 2 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::total 52780 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 52780 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 17.949488 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 17.151899 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 8.362849 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::0-3 96 0.18% 0.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::4-7 68 0.13% 0.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8-11 65 0.12% 0.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::12-15 113 0.21% 0.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 49413 93.62% 94.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 604 1.14% 95.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 382 0.72% 96.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 366 0.69% 96.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 106 0.20% 97.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 120 0.23% 97.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 251 0.48% 97.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 25 0.05% 97.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 347 0.66% 98.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 80 0.15% 98.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 21 0.04% 98.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 55 0.10% 98.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 264 0.50% 99.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 29 0.05% 99.29% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 20 0.04% 99.33% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 122 0.23% 99.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 176 0.33% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 4 0.01% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 2 0.00% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 3 0.01% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 10 0.02% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-163 4 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 52780 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 13931485499 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 35064254249 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 5635405000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12360.68 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31110.68 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 1.34 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 9.40 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 910554 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 721036 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 76.11 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 24921151.64 # Average gap between requests
|
|
system.physmem.pageHitRate 78.65 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 1716089760 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 936358500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 4273627800 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 3054535920 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 3381477484320 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 1299156215670 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 29923425135750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 34614039447720 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 668.589631 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 49779697907279 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 1728771720000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 263256805221 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 1631962080 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 890455500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 4517588400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 3084447600 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3381477484320 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 1291204023120 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 29930400751500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 34613206712520 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.573546 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 49791314720420 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1728771720000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 251640005830 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.walker.walks 115485 # Table walker walks requested
|
|
system.cpu0.dtb.walker.walksLong 115485 # Table walker walks initiated with long descriptors
|
|
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17906 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83637 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting
|
|
system.cpu0.dtb.walker.walkWaitTime::samples 115474 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::mean 0.346398 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::stdev 89.645919 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::0-2047 115472 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkWaitTime::total 115474 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::samples 101554 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::mean 25029.885578 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::gmean 21753.655577 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::stdev 15864.720522 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::0-65535 100973 99.43% 99.43% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8 0.01% 99.44% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 501 0.49% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 8 0.01% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 30 0.03% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.02% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walkCompletionTime::total 101554 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.dtb.walker.walksPending::samples -3996350676 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::mean 1.438404 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::0 1752015204 -43.84% -43.84% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::1 -5748365880 143.84% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walksPending::total -3996350676 # Table walker pending requests distribution
|
|
system.cpu0.dtb.walker.walkPageSizes::4K 83637 82.37% 82.37% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::2M 17906 17.63% 100.00% # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkPageSizes::total 101543 # Table walker page sizes translated
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 115485 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 115485 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101543 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101543 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.walker.walkRequestOrigin::total 217028 # Table walker requests started/completed, data/inst
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 77968786 # DTB read hits
|
|
system.cpu0.dtb.read_misses 88587 # DTB read misses
|
|
system.cpu0.dtb.write_hits 70658355 # DTB write hits
|
|
system.cpu0.dtb.write_misses 26898 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 51778 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 18574 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 67879 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 4111 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 9218 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 78057373 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 70685253 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 148627141 # DTB hits
|
|
system.cpu0.dtb.misses 115485 # DTB misses
|
|
system.cpu0.dtb.accesses 148742626 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.walker.walks 74042 # Table walker walks requested
|
|
system.cpu0.itb.walker.walksLong 74042 # Table walker walks initiated with long descriptors
|
|
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4198 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64736 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu0.itb.walker.walkWaitTime::samples 74042 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::0 74042 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkWaitTime::total 74042 # Table walker wait (enqueue to first request) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::samples 68934 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::mean 28581.273392 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::gmean 25349.599489 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::stdev 19061.356835 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::0-65535 68231 98.98% 98.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::65536-131071 3 0.00% 98.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::131072-196607 610 0.88% 99.87% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::196608-262143 10 0.01% 99.88% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::262144-327679 35 0.05% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walkCompletionTime::total 68934 # Table walker service (enqueue to completion) latency
|
|
system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution
|
|
system.cpu0.itb.walker.walkPageSizes::4K 64736 93.91% 93.91% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::2M 4198 6.09% 100.00% # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkPageSizes::total 68934 # Table walker page sizes translated
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74042 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74042 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 68934 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 68934 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.walker.walkRequestOrigin::total 142976 # Table walker requests started/completed, data/inst
|
|
system.cpu0.itb.inst_hits 413989239 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 74042 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 51778 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 18574 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 49997 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 414063281 # ITB inst accesses
|
|
system.cpu0.itb.hits 413989239 # DTB hits
|
|
system.cpu0.itb.misses 74042 # DTB misses
|
|
system.cpu0.itb.accesses 414063281 # DTB accesses
|
|
system.cpu0.numCycles 51772399583 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 15959 # number of quiesce instructions executed
|
|
system.cpu0.committedInsts 413737178 # Number of instructions committed
|
|
system.cpu0.committedOps 486128458 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 446921205 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 447031 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 24805806 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 62762528 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 446921205 # number of integer instructions
|
|
system.cpu0.num_fp_insts 447031 # number of float instructions
|
|
system.cpu0.num_int_register_reads 646154735 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 354190798 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 724381 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 372700 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 107222136 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 106914913 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 148617421 # number of memory refs
|
|
system.cpu0.num_load_insts 77964333 # Number of load instructions
|
|
system.cpu0.num_store_insts 70653088 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 50228896973.724121 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 1543502609.275879 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.029813 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.970187 # Percentage of idle cycles
|
|
system.cpu0.Branches 92293251 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 336607156 69.20% 69.20% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 1073484 0.22% 69.42% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 49277 0.01% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 55202 0.01% 69.45% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 77964333 16.03% 85.47% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 70653088 14.53% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 486402581 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 9229396 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.942744 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 287404842 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 9229908 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 31.138430 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 5830459500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 300.933674 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.009070 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.587761 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.412127 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 1196218197 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 1196218197 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 73007967 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 72737993 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 145745960 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 67086341 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 66998346 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 134084687 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 184406 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 186200 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 370606 # number of SoftPFReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162812 # number of WriteLineReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 166437 # number of WriteLineReq hits
|
|
system.cpu0.dcache.WriteLineReq_hits::total 329249 # number of WriteLineReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1644610 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1632284 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 3276894 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1785360 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1770652 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 3556012 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 140094308 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 139736339 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 279830647 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 140278714 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 139922539 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 280201253 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 2418380 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 2397518 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 4815898 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 985807 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 975481 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1961288 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 555377 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 547969 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 1103346 # number of SoftPFReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 614035 # number of WriteLineReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 608349 # number of WriteLineReq misses
|
|
system.cpu0.dcache.WriteLineReq_misses::total 1222384 # number of WriteLineReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141557 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 139184 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 280741 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 3404187 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 3372999 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 6777186 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 3959564 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 3920968 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 7880532 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41388359500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 41036783000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 82425142500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32787258000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 32868758500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 65656016500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 36378909000 # number of WriteLineReq miss cycles
|
|
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 36872056500 # number of WriteLineReq miss cycles
|
|
system.cpu0.dcache.WriteLineReq_miss_latency::total 73250965500 # number of WriteLineReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2154150500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2160127500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 4314278000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 80000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 82000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 162000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 74175617500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 73905541500 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 148081159000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 74175617500 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 73905541500 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 148081159000 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 75426347 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 75135511 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 150561858 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 68072148 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 67973827 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 136045975 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 739783 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 734169 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 1473952 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 776847 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 774786 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteLineReq_accesses::total 1551633 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1786167 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1771468 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 3557635 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1785361 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1770653 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 3556014 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 143498495 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 143109338 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 286607833 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 144238278 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 143843507 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 288081785 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032063 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031909 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.031986 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014482 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014351 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.014416 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.750730 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.746380 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.748563 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.790419 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.785183 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787805 # miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079252 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078570 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078912 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.023723 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023569 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.023646 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027452 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027259 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.027355 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17114.084428 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17116.360753 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17115.217660 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33259.307349 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33694.924350 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 33475.969108 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 59245.660264 # average WriteLineReq miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 60610.038810 # average WriteLineReq miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 59924.676288 # average WriteLineReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15217.548408 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15519.941229 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15367.466811 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 80000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 81000 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21789.524929 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21910.928969 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 21849.947604 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18733.279093 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18848.799965 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 18790.756639 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 7232763 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 7232763 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 11983 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 10521 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 22504 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 11535 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 9717 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 21252 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 33493 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 33253 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 66746 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 23518 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 20238 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 43756 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 23518 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 20238 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 43756 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2406397 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2386997 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 4793394 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 974272 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 965764 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 1940036 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 554427 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 547125 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1101552 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 614035 # number of WriteLineReq MSHR misses
|
|
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 608349 # number of WriteLineReq MSHR misses
|
|
system.cpu0.dcache.WriteLineReq_mshr_misses::total 1222384 # number of WriteLineReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 108064 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 105931 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 213995 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3380669 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3352761 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 6733430 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 3935096 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 3899886 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 7834982 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16498 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17202 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33700 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16718 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 16989 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33216 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 34191 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67407 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38272403000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 38035124000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 76307527000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31289337500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31445195500 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 62734533000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10450714000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10117444000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20568158000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 35764874000 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 36263707500 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 72028581500 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1482346000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1473647000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2955993000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 79000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 81000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 69561740500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 69480319500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 139042060000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80012454500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 79597763500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 159610218000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3013571000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3185791500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6199362500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2991819500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3225760000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6217579500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6005390500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6411551500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12416942000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031904 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031769 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031837 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014312 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014208 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014260 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749445 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745230 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747346 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.790419 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.785183 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787805 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060501 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059798 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060151 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023559 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023428 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023494 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027112 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.027197 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15904.442617 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15934.299038 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15919.310409 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32115.607859 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32559.916812 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32336.788080 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18849.576229 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18492.015536 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18671.980987 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58245.660264 # average WriteLineReq mshr miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59610.038810 # average WriteLineReq mshr miss latency
|
|
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58924.676288 # average WriteLineReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13717.297157 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13911.385713 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13813.374144 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 79000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20576.323947 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20723.314158 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20649.514438 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20333.037491 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20410.279557 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20371.484963 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182662.807613 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185198.901291 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183957.344214 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178957.979423 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189873.447525 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.592963 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180798.124398 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187521.613875 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184208.494667 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 13374068 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.782255 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 813470115 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 13374580 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 60.822105 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 61705740500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 283.742263 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 228.039992 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.554184 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.445391 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 840219285 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 840219285 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 407282786 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 406187329 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 813470115 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 407282786 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 406187329 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 813470115 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 407282786 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 406187329 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 813470115 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 6706453 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 6668132 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 13374585 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 6706453 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 6668132 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 13374585 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 6706453 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 6668132 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 13374585 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 91505309500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 91196930000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 182702239500 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 91505309500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 91196930000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 182702239500 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 91505309500 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 91196930000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 182702239500 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 413989239 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 412855461 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 826844700 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 413989239 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 412855461 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 826844700 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 413989239 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 412855461 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 826844700 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016200 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016151 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.016175 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016200 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016151 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.016175 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016200 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016151 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.016175 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13644.367522 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13676.533398 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 13660.404379 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13644.367522 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13676.533398 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 13660.404379 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13644.367522 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13676.533398 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 13660.404379 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.writebacks::writebacks 13374068 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 13374068 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6706453 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6668132 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 13374585 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 6706453 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 6668132 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 13374585 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 6706453 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 6668132 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 13374585 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 22062 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 21063 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 22062 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 21063 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84798856500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 84528798000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 169327654500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84798856500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 84528798000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 169327654500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84798856500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 84528798000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 169327654500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5436799500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436799500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016200 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016151 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016175 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016200 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016151 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.016175 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016200 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016151 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.016175 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12644.367522 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12676.533398 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12660.404379 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12644.367522 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12676.533398 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12660.404379 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12644.367522 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12676.533398 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12660.404379 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.walker.walks 117928 # Table walker walks requested
|
|
system.cpu1.dtb.walker.walksLong 117928 # Table walker walks initiated with long descriptors
|
|
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 18037 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85683 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting
|
|
system.cpu1.dtb.walker.walkWaitTime::samples 117922 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::0 117922 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkWaitTime::total 117922 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::samples 103726 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::mean 24721.569327 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::gmean 21421.072660 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::stdev 15374.016898 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::0-32767 68517 66.06% 66.06% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 34673 33.43% 99.48% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 1 0.00% 99.48% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 7 0.01% 99.49% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 395 0.38% 99.87% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 59 0.06% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 7 0.01% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 7 0.01% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 26 0.03% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 7 0.01% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::393216-425983 18 0.02% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::425984-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walkCompletionTime::total 103726 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.dtb.walker.walksPending::samples 7196110108 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::mean 0.793869 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::stdev 0.404526 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::0 1483343204 20.61% 20.61% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::1 5712766904 79.39% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walksPending::total 7196110108 # Table walker pending requests distribution
|
|
system.cpu1.dtb.walker.walkPageSizes::4K 85684 82.61% 82.61% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::2M 18037 17.39% 100.00% # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkPageSizes::total 103721 # Table walker page sizes translated
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 117928 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 117928 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103721 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103721 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.walker.walkRequestOrigin::total 221649 # Table walker requests started/completed, data/inst
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 77658339 # DTB read hits
|
|
system.cpu1.dtb.read_misses 91087 # DTB read misses
|
|
system.cpu1.dtb.write_hits 70545022 # DTB write hits
|
|
system.cpu1.dtb.write_misses 26841 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 51774 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 19088 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 488 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 67576 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 4039 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 9302 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 77749426 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 70571863 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 148203361 # DTB hits
|
|
system.cpu1.dtb.misses 117928 # DTB misses
|
|
system.cpu1.dtb.accesses 148321289 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.walker.walks 75461 # Table walker walks requested
|
|
system.cpu1.itb.walker.walksLong 75461 # Table walker walks initiated with long descriptors
|
|
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4165 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66112 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu1.itb.walker.walkWaitTime::samples 75461 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::0 75461 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkWaitTime::total 75461 # Table walker wait (enqueue to first request) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::samples 70277 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::mean 28243.080951 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::gmean 25107.153761 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::stdev 18108.319299 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::0-65535 69604 99.04% 99.04% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.05% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::131072-196607 599 0.85% 99.90% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::196608-262143 10 0.01% 99.91% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::262144-327679 30 0.04% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::327680-393215 11 0.02% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walkCompletionTime::total 70277 # Table walker service (enqueue to completion) latency
|
|
system.cpu1.itb.walker.walksPending::samples 1449734704 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::0 1449734704 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walksPending::total 1449734704 # Table walker pending requests distribution
|
|
system.cpu1.itb.walker.walkPageSizes::4K 66112 94.07% 94.07% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::2M 4165 5.93% 100.00% # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkPageSizes::total 70277 # Table walker page sizes translated
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75461 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75461 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 70277 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 70277 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.walker.walkRequestOrigin::total 145738 # Table walker requests started/completed, data/inst
|
|
system.cpu1.itb.inst_hits 412855461 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 75461 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 51774 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 19088 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 488 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 50522 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 412930922 # ITB inst accesses
|
|
system.cpu1.itb.hits 412855461 # DTB hits
|
|
system.cpu1.itb.misses 75461 # DTB misses
|
|
system.cpu1.itb.accesses 412930922 # DTB accesses
|
|
system.cpu1.numCycles 51771053820 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu1.committedInsts 412596709 # Number of instructions committed
|
|
system.cpu1.committedOps 484960221 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 445873459 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 452061 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 24841157 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 62479389 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 445873459 # number of integer instructions
|
|
system.cpu1.num_fp_insts 452061 # number of float instructions
|
|
system.cpu1.num_int_register_reads 645239510 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 353339457 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 727891 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 384564 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 106622832 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 106320597 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 148192340 # number of memory refs
|
|
system.cpu1.num_load_insts 77653796 # Number of load instructions
|
|
system.cpu1.num_store_insts 70538544 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 50233192566.855270 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 1537861253.144726 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.029705 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.970295 # Percentage of idle cycles
|
|
system.cpu1.Branches 92059897 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 335900158 69.22% 69.22% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 1042632 0.21% 69.44% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 47706 0.01% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 57197 0.01% 69.46% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 77653796 16.00% 85.46% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 70538544 14.54% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 485240035 # Class of executed instruction
|
|
system.iobus.trans_dist::ReadReq 40316 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40316 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230990 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 230990 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 353774 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7334392 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7492312 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 42146500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 25708000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 38602000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 566763189 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 147750000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 115482 # number of replacements
|
|
system.iocache.tags.tagsinuse 10.442873 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 13183784926000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 5.854402 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 4.588472 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.365900 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.286779 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.652680 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1039812 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1039812 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8831 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8868 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 8831 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 8871 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 8831 # number of overall misses
|
|
system.iocache.overall_misses::total 8871 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::realview.ide 1624550168 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 1629620168 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 13409547021 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 13409547021 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 1624550168 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 1629971168 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 1624550168 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 1629971168 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8831 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8868 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 8831 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 8871 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 8831 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 8871 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 183959.932963 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 183764.114569 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.646263 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 125717.646263 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 183959.932963 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 183741.536242 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 183959.932963 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 183741.536242 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 32143 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3321 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 9.678711 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
|
system.iocache.writebacks::total 106631 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 8831 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 8868 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 8831 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 8871 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 8831 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 8871 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183000168 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 1186220168 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071216147 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 8071216147 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 1183000168 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 1186421168 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 1183000168 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 1186421168 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133959.932963 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 133764.114569 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75669.543117 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75669.543117 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 133959.932963 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 133741.536242 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 133959.932963 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 133741.536242 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 989396 # number of replacements
|
|
system.l2c.tags.tagsinuse 65299.098652 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 41673385 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 1051747 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 39.623013 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 56075802500 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 37757.667550 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 108.548487 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 160.943912 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 3976.741383 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 9619.817220 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 97.192514 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.itb.walker 146.379867 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 4603.768547 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 8828.039172 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.576136 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001656 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002456 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.060680 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.146787 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001483 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.itb.walker 0.002234 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.070248 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.134705 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.996385 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 252 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 62099 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 252 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 2415 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 5492 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 53743 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.947556 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 372018005 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 372018005 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 204641 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 155167 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 205544 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 156704 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 722056 # number of ReadReq hits
|
|
system.l2c.WritebackDirty_hits::writebacks 7232763 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 7232763 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 13372479 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 13372479 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 4450 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 4428 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 8878 # number of UpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 799766 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 788996 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 1588762 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 6672024 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 6632136 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 13304160 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 2959925 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 2932956 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 5892881 # number of ReadSharedReq hits
|
|
system.l2c.InvalidateReq_hits::cpu0.data 376779 # number of InvalidateReq hits
|
|
system.l2c.InvalidateReq_hits::cpu1.data 366298 # number of InvalidateReq hits
|
|
system.l2c.InvalidateReq_hits::total 743077 # number of InvalidateReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 204641 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 155167 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 6672024 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 3759691 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 205544 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 156704 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 6632136 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 3721952 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 21507859 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 204641 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 155167 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 6672024 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 3759691 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 205544 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 156704 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 6632136 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 3721952 # number of overall hits
|
|
system.l2c.overall_hits::total 21507859 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1093 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 1173 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 925 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.itb.walker 1016 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 4207 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 16132 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 16422 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 32554 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 153924 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 155918 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 309842 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 34429 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 35996 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 70425 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 108963 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 107097 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 216060 # number of ReadSharedReq misses
|
|
system.l2c.InvalidateReq_misses::cpu0.data 237256 # number of InvalidateReq misses
|
|
system.l2c.InvalidateReq_misses::cpu1.data 242051 # number of InvalidateReq misses
|
|
system.l2c.InvalidateReq_misses::total 479307 # number of InvalidateReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1093 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1173 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 34429 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 262887 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 925 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.itb.walker 1016 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 35996 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 263015 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 600534 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1093 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1173 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 34429 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 262887 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 925 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.itb.walker 1016 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 35996 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 263015 # number of overall misses
|
|
system.l2c.overall_misses::total 600534 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 148570500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 161699000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 125931000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 138911000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 575111500 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 649759500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 653789000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 1303548500 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 77500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 157000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 20101505000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 20361051500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 40462556500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 4550795500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 4757748000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 9308543500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 14485135500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 14232733000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 28717868500 # number of ReadSharedReq miss cycles
|
|
system.l2c.InvalidateReq_miss_latency::cpu0.data 30887637000 # number of InvalidateReq miss cycles
|
|
system.l2c.InvalidateReq_miss_latency::cpu1.data 31505054500 # number of InvalidateReq miss cycles
|
|
system.l2c.InvalidateReq_miss_latency::total 62392691500 # number of InvalidateReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 148570500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 161699000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 4550795500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 34586640500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 125931000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.itb.walker 138911000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 4757748000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 34593784500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 79064080000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 148570500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 161699000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 4550795500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 34586640500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 125931000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.itb.walker 138911000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 4757748000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 34593784500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 79064080000 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 205734 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 156340 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 206469 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 157720 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 726263 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::writebacks 7232763 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 7232763 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 13372479 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 13372479 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 20582 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 20850 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 41432 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 953690 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 944914 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 1898604 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 6706453 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 6668132 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 13374585 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 3068888 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 3040053 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 6108941 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::cpu0.data 614035 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::cpu1.data 608349 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.InvalidateReq_accesses::total 1222384 # number of InvalidateReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 205734 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 156340 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 6706453 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 4022578 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 206469 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 157720 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 6668132 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 3984967 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 22108393 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 205734 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 156340 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 6706453 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 4022578 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 206469 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 157720 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 6668132 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 3984967 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 22108393 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005313 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.007503 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004480 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.006442 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.005793 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.783792 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.787626 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.785721 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.161398 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.165008 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.163195 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.005134 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005398 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.005266 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.035506 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.035229 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.035368 # miss rate for ReadSharedReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.386388 # miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.397882 # miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_miss_rate::total 0.392108 # miss rate for InvalidateReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.005313 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.007503 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.005134 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.065353 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004480 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.itb.walker 0.006442 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.005398 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.066002 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.027163 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.005313 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.007503 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.005134 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.065353 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004480 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.itb.walker 0.006442 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.005398 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.066002 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.027163 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 135929.094236 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 137850.809889 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 136141.621622 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 136723.425197 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 136703.470406 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 40277.677907 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39811.776885 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 40042.652209 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 77500 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 78500 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 130593.702087 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130588.203415 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 130590.935057 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 132179.136774 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132174.352706 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 132176.691516 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132936.276534 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 132895.720702 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 132916.173748 # average ReadSharedReq miss latency
|
|
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 130186.958391 # average InvalidateReq miss latency
|
|
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130158.745471 # average InvalidateReq miss latency
|
|
system.l2c.InvalidateReq_avg_miss_latency::total 130172.710810 # average InvalidateReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135929.094236 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 137850.809889 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 132179.136774 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 131564.666568 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 136141.621622 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 136723.425197 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 132174.352706 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 131527.800696 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 131656.292566 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135929.094236 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 137850.809889 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 132179.136774 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 131564.666568 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 136141.621622 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 136723.425197 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 132174.352706 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 131527.800696 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 131656.292566 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 840426 # number of writebacks
|
|
system.l2c.writebacks::total 840426 # number of writebacks
|
|
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1093 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1173 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 925 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1016 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 4207 # number of ReadReq MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 16132 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 16422 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 32554 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 153924 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 155918 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 309842 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 34429 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 35996 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 70425 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 108963 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 107097 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 216060 # number of ReadSharedReq MSHR misses
|
|
system.l2c.InvalidateReq_mshr_misses::cpu0.data 237256 # number of InvalidateReq MSHR misses
|
|
system.l2c.InvalidateReq_mshr_misses::cpu1.data 242051 # number of InvalidateReq MSHR misses
|
|
system.l2c.InvalidateReq_mshr_misses::total 479307 # number of InvalidateReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.dtb.walker 1093 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.itb.walker 1173 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 34429 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 262887 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 925 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.itb.walker 1016 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 35996 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 263015 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 600534 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.dtb.walker 1093 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.itb.walker 1173 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 34429 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 262887 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 925 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.itb.walker 1016 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 35996 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 263015 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 600534 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 22062 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16498 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 21063 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17202 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 76825 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16718 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 16989 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 33707 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 22062 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33216 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 21063 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 34191 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 110532 # number of overall MSHR uncacheable misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 137640500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 149969000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 116681000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 128751000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 533041500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1096016000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1115563500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 2211579500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 67500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 69500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 18562265000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 18801871500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 37364136500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 4206505500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 4397788000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 8604293500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 13395505500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13161763000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 26557268500 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 28515077000 # number of InvalidateReq MSHR miss cycles
|
|
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 29084544500 # number of InvalidateReq MSHR miss cycles
|
|
system.l2c.InvalidateReq_mshr_miss_latency::total 57599621500 # number of InvalidateReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 137640500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 149969000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 4206505500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 31957770500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 116681000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 128751000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 4397788000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 31963634500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 73058740000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 137640500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 149969000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 4206505500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 31957770500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 116681000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 128751000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 4397788000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 31963634500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 73058740000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2504816500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2806974500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2392920500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2970370000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 10675081500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2799558000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3030380000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 5829938000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2504816500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5606532500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2392920500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6000750000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 16505019500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005313 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007503 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004480 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.006442 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.005793 # mshr miss rate for ReadReq accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.783792 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.787626 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.785721 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.161398 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.165008 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.163195 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005134 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005398 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005266 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.035506 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035229 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.035368 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.386388 # mshr miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.397882 # mshr miss rate for InvalidateReq accesses
|
|
system.l2c.InvalidateReq_mshr_miss_rate::total 0.392108 # mshr miss rate for InvalidateReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005313 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007503 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005134 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.065353 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004480 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.006442 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005398 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.066002 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.027163 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005313 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007503 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005134 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.065353 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004480 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006442 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005398 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.066002 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.027163 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125929.094236 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127850.809889 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126141.621622 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 126723.425197 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 126703.470406 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67940.490950 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67931.037632 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67935.722185 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120593.702087 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120588.203415 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 120590.935057 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122179.136774 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122174.352706 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122176.691516 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122936.276534 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122895.720702 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122916.173748 # average ReadSharedReq mshr miss latency
|
|
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120186.958391 # average InvalidateReq mshr miss latency
|
|
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120158.745471 # average InvalidateReq mshr miss latency
|
|
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120172.710810 # average InvalidateReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125929.094236 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127850.809889 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122179.136774 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121564.666568 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126141.621622 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126723.425197 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122174.352706 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121527.800696 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 121656.292566 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125929.094236 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127850.809889 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122179.136774 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121564.666568 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126141.621622 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126723.425197 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122174.352706 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121527.800696 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 121656.292566 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170140.289732 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172675.851645 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138953.224862 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167457.710252 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178373.064924 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.266621 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168790.116209 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175506.712293 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 149323.449318 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 76825 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 376385 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 33707 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 33707 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 947057 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 156816 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 33121 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 7 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 788585 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 788585 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 299560 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3270790 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 3400476 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237068 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 237068 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 3637544 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 123012320 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 123182134 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7211648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7211648 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 130393782 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 3477 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 2442384 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 2442384 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 2442384 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 106884000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 5641500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 6231197843 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 5914461286 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 44673503 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
|
|
system.toL2Bus.snoop_filter.tot_requests 45780480 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 23175972 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 2220 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 2220 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 1179802 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 20664144 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 8179867 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 13374068 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 2154454 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 41435 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 41437 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 1898604 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 1898604 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 13374585 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 6117809 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 1329048 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateResp 1222384 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40209488 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27907755 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 753930 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1075310 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 69946483 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1712086292 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 975622370 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2512480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3297624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 2693518766 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 1597993 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 25079917 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.021333 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.144493 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 24544878 97.87% 97.87% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 535039 2.13% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 25079917 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 43855145000 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 1530888 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 20105002500 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 12693791976 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 439870000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 663107000 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|