2006-09-01 23:59:36 +02:00
---------- Begin Simulation Statistics ----------
2015-09-15 15:14:09 +02:00
sim_seconds 0.000012 # Number of seconds simulated
2016-04-08 18:01:45 +02:00
sim_ticks 12409500 # Number of ticks simulated
final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2006-09-01 23:59:36 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-05-31 12:07:18 +02:00
host_inst_rate 87055 # Simulator instruction rate (inst/s)
host_op_rate 87008 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 452104980 # Simulator tick rate (ticks/s)
host_mem_usage 247976 # Number of bytes of host memory used
host_seconds 0.03 # Real time elapsed on the host
2006-09-01 23:59:36 +02:00
sim_insts 2387 # Number of instructions simulated
2012-02-12 23:07:43 +01:00
sim_ops 2387 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
2014-09-03 13:42:59 +02:00
system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
2016-04-08 18:01:45 +02:00
system.physmem.bw_read::cpu.inst 964422418 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 438373827 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1402796245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 964422418 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 964422418 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 964422418 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 438373827 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1402796245 # Total bandwidth to/from this memory (bytes/s)
2014-09-03 13:42:59 +02:00
system.physmem.readReqs 272 # Number of read requests accepted
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
2014-09-03 13:42:59 +02:00
system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
2014-09-03 13:42:59 +02:00
system.physmem.bytesReadDRAM 17408 # Total number of bytes read from DRAM
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
2014-09-03 13:42:59 +02:00
system.physmem.bytesReadSys 17408 # Total read bytes from the system interface side
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 0 # Per bank write bursts
system.physmem.perBankRdBursts::1 1 # Per bank write bursts
system.physmem.perBankRdBursts::2 2 # Per bank write bursts
system.physmem.perBankRdBursts::3 24 # Per bank write bursts
system.physmem.perBankRdBursts::4 18 # Per bank write bursts
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
system.physmem.perBankRdBursts::6 24 # Per bank write bursts
system.physmem.perBankRdBursts::7 37 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::8 60 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::9 2 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::10 15 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::11 9 # Per bank write bursts
system.physmem.perBankRdBursts::12 17 # Per bank write bursts
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::13 50 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.perBankRdBursts::14 12 # Per bank write bursts
system.physmem.perBankRdBursts::15 1 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
2016-04-08 18:01:45 +02:00
system.physmem.totGap 12313000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2014-09-03 13:42:59 +02:00
system.physmem.readPktSize::6 272 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
2016-04-08 18:01:45 +02:00
system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 81 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
2015-03-02 11:04:20 +01:00
system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation
2015-07-03 16:15:03 +02:00
system.physmem.bytesPerActivate::mean 398.222222 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 237.741650 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 358.174986 # Bytes accessed per row activation
2015-03-02 11:04:20 +01:00
system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation
2016-04-08 18:01:45 +02:00
system.physmem.totQLat 1652750 # Total ticks spent queuing
system.physmem.totMemAccLat 6752750 # Total ticks spent from burst creation until serviced by the DRAM
2014-09-03 13:42:59 +02:00
system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers
2016-04-08 18:01:45 +02:00
system.physmem.avgQLat 6076.29 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-04-08 18:01:45 +02:00
system.physmem.avgMemAccLat 24826.29 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1402.80 # Average DRAM read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
2016-04-08 18:01:45 +02:00
system.physmem.avgRdBWSys 1402.80 # Average system read bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-04-08 18:01:45 +02:00
system.physmem.busUtil 10.96 # Data bus utilization in percentage
system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
2016-04-08 18:01:45 +02:00
system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
2015-03-02 11:04:20 +01:00
system.physmem.readRowHits 226 # Number of row buffer hits during reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
2015-03-02 11:04:20 +01:00
system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
2016-04-08 18:01:45 +02:00
system.physmem.avgGap 45268.38 # Average gap between requests
2015-03-02 11:04:20 +01:00
system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined
2014-12-23 15:31:20 +01:00
system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ)
2015-07-03 16:15:03 +02:00
system.physmem_0.readEnergy 592800 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ)
2015-07-03 16:15:03 +02:00
system.physmem_0.totalEnergy 6707115 # Total energy per rank (pJ)
system.physmem_0.averagePower 833.570297 # Core power per rank (mW)
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::REF 260000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-03-02 11:04:20 +01:00
system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-03-02 11:04:20 +01:00
system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
2015-07-03 16:15:03 +02:00
system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ)
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ)
2015-03-02 11:04:20 +01:00
system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ)
2015-07-03 16:15:03 +02:00
system.physmem_1.totalEnergy 6969270 # Total energy per rank (pJ)
system.physmem_1.averagePower 866.151313 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 708000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::REF 260000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-03-02 11:04:20 +01:00
system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.lookups 1003 # Number of BP lookups
system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 688 # Number of BTB lookups
system.cpu.branchPred.BTBHits 176 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-04-08 18:01:45 +02:00
system.cpu.branchPred.BTBHitPct 25.581395 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 101 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 3 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 98 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
2016-04-08 18:01:45 +02:00
system.cpu.dtb.read_hits 712 # DTB read hits
system.cpu.dtb.read_misses 13 # DTB read misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.read_acv 1 # DTB read access violations
2016-04-08 18:01:45 +02:00
system.cpu.dtb.read_accesses 725 # DTB read accesses
system.cpu.dtb.write_hits 349 # DTB write hits
system.cpu.dtb.write_misses 17 # DTB write misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
2016-04-08 18:01:45 +02:00
system.cpu.dtb.write_accesses 366 # DTB write accesses
system.cpu.dtb.data_hits 1061 # DTB hits
system.cpu.dtb.data_misses 30 # DTB misses
2011-07-10 19:56:09 +02:00
system.cpu.dtb.data_acv 1 # DTB access violations
2016-04-08 18:01:45 +02:00
system.cpu.dtb.data_accesses 1091 # DTB accesses
system.cpu.itb.fetch_hits 878 # ITB hits
system.cpu.itb.fetch_misses 32 # ITB misses
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
2016-04-08 18:01:45 +02:00
system.cpu.itb.fetch_accesses 910 # ITB accesses
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
2016-04-08 18:01:45 +02:00
system.cpu.numCycles 24820 # number of cpu cycles simulated
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-04-08 18:01:45 +02:00
system.cpu.fetch.icacheStallCycles 4371 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 6065 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1003 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 400 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1173 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing
2012-10-30 14:35:32 +01:00
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
2016-04-08 18:01:45 +02:00
system.cpu.fetch.PendingTrapStallCycles 1146 # Number of stall cycles due to pending traps
2012-10-30 14:35:32 +01:00
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
2016-04-08 18:01:45 +02:00
system.cpu.fetch.CacheLines 878 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 6955 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.872035 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.274710 # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-04-08 18:01:45 +02:00
system.cpu.fetch.rateDist::0 5922 85.15% 85.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 27 0.39% 85.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 100 1.44% 86.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 87 1.25% 88.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 141 2.03% 90.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 81 1.16% 91.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 46 0.66% 92.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 76 1.09% 93.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 475 6.83% 100.00% # Number of instructions fetched each cycle (Total)
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2016-04-08 18:01:45 +02:00
system.cpu.fetch.rateDist::total 6955 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.040411 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.244359 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 5210 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 623 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 919 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch
2015-09-15 15:14:09 +02:00
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
2016-04-08 18:01:45 +02:00
system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode
2015-09-15 15:14:09 +02:00
system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode
2016-04-08 18:01:45 +02:00
system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 5285 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 327 # Number of cycles rename is blocking
2015-07-03 16:15:03 +02:00
system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst
2016-04-08 18:01:45 +02:00
system.cpu.rename.RunCycles 881 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename
2015-09-15 15:14:09 +02:00
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
2016-04-08 18:01:45 +02:00
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
system.cpu.rename.RenamedOperands 3638 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5669 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5662 # Number of integer rename lookups
2013-10-16 16:44:12 +02:00
system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups
2011-07-10 19:56:09 +02:00
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
2016-04-08 18:01:45 +02:00
system.cpu.rename.UndoneMaps 1870 # Number of HB maps that are undone due to squashing
2011-07-10 19:56:09 +02:00
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
2016-04-08 18:01:45 +02:00
system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 846 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
2015-09-15 15:14:09 +02:00
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqInstsAdded 4387 # Number of instructions added to the IQ (excludes non-spec)
2012-06-29 17:19:03 +02:00
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
2016-04-08 18:01:45 +02:00
system.cpu.iq.iqInstsIssued 3758 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 28 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph
2012-06-29 17:19:03 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::samples 6955 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.540331 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.279888 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::0 5508 79.19% 79.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 469 6.74% 85.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 342 4.92% 90.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 254 3.65% 94.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 193 2.77% 97.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 103 1.48% 98.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 56 0.81% 99.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2016-04-08 18:01:45 +02:00
system.cpu.iq.issued_per_cycle::total 6955 # Number of insts issued each cycle
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-04-08 18:01:45 +02:00
system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 31 50.82% 60.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 24 39.34% 100.00% # attempts to use FU when none available
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::IntAlu 2627 69.90% 69.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.03% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.93% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 757 20.14% 90.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Type of FU issued
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-04-08 18:01:45 +02:00
system.cpu.iq.FU_type_0::total 3758 # Type of FU issued
system.cpu.iq.rate 0.151410 # Inst issue rate
system.cpu.iq.fu_busy_cnt 61 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 14547 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
2016-04-08 18:01:45 +02:00
system.cpu.iq.int_alu_accesses 3812 # Number of integer alu accesses
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 431 # Number of loads squashed
2014-09-03 13:42:59 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
2016-04-08 18:01:45 +02:00
system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 297 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 846 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions
2012-06-29 17:19:03 +02:00
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
2016-04-08 18:01:45 +02:00
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
2015-07-03 16:15:03 +02:00
system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations
2016-04-08 18:01:45 +02:00
system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 3634 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 727 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-04-08 18:01:45 +02:00
system.cpu.iew.exec_nop 307 # number of nop insts executed
2015-09-15 15:14:09 +02:00
system.cpu.iew.exec_refs 1093 # number of memory reference insts executed
2016-04-08 18:01:45 +02:00
system.cpu.iew.exec_branches 599 # Number of branches executed
system.cpu.iew.exec_stores 366 # Number of stores executed
system.cpu.iew.exec_rate 0.146414 # Inst execution rate
system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 3425 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1633 # num instructions producing a value
system.cpu.iew.wb_consumers 2097 # num instructions consuming a value
system.cpu.iew.wb_rate 0.137994 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit
2006-09-01 23:59:36 +02:00
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
2016-04-08 18:01:45 +02:00
system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 6540 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.393884 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.249766 # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-04-08 18:01:45 +02:00
system.cpu.commit.committed_per_cycle::0 5669 86.68% 86.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 198 3.03% 89.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 318 4.86% 94.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 63 0.96% 97.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 37 0.57% 98.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-04-08 18:01:45 +02:00
system.cpu.commit.committed_per_cycle::total 6540 # Number of insts commited each cycle
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 709 # Number of memory references committed
2011-04-20 03:45:23 +02:00
system.cpu.commit.loads 415 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
2011-07-10 19:56:09 +02:00
system.cpu.commit.branches 396 # Number of branches committed
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
2016-04-08 18:01:45 +02:00
system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 10930 # The number of ROB reads
system.cpu.rob.rob_writes 9815 # The number of ROB writes
system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 17865 # Total number of cycles that the CPU has spent unscheduled due to idling
2006-09-01 23:59:36 +02:00
system.cpu.committedInsts 2387 # Number of Instructions Simulated
2012-02-12 23:07:43 +01:00
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
2016-04-08 18:01:45 +02:00
system.cpu.cpi 10.397989 # CPI: Cycles Per Instruction
system.cpu.cpi_total 10.397989 # CPI: Total CPI of All Threads
system.cpu.ipc 0.096172 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.096172 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4383 # number of integer regfile reads
system.cpu.int_regfile_writes 2640 # number of integer regfile writes
2011-07-10 19:56:09 +02:00
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.tagsinuse 45.439304 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 45.439304 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.011094 # Average percentage of cache occupancy
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
2016-04-08 18:01:45 +02:00
system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_hits::cpu.data 735 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 735 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 735 # number of overall hits
system.cpu.dcache.overall_hits::total 735 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
system.cpu.dcache.overall_misses::total 182 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6673500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6673500 # number of ReadReq miss cycles
2015-09-15 15:14:09 +02:00
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5672000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5672000 # number of WriteReq miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 12345500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12345500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12345500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12345500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 623 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 623 # number of ReadReq accesses(hits+misses)
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_accesses::cpu.data 917 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 917 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 917 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 917 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.162119 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.162119 # miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.198473 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.198473 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.198473 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.198473 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66074.257426 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66074.257426 # average ReadReq miss latency
2015-09-15 15:14:09 +02:00
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67832.417582 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67832.417582 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 256 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked
2014-12-23 15:31:20 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits
2014-12-23 15:31:20 +01:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4797000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4797000 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6648000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6648000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6648000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6648000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.097913 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.097913 # mshr miss rate for ReadReq accesses
2014-12-23 15:31:20 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.092694 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.092694 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78639.344262 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78639.344262 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency
2016-04-08 18:01:45 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.replacements 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks.
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.avg_refs 3.342246 # Average number of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 90.399218 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.044140 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.044140 # Average percentage of cache occupancy
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id
2016-04-08 18:01:45 +02:00
system.cpu.icache.tags.tag_accesses 1943 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1943 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 625 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 625 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 625 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 625 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 625 # number of overall hits
system.cpu.icache.overall_hits::total 625 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses
system.cpu.icache.overall_misses::total 253 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18863999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 18863999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 18863999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 18863999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18863999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18863999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 878 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 878 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 878 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 878 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 878 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 878 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288155 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.288155 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.288155 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.288155 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.288155 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.288155 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74561.260870 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 74561.260870 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 74561.260870 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 74561.260870 # average overall miss latency
2015-07-03 16:15:03 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2013-05-30 18:54:18 +02:00
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-04-08 18:01:45 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses
2016-04-08 18:01:45 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14160499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 14160499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14160499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 14160499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14160499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 14160499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.212984 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.212984 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.212984 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.593583 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.593583 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.557444 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.703859 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002764 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000876 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.003640 # Average percentage of cache occupancy
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id
2015-09-15 15:14:09 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 187 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.overall_misses::total 272 # number of overall misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13879000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13879000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4705500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4705500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 13879000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6519000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 20398000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 13879000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6519000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 20398000 # number of overall miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 187 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses)
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74219.251337 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74219.251337 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77139.344262 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77139.344262 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74992.647059 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74992.647059 # average overall miss latency
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 187 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12009000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12009000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4095500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4095500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12009000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5669000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17678000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12009000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5669000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17678000 # number of overall MSHR miss cycles
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency
2016-04-08 18:01:45 +02:00
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64219.251337 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64219.251337 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67139.344262 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67139.344262 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadCleanReq 187 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks)
2015-09-15 15:14:09 +02:00
system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadResp 248 # Transaction distribution
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadSharedReq 248 # Transaction distribution
2014-12-23 15:31:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 272 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 272 # Request fanout histogram
2016-04-08 18:01:45 +02:00
system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
2016-04-08 18:01:45 +02:00
system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.6 # Layer utilization (%)
2006-09-01 23:59:36 +02:00
---------- End Simulation Statistics ----------
