2006-09-01 23:59:36 +02:00
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---------- Begin Simulation Statistics ----------
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2011-07-10 19:56:09 +02:00
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sim_seconds 0.000007 # Number of seconds simulated
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2012-02-13 19:30:30 +01:00
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sim_ticks 7015000 # Number of ticks simulated
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final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2006-09-01 23:59:36 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-06-05 07:23:16 +02:00
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host_inst_rate 16156 # Simulator instruction rate (inst/s)
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host_op_rate 16154 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 47467285 # Simulator tick rate (ticks/s)
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host_mem_usage 214556 # Number of bytes of host memory used
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host_seconds 0.15 # Real time elapsed on the host
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2006-09-01 23:59:36 +02:00
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sim_insts 2387 # Number of instructions simulated
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2012-02-12 23:07:43 +01:00
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sim_ops 2387 # Number of ops (including micro ops) simulated
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2012-06-05 07:23:16 +02:00
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system.physmem.bytes_read::cpu.inst 12096 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 5504 # Number of bytes read from this memory
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system.physmem.bytes_read::total 17600 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 12096 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 12096 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 189 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 86 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 275 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1724305061 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 784604419 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2508909480 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1724305061 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1724305061 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1724305061 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 784604419 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2508909480 # Total bandwidth to/from this memory (bytes/s)
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2011-07-10 19:56:09 +02:00
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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2012-02-13 19:30:30 +01:00
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system.cpu.dtb.read_hits 711 # DTB read hits
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system.cpu.dtb.read_misses 43 # DTB read misses
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2011-07-10 19:56:09 +02:00
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system.cpu.dtb.read_acv 1 # DTB read access violations
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2012-02-13 19:30:30 +01:00
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system.cpu.dtb.read_accesses 754 # DTB read accesses
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system.cpu.dtb.write_hits 380 # DTB write hits
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system.cpu.dtb.write_misses 23 # DTB write misses
|
2011-07-10 19:56:09 +02:00
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system.cpu.dtb.write_acv 0 # DTB write access violations
|
2012-02-13 19:30:30 +01:00
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system.cpu.dtb.write_accesses 403 # DTB write accesses
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system.cpu.dtb.data_hits 1091 # DTB hits
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system.cpu.dtb.data_misses 66 # DTB misses
|
2011-07-10 19:56:09 +02:00
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system.cpu.dtb.data_acv 1 # DTB access violations
|
2012-02-13 19:30:30 +01:00
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system.cpu.dtb.data_accesses 1157 # DTB accesses
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system.cpu.itb.fetch_hits 1067 # ITB hits
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system.cpu.itb.fetch_misses 33 # ITB misses
|
2011-07-10 19:56:09 +02:00
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system.cpu.itb.fetch_acv 0 # ITB acv
|
2012-02-13 19:30:30 +01:00
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system.cpu.itb.fetch_accesses 1100 # ITB accesses
|
2011-07-10 19:56:09 +02:00
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4 # Number of system calls
|
2012-02-13 19:30:30 +01:00
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system.cpu.numCycles 14031 # number of cpu cycles simulated
|
2011-07-10 19:56:09 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2012-02-13 19:30:30 +01:00
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system.cpu.BPredUnit.lookups 1201 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2012-02-13 19:30:30 +01:00
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system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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2012-02-13 19:30:30 +01:00
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system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total)
|
2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2012-02-13 19:30:30 +01:00
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system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total)
|
2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2012-02-13 19:30:30 +01:00
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system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 1197 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking
|
2011-07-10 19:56:09 +02:00
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system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst
|
2012-02-13 19:30:30 +01:00
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system.cpu.rename.RunCycles 1115 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups
|
2011-07-10 19:56:09 +02:00
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system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
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2012-02-13 19:30:30 +01:00
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system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
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2012-02-13 19:30:30 +01:00
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system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
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system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle
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|
system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle
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|
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system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle
|
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|
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system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
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system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available
|
|
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|
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available
|
|
|
|
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available
|
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system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available
|
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|
|
system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.FU_type_0::total 4206 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 0.299765 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 43 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.exec_nop 368 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 1160 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 681 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 403 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 0.285439 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 3813 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 1793 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 2339 # num instructions consuming a value
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.commit.committedInsts 2576 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 709 # Number of memory references committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.loads 415 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.branches 396 # Number of branches committed
|
|
|
|
|
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
|
|
|
|
|
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
|
|
|
|
|
system.cpu.commit.function_calls 71 # Number of function calls committed.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.rob.rob_reads 11567 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 11753 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 4832 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 2958 # number of integer regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
|
|
|
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 817 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 817 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 250 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.234302 # miss rate for ReadReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_miss_rate::total 0.234302 # miss rate for demand accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_miss_rate::total 0.234302 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 35830 # average ReadReq miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 35830 # average overall miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 35830 # average overall miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 189 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6695500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 6695500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6695500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 6695500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177132 # mshr miss rate for ReadReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.177132 # mshr miss rate for demand accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.177132 # mshr miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926 # average ReadReq mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 793 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_hits::cpu.data 793 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 793 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 793 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 793 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 107 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 107 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_misses::cpu.data 179 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 179 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 179 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 179 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3676500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3676500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.157817 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.184156 # miss rate for demand accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.184156 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084 # average ReadReq miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111 # average WriteReq miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 36270.949721 # average overall miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 36270.949721 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 86 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 86 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2205000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2205000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 873500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 873500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3078500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 3078500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.091445 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.088477 # mshr miss rate for demand accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.088477 # mshr miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129 # average ReadReq mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333 # average WriteReq mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 29.106633 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.002857 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000888 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.003746 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 189 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 62 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 251 # number of ReadReq misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 189 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 86 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 275 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 189 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 86 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 275 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6484000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2135500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 8619500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 832000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 832000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 6484000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 2967500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 9451500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 6484000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 2967500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 9451500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 189 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 62 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450 # average ReadReq miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667 # average ReadExReq miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909 # average overall miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359 # average ReadReq mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000 # average ReadExReq mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency
|
2012-02-13 19:30:30 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-09-01 23:59:36 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
