2006-09-01 23:59:36 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2008-08-04 00:13:29 +02:00
|
|
|
global.BPredUnit.BTBHits 198 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 684 # Number of BTB lookups
|
|
|
|
|
global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
|
2008-02-26 08:20:40 +01:00
|
|
|
global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect
|
2008-08-04 00:13:29 +02:00
|
|
|
global.BPredUnit.condPredicted 447 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 859 # Number of BP lookups
|
|
|
|
|
global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target.
|
2009-02-16 18:09:45 +01:00
|
|
|
host_inst_rate 22600 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 199684 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 0.11 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 67889683 # Simulator tick rate (ticks/s)
|
2007-08-27 05:27:53 +02:00
|
|
|
memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
|
2007-04-22 20:50:37 +02:00
|
|
|
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
|
2008-08-04 00:13:29 +02:00
|
|
|
memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit.
|
2006-09-01 23:59:36 +02:00
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
|
|
|
sim_insts 2387 # Number of instructions simulated
|
2008-08-04 00:13:29 +02:00
|
|
|
sim_seconds 0.000007 # Number of seconds simulated
|
|
|
|
|
sim_ticks 7183000 # Number of ticks simulated
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:branches 396 # Number of branches committed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 6196
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2008-08-04 00:13:29 +02:00
|
|
|
0 5239 8455.46%
|
|
|
|
|
1 263 424.47%
|
|
|
|
|
2 334 539.06%
|
|
|
|
|
3 134 216.27%
|
|
|
|
|
4 73 117.82%
|
|
|
|
|
5 63 101.68%
|
|
|
|
|
6 32 51.65%
|
|
|
|
|
7 20 32.28%
|
|
|
|
|
8 38 61.33%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.commit.COM:count 2576 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 415 # Number of loads committed
|
|
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.COM:refs 709 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
|
2008-02-28 00:17:37 +01:00
|
|
|
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles
|
2008-02-28 00:17:37 +01:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.overall_hits 674 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_misses 193 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 715 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.accesses 971 # DTB accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.acv 1 # DTB access violations
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.hits 946 # DTB hits
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.dtb.misses 25 # DTB misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.read_accesses 611 # DTB read accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.read_acv 1 # DTB read access violations
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.read_hits 600 # DTB read hits
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.dtb.read_misses 11 # DTB read misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.write_accesses 360 # DTB write accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.dtb.write_hits 346 # DTB write hits
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.dtb.write_misses 14 # DTB write misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.fetch.Branches 859 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 747 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 6528
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2008-08-04 00:13:29 +02:00
|
|
|
0 5595 8570.77%
|
|
|
|
|
1 36 55.15%
|
|
|
|
|
2 100 153.19%
|
|
|
|
|
3 69 105.70%
|
|
|
|
|
4 130 199.14%
|
|
|
|
|
5 72 110.29%
|
|
|
|
|
6 45 68.93%
|
|
|
|
|
7 48 73.53%
|
|
|
|
|
8 433 663.30%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 512 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 235 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.overall_hits 512 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 235 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 512 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 584 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 286 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 360 # Number of stores executed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.WB:consumers 1896 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 3311 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.WB:producers 1509 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2007-06-12 16:56:53 +02:00
|
|
|
No_OpClass 0 0.00% # Type of FU issued
|
2008-08-04 00:13:29 +02:00
|
|
|
IntAlu 2506 71.31% # Type of FU issued
|
2006-11-06 02:42:05 +01:00
|
|
|
IntMult 1 0.03% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2008-08-04 00:13:29 +02:00
|
|
|
MemRead 639 18.18% # Type of FU issued
|
|
|
|
|
MemWrite 368 10.47% # Type of FU issued
|
2006-11-06 02:42:05 +01:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst)
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
2007-06-12 16:56:53 +02:00
|
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
2008-08-04 00:13:29 +02:00
|
|
|
IntAlu 1 2.94% # attempts to use FU when none available
|
2006-09-01 23:59:36 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2008-08-04 00:13:29 +02:00
|
|
|
MemRead 11 32.35% # attempts to use FU when none available
|
|
|
|
|
MemWrite 22 64.71% # attempts to use FU when none available
|
2006-09-01 23:59:36 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 6528
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2008-08-04 00:13:29 +02:00
|
|
|
0 5051 7737.44%
|
|
|
|
|
1 569 871.63%
|
|
|
|
|
2 331 507.05%
|
|
|
|
|
3 253 387.56%
|
|
|
|
|
4 172 263.48%
|
|
|
|
|
5 97 148.59%
|
|
|
|
|
6 39 59.74%
|
|
|
|
|
7 11 16.85%
|
|
|
|
|
8 5 7.66%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.itb.accesses 776 # ITB accesses
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.itb.acv 0 # ITB acv
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.itb.hits 747 # ITB hits
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.itb.misses 29 # ITB misses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
2007-08-13 01:43:55 +02:00
|
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.overall_misses 266 # number of overall misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.numCycles 14367 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle
|
2007-08-27 05:27:53 +02:00
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer
|
2007-08-04 00:04:30 +02:00
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
