2006-09-01 23:59:36 +02:00
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|
---------- Begin Simulation Statistics ----------
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|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-03-30 22:59:40 +02:00
|
|
|
global.BPredUnit.BTBHits 187 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 653 # Number of BTB lookups
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|
|
|
|
global.BPredUnit.RASInCorrect 41 # Number of incorrect RAS predictions.
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|
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|
|
global.BPredUnit.condIncorrect 217 # Number of conditional branches incorrect
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|
global.BPredUnit.condPredicted 426 # Number of conditional branches predicted
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|
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|
global.BPredUnit.lookups 832 # Number of BP lookups
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|
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|
|
global.BPredUnit.usedRAS 170 # Number of times the RAS was used to get a target.
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|
|
host_inst_rate 19984 # Simulator instruction rate (inst/s)
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|
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|
host_mem_usage 153584 # Number of bytes of host memory used
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|
host_seconds 0.12 # Real time elapsed on the host
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|
host_tick_rate 6228839 # Simulator tick rate (ticks/s)
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|
memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
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2006-10-14 00:59:29 +02:00
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|
memdepunit.memDep.conflictingStores 8 # Number of conflicting stores.
|
2007-03-30 22:59:40 +02:00
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|
|
memdepunit.memDep.insertedLoads 701 # Number of loads inserted to the mem dependence unit.
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|
memdepunit.memDep.insertedStores 382 # Number of stores inserted to the mem dependence unit.
|
2006-09-01 23:59:36 +02:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
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|
sim_insts 2387 # Number of instructions simulated
|
2006-10-14 00:59:29 +02:00
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|
|
sim_seconds 0.000001 # Number of seconds simulated
|
2007-03-30 22:59:40 +02:00
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|
|
sim_ticks 746028 # Number of ticks simulated
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.commit.COM:branches 396 # Number of branches committed
|
2007-03-30 22:59:40 +02:00
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|
|
system.cpu.commit.COM:bw_lim_events 52 # number cycles where commit BW limit reached
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2006-09-01 23:59:36 +02:00
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|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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2007-03-30 22:59:40 +02:00
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|
system.cpu.commit.COM:committed_per_cycle.samples 29809
|
2006-09-01 23:59:36 +02:00
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|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-03-30 22:59:40 +02:00
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0 28885 9690.03%
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|
1 239 80.18%
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2 325 109.03%
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3 129 43.28%
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4 78 26.17%
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5 53 17.78%
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6 29 9.73%
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7 19 6.37%
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8 52 17.44%
|
2006-09-01 23:59:36 +02:00
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|
system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 2576 # Number of instructions committed
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system.cpu.commit.COM:loads 415 # Number of loads committed
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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|
system.cpu.commit.COM:refs 709 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2007-03-30 22:59:40 +02:00
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|
|
system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted
|
2006-09-01 23:59:36 +02:00
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|
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
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|
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
2007-03-30 22:59:40 +02:00
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|
system.cpu.commit.commitSquashedInsts 1536 # The number of squashed insts skipped by commit
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.committedInsts 2387 # Number of Instructions Simulated
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|
|
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
2007-03-30 22:59:40 +02:00
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|
|
system.cpu.cpi 312.537914 # CPI: Cycles Per Instruction
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|
system.cpu.cpi_total 312.537914 # CPI: Total CPI of All Threads
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|
system.cpu.dcache.ReadReq_accesses 565 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 7055.843750 # average ReadReq miss latency
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|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7158.016393 # average ReadReq mshr miss latency
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|
|
|
|
system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits
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|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 677361 # number of ReadReq miss cycles
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|
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|
|
system.cpu.dcache.ReadReq_miss_rate 0.169912 # miss rate for ReadReq accesses
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|
|
|
|
system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses
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|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
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|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 436639 # number of ReadReq MSHR miss cycles
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|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.107965 # mshr miss rate for ReadReq accesses
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2006-09-01 23:59:36 +02:00
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|
|
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
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|
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|
|
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
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2007-03-30 22:59:40 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 7089.086420 # average WriteReq miss latency
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|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6946.208333 # average WriteReq mshr miss latency
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|
system.cpu.dcache.WriteReq_hits 213 # number of WriteReq hits
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|
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|
system.cpu.dcache.WriteReq_miss_latency 574216 # number of WriteReq miss cycles
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|
system.cpu.dcache.WriteReq_miss_rate 0.275510 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses
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|
system.cpu.dcache.WriteReq_mshr_hits 57 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 166709 # number of WriteReq MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
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|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
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|
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|
system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
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|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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2007-03-30 22:59:40 +02:00
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|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 8.023529 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-03-30 22:59:40 +02:00
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|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-03-30 22:59:40 +02:00
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|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-03-30 22:59:40 +02:00
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|
|
system.cpu.dcache.demand_accesses 859 # number of demand (read+write) accesses
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|
|
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|
system.cpu.dcache.demand_avg_miss_latency 7071.056497 # average overall miss latency
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|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency
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|
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|
|
system.cpu.dcache.demand_hits 682 # number of demand (read+write) hits
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|
|
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|
system.cpu.dcache.demand_miss_latency 1251577 # number of demand (read+write) miss cycles
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|
system.cpu.dcache.demand_miss_rate 0.206054 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 177 # number of demand (read+write) misses
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|
system.cpu.dcache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits
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|
system.cpu.dcache.demand_mshr_miss_latency 603348 # number of demand (read+write) MSHR miss cycles
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|
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|
|
system.cpu.dcache.demand_mshr_miss_rate 0.098952 # mshr miss rate for demand accesses
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2006-09-01 23:59:36 +02:00
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|
|
system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
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|
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|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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|
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|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2007-03-30 22:59:40 +02:00
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|
|
system.cpu.dcache.overall_accesses 859 # number of overall (read+write) accesses
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|
system.cpu.dcache.overall_avg_miss_latency 7071.056497 # average overall miss latency
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|
system.cpu.dcache.overall_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
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|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-03-30 22:59:40 +02:00
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|
system.cpu.dcache.overall_hits 682 # number of overall hits
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|
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system.cpu.dcache.overall_miss_latency 1251577 # number of overall miss cycles
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|
system.cpu.dcache.overall_miss_rate 0.206054 # miss rate for overall accesses
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|
system.cpu.dcache.overall_misses 177 # number of overall misses
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|
|
|
|
system.cpu.dcache.overall_mshr_hits 92 # number of overall MSHR hits
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|
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|
system.cpu.dcache.overall_mshr_miss_latency 603348 # number of overall MSHR miss cycles
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|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.098952 # mshr miss rate for overall accesses
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
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|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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|
|
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|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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|
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|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
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|
|
|
|
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
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|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-03-30 22:59:40 +02:00
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|
|
system.cpu.dcache.tagsinuse 46.650284 # Cycle average of tags in use
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|
system.cpu.dcache.total_refs 682 # Total number of references to valid blocks.
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2006-09-01 23:59:36 +02:00
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|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2007-03-30 22:59:40 +02:00
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|
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system.cpu.decode.DECODE:BlockedCycles 23701 # Number of cycles decode is blocked
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
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2007-03-30 22:59:40 +02:00
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|
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system.cpu.decode.DECODE:BranchResolved 129 # Number of times decode resolved a branch
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|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 4617 # Number of instructions handled by decode
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|
system.cpu.decode.DECODE:IdleCycles 5228 # Number of cycles decode is idle
|
|
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|
system.cpu.decode.DECODE:RunCycles 877 # Number of cycles decode is running
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|
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|
system.cpu.decode.DECODE:SquashCycles 297 # Number of cycles decode is squashing
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
|
2007-03-30 22:59:40 +02:00
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|
|
system.cpu.decode.DECODE:UnblockCycles 4 # Number of cycles decode is unblocking
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|
|
|
|
system.cpu.fetch.Branches 832 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 760 # Number of cache lines fetched
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|
|
|
|
system.cpu.fetch.Cycles 1674 # Number of cycles fetch has run and was not squashing or blocked
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|
|
|
|
system.cpu.fetch.IcacheSquashes 131 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 5310 # Number of instructions fetch has processed
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|
|
|
|
system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing
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|
|
|
|
system.cpu.fetch.branchRate 0.027635 # Number of branch fetches per cycle
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|
|
|
|
system.cpu.fetch.icacheStallCycles 760 # Number of cycles fetch is stalled on an Icache miss
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|
|
|
|
system.cpu.fetch.predictedBranches 357 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.176371 # Number of inst fetches per cycle
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 30107
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-03-30 22:59:40 +02:00
|
|
|
0 29196 9697.41%
|
|
|
|
|
1 37 12.29%
|
|
|
|
|
2 87 28.90%
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|
|
|
|
3 73 24.25%
|
|
|
|
|
4 125 41.52%
|
|
|
|
|
5 66 21.92%
|
|
|
|
|
6 42 13.95%
|
|
|
|
|
7 50 16.61%
|
|
|
|
|
8 431 143.16%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 760 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 4979.783333 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4157.255435 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 520 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 1195148 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.315789 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 240 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 764935 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.242105 # mshr miss rate for ReadReq accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 2.826087 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.demand_accesses 760 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 4979.783333 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 520 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 1195148 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.315789 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 240 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 764935 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.242105 # mshr miss rate for demand accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.overall_accesses 760 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 4979.783333 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.overall_hits 520 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 1195148 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.315789 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 240 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 764935 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.242105 # mshr miss rate for overall accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.icache.tagsinuse 91.559894 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 520 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.idleCycles 715922 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 547 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 269 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.108081 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 940 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 340 # Number of stores executed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.WB:consumers 1841 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 3178 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.788702 # average fanout of values written-back
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.WB:producers 1452 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.105557 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 3194 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 16588 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 701 # Number of dispatched load instructions
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 62 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 382 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 4113 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 600 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 110 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 3254 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 297 # Number of cycles IEW is squashing
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 286 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 88 # Number of stores squashed
|
2007-03-25 07:05:48 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 96 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.003200 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.003200 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 3364 # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2006-11-06 02:42:05 +01:00
|
|
|
(null) 0 0.00% # Type of FU issued
|
2007-03-30 22:59:40 +02:00
|
|
|
IntAlu 2398 71.28% # Type of FU issued
|
2006-11-06 02:42:05 +01:00
|
|
|
IntMult 1 0.03% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
2007-03-30 22:59:40 +02:00
|
|
|
MemRead 618 18.37% # Type of FU issued
|
|
|
|
|
MemWrite 347 10.32% # Type of FU issued
|
2006-11-06 02:42:05 +01:00
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2006-11-12 17:07:34 +01:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.010107 # FU busy rate (busy events/executed inst)
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
2006-11-12 17:07:34 +01:00
|
|
|
IntAlu 1 2.94% # attempts to use FU when none available
|
2006-09-01 23:59:36 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2006-11-12 17:07:34 +01:00
|
|
|
MemRead 11 32.35% # attempts to use FU when none available
|
|
|
|
|
MemWrite 22 64.71% # attempts to use FU when none available
|
2006-09-01 23:59:36 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 30107
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-03-30 22:59:40 +02:00
|
|
|
0 28628 9508.75%
|
|
|
|
|
1 616 204.60%
|
|
|
|
|
2 335 111.27%
|
|
|
|
|
3 225 74.73%
|
|
|
|
|
4 177 58.79%
|
|
|
|
|
5 80 26.57%
|
|
|
|
|
6 31 10.30%
|
|
|
|
|
7 11 3.65%
|
|
|
|
|
8 4 1.33%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 0.111735 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 3838 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 3364 # Number of instructions issued
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 1301 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 682 # Number of squashed operands that are examined and possibly removed from graph
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses)
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4610.717472 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2315.289963 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1240283 # number of ReadReq miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 622813 # number of ReadReq MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4610.717472 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 1240283 # number of demand (read+write) miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 622813 # number of demand (read+write) MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4610.717472 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 1240283 # number of overall miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.overall_misses 269 # number of overall misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 622813 # number of overall MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 138.742329 # Cycle average of tags in use
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.numCycles 30107 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 16613 # Number of cycles rename is blocking
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 14 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 5311 # Number of cycles rename is idle
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.rename.RENAME:RenameLookups 5020 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 4436 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 3192 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 802 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 297 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 23 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 1424 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 7061 # count of cycles rename stalled for serializing inst
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
2007-03-30 22:59:40 +02:00
|
|
|
system.cpu.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
