Add o3-timing configuration for ALPHA_SE "Hello world" tests.
build_opts/ALPHA_SE:
Add O3CPU to default CPU model list.
tests/SConscript:
Add o3-timing configuration.
--HG--
extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
This commit is contained in:
Steve Reinhardt
parent
e9ab841497
commit
2c9dc949ce
13 changed files with 5651 additions and 1 deletions
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@ -1,2 +1,3 @@
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
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@ -207,7 +207,7 @@ if env['FULL_SYSTEM']:
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'tsunami-simple-atomic-dual',
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'tsunami-simple-timing-dual']
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else:
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configs += ['simple-atomic', 'simple-timing']
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configs += ['simple-atomic', 'simple-timing', 'o3-timing']
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cwd = os.getcwd()
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os.chdir(str(Dir('.').srcdir))
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52
tests/configs/o3-timing.py
Normal file
52
tests/configs/o3-timing.py
Normal file
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@ -0,0 +1,52 @@
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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import m5
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from m5.objects import *
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m5.AddToPath('../configs/common')
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from FullO3Config import *
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class MyCache(BaseCache):
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assoc = 2
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block_size = 64
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latency = 1
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mshrs = 10
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tgts_per_mshr = 5
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cpu = DetailedO3CPU()
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cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
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MyCache(size = '2MB'))
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cpu.mem = cpu.dcache
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system = System(cpu = cpu,
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physmem = PhysicalMemory(),
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membus = Bus())
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system.physmem.port = system.membus.port
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cpu.connectMemPorts(system.membus)
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root = Root(system = system)
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406
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
Normal file
406
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
Normal file
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@ -0,0 +1,406 @@
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[root]
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type=Root
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children=system
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checkpoint=
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clock=1000000000000
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max_tick=0
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output_file=cout
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progress_interval=0
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[debug]
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break_cycles=
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[exetrace]
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intel_format=false
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pc_symbol=true
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print_cpseq=false
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print_cycle=true
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print_data=true
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print_effaddr=true
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print_fetchseq=false
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print_iregs=false
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print_opclass=true
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print_thread=true
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speculative=true
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trace_system=client
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[serialize]
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count=10
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cycle=0
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dir=cpt.%012d
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period=0
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[stats]
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descriptions=true
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dump_cycle=0
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dump_period=0
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dump_reset=false
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ignore_events=
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mysql_db=
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mysql_host=
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mysql_password=
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mysql_user=
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project_name=test
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simulation_name=test
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simulation_sample=0
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text_compat=true
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text_file=m5stats.txt
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=DerivO3CPU
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children=dcache fuPool icache l2cache toL2Bus workload
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BTBEntries=4096
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BTBTagSize=16
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LFSTSize=1024
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LQEntries=32
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RASSize=16
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SQEntries=32
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SSITSize=1024
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activity=0
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backComSize=5
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choiceCtrBits=2
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choicePredictorSize=8192
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clock=1
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commitToDecodeDelay=1
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commitToFetchDelay=1
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commitToIEWDelay=1
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commitToRenameDelay=1
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commitWidth=8
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decodeToFetchDelay=1
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decodeToRenameDelay=1
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decodeWidth=8
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defer_registration=false
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dispatchWidth=8
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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forwardComSize=5
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fuPool=system.cpu.fuPool
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function_trace=false
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function_trace_start=0
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globalCtrBits=2
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globalHistoryBits=13
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globalPredictorSize=8192
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iewToCommitDelay=1
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iewToDecodeDelay=1
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iewToFetchDelay=1
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iewToRenameDelay=1
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instShiftAmt=2
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issueToExecuteDelay=1
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issueWidth=8
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localCtrBits=2
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localHistoryBits=11
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localHistoryTableSize=2048
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localPredictorSize=2048
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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mem=system.cpu.dcache
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numIQEntries=64
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numPhysFloatRegs=256
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numPhysIntRegs=256
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numROBEntries=192
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numRobs=1
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numThreads=1
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predType=tournament
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renameToDecodeDelay=1
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renameToFetchDelay=1
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renameToIEWDelay=2
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renameToROBDelay=1
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renameWidth=8
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squashWidth=8
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system=system
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=system.cpu.workload
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[system.cpu.dcache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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do_copy=false
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=262144
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
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[system.cpu.fuPool.FUList0]
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type=FUDesc
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children=opList0
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count=6
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opList=system.cpu.fuPool.FUList0.opList0
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[system.cpu.fuPool.FUList0.opList0]
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type=OpDesc
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issueLat=1
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opClass=IntAlu
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opLat=1
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[system.cpu.fuPool.FUList1]
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type=FUDesc
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children=opList0 opList1
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count=2
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opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
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[system.cpu.fuPool.FUList1.opList0]
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type=OpDesc
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issueLat=1
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opClass=IntMult
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opLat=3
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[system.cpu.fuPool.FUList1.opList1]
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type=OpDesc
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issueLat=19
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opClass=IntDiv
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opLat=20
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[system.cpu.fuPool.FUList2]
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type=FUDesc
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children=opList0 opList1 opList2
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count=4
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opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
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[system.cpu.fuPool.FUList2.opList0]
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type=OpDesc
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issueLat=1
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opClass=FloatAdd
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opLat=2
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[system.cpu.fuPool.FUList2.opList1]
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type=OpDesc
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issueLat=1
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opClass=FloatCmp
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opLat=2
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[system.cpu.fuPool.FUList2.opList2]
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type=OpDesc
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issueLat=1
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opClass=FloatCvt
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opLat=2
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[system.cpu.fuPool.FUList3]
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type=FUDesc
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children=opList0 opList1 opList2
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count=2
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opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
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[system.cpu.fuPool.FUList3.opList0]
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type=OpDesc
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issueLat=1
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opClass=FloatMult
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opLat=4
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[system.cpu.fuPool.FUList3.opList1]
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type=OpDesc
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issueLat=12
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opClass=FloatDiv
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opLat=12
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[system.cpu.fuPool.FUList3.opList2]
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type=OpDesc
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issueLat=24
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opClass=FloatSqrt
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opLat=24
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[system.cpu.fuPool.FUList4]
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type=FUDesc
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children=opList0
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count=0
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opList=system.cpu.fuPool.FUList4.opList0
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[system.cpu.fuPool.FUList4.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu.fuPool.FUList5]
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type=FUDesc
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children=opList0
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count=0
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opList=system.cpu.fuPool.FUList5.opList0
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[system.cpu.fuPool.FUList5.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemWrite
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opLat=1
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[system.cpu.fuPool.FUList6]
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type=FUDesc
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children=opList0 opList1
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count=4
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opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
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[system.cpu.fuPool.FUList6.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu.fuPool.FUList6.opList1]
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type=OpDesc
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issueLat=1
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opClass=MemWrite
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opLat=1
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[system.cpu.fuPool.FUList7]
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type=FUDesc
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children=opList0
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count=1
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opList=system.cpu.fuPool.FUList7.opList0
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[system.cpu.fuPool.FUList7.opList0]
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type=OpDesc
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issueLat=3
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opClass=IprAccess
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opLat=3
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[system.cpu.icache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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do_copy=false
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hash_delay=1
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hit_latency=1
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latency=1
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lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=131072
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=5
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trace_addr=0
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two_queue=false
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write_buffers=8
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[system.cpu.l2cache]
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type=BaseCache
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adaptive_compression=false
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assoc=2
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block_size=64
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compressed_bus=false
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compression_latency=0
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do_copy=false
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hash_delay=1
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hit_latency=1
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latency=1
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||||
lifo=false
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max_miss_count=0
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mshrs=10
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prefetch_access=false
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prefetch_cache_check_push=true
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||||
prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10
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prefetch_miss=false
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prefetch_past_page=false
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||||
prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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||||
protocol=Null
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||||
repl=Null
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||||
size=2097152
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||||
split=false
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||||
split_size=0
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||||
store_compressed=false
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||||
subblock_size=0
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||||
tgts_per_mshr=5
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||||
trace_addr=0
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||||
two_queue=false
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||||
write_buffers=8
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[system.cpu.toL2Bus]
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type=Bus
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||||
bus_id=0
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||||
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[system.cpu.workload]
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type=LiveProcess
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||||
cmd=hello
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env=
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executable=tests/test-progs/hello/bin/alpha/linux/hello
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input=cin
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output=cout
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system=system
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||||
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||||
[system.membus]
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type=Bus
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||||
bus_id=0
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||||
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[system.physmem]
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type=PhysicalMemory
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||||
file=
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latency=1
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||||
range=0:134217727
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[trace]
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bufsize=0
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||||
dump_on_exit=false
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file=cout
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flags=
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||||
ignore=
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start=0
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403
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
Normal file
403
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
Normal file
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@ -0,0 +1,403 @@
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[root]
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type=Root
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clock=1000000000000
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max_tick=0
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progress_interval=0
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output_file=cout
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[system.physmem]
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type=PhysicalMemory
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file=
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range=[0,134217727]
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latency=1
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||||
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[system]
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||||
type=System
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||||
physmem=system.physmem
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mem_mode=atomic
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||||
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||||
[system.membus]
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||||
type=Bus
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||||
bus_id=0
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||||
|
||||
[system.cpu.workload]
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||||
type=LiveProcess
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||||
cmd=hello
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||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
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||||
input=cin
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||||
output=cout
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||||
env=
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||||
system=system
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||||
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||||
[system.cpu.dcache]
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||||
type=BaseCache
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||||
size=262144
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assoc=2
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||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
1974
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
Normal file
1974
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
Normal file
File diff suppressed because it is too large
Load diff
3
tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
Normal file
3
tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
|
||||
13
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
Normal file
13
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 1 2006 16:10:44
|
||||
M5 started Fri Sep 1 16:23:41 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
406
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
Normal file
406
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
Normal file
|
|
@ -0,0 +1,406 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
checkpoint=
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
dir=cpt.%012d
|
||||
period=0
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
dump_reset=false
|
||||
ignore_events=
|
||||
mysql_db=
|
||||
mysql_host=
|
||||
mysql_password=
|
||||
mysql_user=
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_compat=true
|
||||
text_file=m5stats.txt
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
children=dcache fuPool icache l2cache toL2Bus workload
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
LFSTSize=1024
|
||||
LQEntries=32
|
||||
RASSize=16
|
||||
SQEntries=32
|
||||
SSITSize=1024
|
||||
activity=0
|
||||
backComSize=5
|
||||
choiceCtrBits=2
|
||||
choicePredictorSize=8192
|
||||
clock=1
|
||||
commitToDecodeDelay=1
|
||||
commitToFetchDelay=1
|
||||
commitToIEWDelay=1
|
||||
commitToRenameDelay=1
|
||||
commitWidth=8
|
||||
decodeToFetchDelay=1
|
||||
decodeToRenameDelay=1
|
||||
decodeWidth=8
|
||||
defer_registration=false
|
||||
dispatchWidth=8
|
||||
fetchToDecodeDelay=1
|
||||
fetchTrapLatency=1
|
||||
fetchWidth=8
|
||||
forwardComSize=5
|
||||
fuPool=system.cpu.fuPool
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
globalPredictorSize=8192
|
||||
iewToCommitDelay=1
|
||||
iewToDecodeDelay=1
|
||||
iewToFetchDelay=1
|
||||
iewToRenameDelay=1
|
||||
instShiftAmt=2
|
||||
issueToExecuteDelay=1
|
||||
issueWidth=8
|
||||
localCtrBits=2
|
||||
localHistoryBits=11
|
||||
localHistoryTableSize=2048
|
||||
localPredictorSize=2048
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
mem=system.cpu.dcache
|
||||
numIQEntries=64
|
||||
numPhysFloatRegs=256
|
||||
numPhysIntRegs=256
|
||||
numROBEntries=192
|
||||
numRobs=1
|
||||
numThreads=1
|
||||
predType=tournament
|
||||
renameToDecodeDelay=1
|
||||
renameToFetchDelay=1
|
||||
renameToIEWDelay=2
|
||||
renameToROBDelay=1
|
||||
renameWidth=8
|
||||
squashWidth=8
|
||||
system=system
|
||||
trapLatency=13
|
||||
wbDepth=1
|
||||
wbWidth=8
|
||||
workload=system.cpu.workload
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=262144
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=6
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
issueLat=19
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
children=opList0 opList1 opList2
|
||||
count=2
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
issueLat=12
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
issueLat=24
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=0
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
children=opList0 opList1
|
||||
count=4
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
issueLat=1
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
children=opList0
|
||||
count=1
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
issueLat=3
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=131072
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
adaptive_compression=false
|
||||
assoc=2
|
||||
block_size=64
|
||||
compressed_bus=false
|
||||
compression_latency=0
|
||||
do_copy=false
|
||||
hash_delay=1
|
||||
hit_latency=1
|
||||
latency=1
|
||||
lifo=false
|
||||
max_miss_count=0
|
||||
mshrs=10
|
||||
prefetch_access=false
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_data_accesses_only=false
|
||||
prefetch_degree=1
|
||||
prefetch_latency=10
|
||||
prefetch_miss=false
|
||||
prefetch_past_page=false
|
||||
prefetch_policy=none
|
||||
prefetch_serial_squash=false
|
||||
prefetch_use_cpu_id=true
|
||||
prefetcher_size=100
|
||||
prioritizeRequests=false
|
||||
protocol=Null
|
||||
repl=Null
|
||||
size=2097152
|
||||
split=false
|
||||
split_size=0
|
||||
store_compressed=false
|
||||
subblock_size=0
|
||||
tgts_per_mshr=5
|
||||
trace_addr=0
|
||||
two_queue=false
|
||||
write_buffers=8
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
env=
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
input=cin
|
||||
output=cout
|
||||
system=system
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
403
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
Normal file
403
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
Normal file
|
|
@ -0,0 +1,403 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=1000000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
|
||||
[system]
|
||||
type=System
|
||||
physmem=system.physmem
|
||||
mem_mode=atomic
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
system=system
|
||||
|
||||
[system.cpu.dcache]
|
||||
type=BaseCache
|
||||
size=262144
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.fuPool.FUList0.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntAlu
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList0]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList0.opList0
|
||||
count=6
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList0]
|
||||
type=OpDesc
|
||||
opClass=IntMult
|
||||
opLat=3
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList1.opList1]
|
||||
type=OpDesc
|
||||
opClass=IntDiv
|
||||
opLat=20
|
||||
issueLat=19
|
||||
|
||||
[system.cpu.fuPool.FUList1]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatAdd
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatCmp
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatCvt
|
||||
opLat=2
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList2]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList0]
|
||||
type=OpDesc
|
||||
opClass=FloatMult
|
||||
opLat=4
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList1]
|
||||
type=OpDesc
|
||||
opClass=FloatDiv
|
||||
opLat=12
|
||||
issueLat=12
|
||||
|
||||
[system.cpu.fuPool.FUList3.opList2]
|
||||
type=OpDesc
|
||||
opClass=FloatSqrt
|
||||
opLat=24
|
||||
issueLat=24
|
||||
|
||||
[system.cpu.fuPool.FUList3]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
|
||||
count=2
|
||||
|
||||
[system.cpu.fuPool.FUList4.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList4]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList4.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList5.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList5]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList5.opList0
|
||||
count=0
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList0]
|
||||
type=OpDesc
|
||||
opClass=MemRead
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6.opList1]
|
||||
type=OpDesc
|
||||
opClass=MemWrite
|
||||
opLat=1
|
||||
issueLat=1
|
||||
|
||||
[system.cpu.fuPool.FUList6]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
|
||||
count=4
|
||||
|
||||
[system.cpu.fuPool.FUList7.opList0]
|
||||
type=OpDesc
|
||||
opClass=IprAccess
|
||||
opLat=3
|
||||
issueLat=3
|
||||
|
||||
[system.cpu.fuPool.FUList7]
|
||||
type=FUDesc
|
||||
opList=system.cpu.fuPool.FUList7.opList0
|
||||
count=1
|
||||
|
||||
[system.cpu.fuPool]
|
||||
type=FUPool
|
||||
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
|
||||
|
||||
[system.cpu]
|
||||
type=DerivO3CPU
|
||||
clock=1
|
||||
numThreads=1
|
||||
activity=0
|
||||
workload=system.cpu.workload
|
||||
mem=system.cpu.dcache
|
||||
checker=null
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
cachePorts=200
|
||||
decodeToFetchDelay=1
|
||||
renameToFetchDelay=1
|
||||
iewToFetchDelay=1
|
||||
commitToFetchDelay=1
|
||||
fetchWidth=8
|
||||
renameToDecodeDelay=1
|
||||
iewToDecodeDelay=1
|
||||
commitToDecodeDelay=1
|
||||
fetchToDecodeDelay=1
|
||||
decodeWidth=8
|
||||
iewToRenameDelay=1
|
||||
commitToRenameDelay=1
|
||||
decodeToRenameDelay=1
|
||||
renameWidth=8
|
||||
commitToIEWDelay=1
|
||||
renameToIEWDelay=2
|
||||
issueToExecuteDelay=1
|
||||
dispatchWidth=8
|
||||
issueWidth=8
|
||||
wbWidth=8
|
||||
wbDepth=1
|
||||
fuPool=system.cpu.fuPool
|
||||
iewToCommitDelay=1
|
||||
renameToROBDelay=1
|
||||
commitWidth=8
|
||||
squashWidth=8
|
||||
trapLatency=13
|
||||
backComSize=5
|
||||
forwardComSize=5
|
||||
predType=tournament
|
||||
localPredictorSize=2048
|
||||
localCtrBits=2
|
||||
localHistoryTableSize=2048
|
||||
localHistoryBits=11
|
||||
globalPredictorSize=8192
|
||||
globalCtrBits=2
|
||||
globalHistoryBits=13
|
||||
choicePredictorSize=8192
|
||||
choiceCtrBits=2
|
||||
BTBEntries=4096
|
||||
BTBTagSize=16
|
||||
RASSize=16
|
||||
LQEntries=32
|
||||
SQEntries=32
|
||||
LFSTSize=1024
|
||||
SSITSize=1024
|
||||
numPhysIntRegs=256
|
||||
numPhysFloatRegs=256
|
||||
numIQEntries=64
|
||||
numROBEntries=192
|
||||
smtNumFetchingThreads=1
|
||||
smtFetchPolicy=SingleThread
|
||||
smtLSQPolicy=Partitioned
|
||||
smtLSQThreshold=100
|
||||
smtIQPolicy=Partitioned
|
||||
smtIQThreshold=100
|
||||
smtROBPolicy=Partitioned
|
||||
smtROBThreshold=100
|
||||
smtCommitPolicy=RoundRobin
|
||||
instShiftAmt=2
|
||||
defer_registration=false
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
|
||||
[system.cpu.icache]
|
||||
type=BaseCache
|
||||
size=131072
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.l2cache]
|
||||
type=BaseCache
|
||||
size=2097152
|
||||
assoc=2
|
||||
block_size=64
|
||||
latency=1
|
||||
mshrs=10
|
||||
tgts_per_mshr=5
|
||||
write_buffers=8
|
||||
prioritizeRequests=false
|
||||
do_copy=false
|
||||
protocol=null
|
||||
trace_addr=0
|
||||
hash_delay=1
|
||||
repl=null
|
||||
compressed_bus=false
|
||||
store_compressed=false
|
||||
adaptive_compression=false
|
||||
compression_latency=0
|
||||
block_size=64
|
||||
max_miss_count=0
|
||||
addr_range=[0,18446744073709551615]
|
||||
split=false
|
||||
split_size=0
|
||||
lifo=false
|
||||
two_queue=false
|
||||
prefetch_miss=false
|
||||
prefetch_access=false
|
||||
prefetcher_size=100
|
||||
prefetch_past_page=false
|
||||
prefetch_serial_squash=false
|
||||
prefetch_latency=10
|
||||
prefetch_degree=1
|
||||
prefetch_policy=none
|
||||
prefetch_cache_check_push=true
|
||||
prefetch_use_cpu_id=true
|
||||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[system.cpu.toL2Bus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
simulation_name=test
|
||||
simulation_sample=0
|
||||
text_file=m5stats.txt
|
||||
text_compat=true
|
||||
mysql_db=
|
||||
mysql_user=
|
||||
mysql_password=
|
||||
mysql_host=
|
||||
events_start=-1
|
||||
dump_reset=false
|
||||
dump_cycle=0
|
||||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
trace_system=client
|
||||
|
||||
[debug]
|
||||
break_cycles=
|
||||
|
||||
1972
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
Normal file
1972
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
Normal file
File diff suppressed because it is too large
Load diff
4
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
Normal file
4
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
|
||||
warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
13
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
Normal file
13
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
Hello world!
|
||||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 1 2006 16:10:44
|
||||
M5 started Fri Sep 1 16:23:45 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
|
||||
Exiting @ tick 2886 because target called exit()
|
||||
Loading…
Reference in a new issue