2006-09-01 23:59:36 +02:00
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|
|
|
|
|
---------- Begin Simulation Statistics ----------
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|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2006-10-14 00:59:29 +02:00
|
|
|
global.BPredUnit.BTBHits 200 # Number of BTB hits
|
2006-09-01 23:59:36 +02:00
|
|
|
global.BPredUnit.BTBLookups 711 # Number of BTB lookups
|
2006-10-14 00:59:29 +02:00
|
|
|
global.BPredUnit.RASInCorrect 42 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 221 # Number of conditional branches incorrect
|
|
|
|
|
global.BPredUnit.condPredicted 451 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 891 # Number of BP lookups
|
|
|
|
|
global.BPredUnit.usedRAS 172 # Number of times the RAS was used to get a target.
|
2006-11-06 02:42:05 +01:00
|
|
|
host_inst_rate 20134 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 179640 # Number of bytes of host memory used
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|
|
|
|
host_seconds 0.12 # Real time elapsed on the host
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|
|
|
host_tick_rate 6326998 # Simulator tick rate (ticks/s)
|
2006-10-14 00:59:29 +02:00
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|
|
memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads.
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|
|
|
|
memdepunit.memDep.conflictingStores 8 # Number of conflicting stores.
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|
|
|
|
memdepunit.memDep.insertedLoads 784 # Number of loads inserted to the mem dependence unit.
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|
|
|
|
memdepunit.memDep.insertedStores 376 # Number of stores inserted to the mem dependence unit.
|
2006-09-01 23:59:36 +02:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
|
|
|
sim_insts 2387 # Number of instructions simulated
|
2006-10-14 00:59:29 +02:00
|
|
|
sim_seconds 0.000001 # Number of seconds simulated
|
|
|
|
|
sim_ticks 752027 # Number of ticks simulated
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.commit.COM:branches 396 # Number of branches committed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 56 # number cycles where commit BW limit reached
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.commit.COM:committed_per_cycle.samples 28113
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2006-10-14 00:59:29 +02:00
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|
|
0 27203 9676.31%
|
|
|
|
|
1 230 81.81%
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|
|
|
|
2 313 111.34%
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|
|
3 133 47.31%
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|
|
|
4 80 28.46%
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|
|
|
|
5 53 18.85%
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|
|
|
|
6 27 9.60%
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|
|
|
|
7 18 6.40%
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|
|
|
|
8 56 19.92%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
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|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
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|
system.cpu.commit.COM:count 2576 # Number of instructions committed
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|
|
|
|
system.cpu.commit.COM:loads 415 # Number of loads committed
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|
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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|
|
|
|
system.cpu.commit.COM:refs 709 # Number of memory references committed
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|
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.commit.branchMispredicts 144 # The number of times a branch was mispredicted
|
2006-09-01 23:59:36 +02:00
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|
|
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
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|
|
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.commit.commitSquashedInsts 1694 # The number of squashed insts skipped by commit
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.cpi 315.051110 # CPI: Cycles Per Instruction
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|
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|
|
system.cpu.cpi_total 315.051110 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 562 # number of ReadReq accesses(hits+misses)
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|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 7254.010870 # average ReadReq miss latency
|
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|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7288.590164 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 667369 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.163701 # miss rate for ReadReq accesses
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|
|
|
|
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
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|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits
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|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 444604 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.108541 # mshr miss rate for ReadReq accesses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
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|
|
|
|
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.dcache.WriteReq_avg_miss_latency 6647.600000 # average WriteReq miss latency
|
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|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6571.583333 # average WriteReq mshr miss latency
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|
|
|
|
system.cpu.dcache.WriteReq_hits 224 # number of WriteReq hits
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|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 465332 # number of WriteReq miss cycles
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|
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.238095 # miss rate for WriteReq accesses
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|
|
|
|
system.cpu.dcache.WriteReq_misses 70 # number of WriteReq misses
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|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits
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|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 157718 # number of WriteReq MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
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|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
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|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.dcache.avg_blocked_cycles_no_targets 2980.125000 # average number of cycles each access was blocked
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|
|
|
|
system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.blocked_no_targets 8 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 23841 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.demand_accesses 856 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 6991.981481 # average overall miss latency
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|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 694 # number of demand (read+write) hits
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|
|
|
|
system.cpu.dcache.demand_miss_latency 1132701 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.189252 # miss rate for demand accesses
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|
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|
|
system.cpu.dcache.demand_misses 162 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 77 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 602322 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.099299 # mshr miss rate for demand accesses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.overall_accesses 856 # number of overall (read+write) accesses
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|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 6991.981481 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 7086.141176 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
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|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-10-14 00:59:29 +02:00
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|
|
system.cpu.dcache.overall_hits 694 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 1132701 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.189252 # miss rate for overall accesses
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|
|
|
|
system.cpu.dcache.overall_misses 162 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 77 # number of overall MSHR hits
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|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 602322 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.099299 # mshr miss rate for overall accesses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.dcache.tagsinuse 46.684937 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 694 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.decode.DECODE:BlockedCycles 21872 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
|
|
|
|
|
system.cpu.decode.DECODE:BranchResolved 150 # Number of times decode resolved a branch
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 4868 # Number of instructions handled by decode
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|
|
|
|
system.cpu.decode.DECODE:IdleCycles 5315 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 925 # Number of cycles decode is running
|
|
|
|
|
system.cpu.decode.DECODE:SquashCycles 338 # Number of cycles decode is squashing
|
|
|
|
|
system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 891 # Number of branches that fetch encountered
|
|
|
|
|
system.cpu.fetch.CacheLines 814 # Number of cache lines fetched
|
|
|
|
|
system.cpu.fetch.Cycles 1788 # Number of cycles fetch has run and was not squashing or blocked
|
|
|
|
|
system.cpu.fetch.IcacheSquashes 145 # Number of outstanding Icache misses that were squashed
|
|
|
|
|
system.cpu.fetch.Insts 5562 # Number of instructions fetch has processed
|
|
|
|
|
system.cpu.fetch.SquashCycles 260 # Number of cycles fetch has spent squashing
|
|
|
|
|
system.cpu.fetch.branchRate 0.031316 # Number of branch fetches per cycle
|
|
|
|
|
system.cpu.fetch.icacheStallCycles 814 # Number of cycles fetch is stalled on an Icache miss
|
|
|
|
|
system.cpu.fetch.predictedBranches 372 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.195487 # Number of inst fetches per cycle
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 28452
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2006-10-14 00:59:29 +02:00
|
|
|
0 27494 9663.29%
|
|
|
|
|
1 51 17.92%
|
|
|
|
|
2 92 32.34%
|
|
|
|
|
3 74 26.01%
|
|
|
|
|
4 117 41.12%
|
|
|
|
|
5 71 24.95%
|
|
|
|
|
6 43 15.11%
|
|
|
|
|
7 56 19.68%
|
|
|
|
|
8 454 159.57%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 4971.589641 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4152.244565 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_hits 563 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 1247869 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.308354 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 251 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 67 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 764013 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.226044 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets 3445 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 3.059783 # Average number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.blocked_no_targets 4 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.blocked_cycles_no_targets 13780 # number of cycles access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.demand_accesses 814 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 4971.589641 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 563 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 1247869 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.308354 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 251 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 67 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 764013 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.226044 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.overall_accesses 814 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 4971.589641 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4152.244565 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.overall_hits 563 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 1247869 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.308354 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 251 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 67 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 764013 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.226044 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 0 # number of replacements
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.icache.tagsinuse 91.596526 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 563 # Total number of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.idleCycles 723576 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 571 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 266 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 0.119043 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 1018 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 343 # Number of stores executed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.WB:consumers 1875 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 3246 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.785067 # average fanout of values written-back
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.WB:producers 1472 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 0.114087 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 3258 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 160 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 14741 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 784 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 71 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 376 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 4271 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 675 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 113 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 3387 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 82 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2006-10-07 17:32:10 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 369 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 82 # Number of stores squashed
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 99 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.003174 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.003174 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 3500 # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
2006-11-06 02:42:05 +01:00
|
|
|
(null) 0 0.00% # Type of FU issued
|
|
|
|
|
IntAlu 2460 70.29% # Type of FU issued
|
|
|
|
|
IntMult 1 0.03% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
|
|
|
MemRead 695 19.86% # Type of FU issued
|
|
|
|
|
MemWrite 344 9.83% # Type of FU issued
|
|
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.010000 # FU busy rate (busy events/executed inst)
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
2006-10-14 00:59:29 +02:00
|
|
|
IntAlu 2 5.71% # attempts to use FU when none available
|
2006-09-01 23:59:36 +02:00
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
2006-10-14 00:59:29 +02:00
|
|
|
MemRead 11 31.43% # attempts to use FU when none available
|
|
|
|
|
MemWrite 22 62.86% # attempts to use FU when none available
|
2006-09-01 23:59:36 +02:00
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 28452
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2006-10-14 00:59:29 +02:00
|
|
|
0 26938 9467.88%
|
|
|
|
|
1 609 214.04%
|
|
|
|
|
2 344 120.91%
|
|
|
|
|
3 248 87.16%
|
|
|
|
|
4 180 63.26%
|
|
|
|
|
5 81 28.47%
|
|
|
|
|
6 35 12.30%
|
|
|
|
|
7 12 4.22%
|
|
|
|
|
8 5 1.76%
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 0.123014 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 3999 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 3500 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 1423 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 761 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4622.063197 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2296.591078 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 1243335 # number of ReadReq miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 617783 # number of ReadReq MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses
|
2006-10-07 18:58:37 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4622.063197 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 1243335 # number of demand (read+write) miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 617783 # number of demand (read+write) MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4622.063197 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2296.591078 # average overall mshr miss latency
|
2006-11-06 02:42:05 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 1243335 # number of overall miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.overall_misses 269 # number of overall misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 617783 # number of overall MSHR miss cycles
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks.
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 138.802720 # Cycle average of tags in use
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.numCycles 28452 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 14785 # Number of cycles rename is blocking
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
2006-10-14 00:59:29 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 18 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 5396 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
|
|
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 5263 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 4690 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 3393 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 851 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 338 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 25 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 1625 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 7057 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 88 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2006-09-01 23:59:36 +02:00
|
|
|
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
