Update stats for change in functional path in cache
--HG-- extra : convert_revision : 5abc964ca95b80522266c5c1bc5e661d41f2798a
This commit is contained in:
Ron Dreslinski
parent
467c17fbd9
commit
413a5379b8
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@ -2,39 +2,39 @@
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 542 # Number of BTB hits
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global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
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global.BPredUnit.BTBLookups 1936 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
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global.BPredUnit.lookups 2256 # Number of BP lookups
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global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted
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global.BPredUnit.lookups 2254 # Number of BP lookups
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global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
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host_inst_rate 25564 # Simulator instruction rate (inst/s)
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host_mem_usage 160400 # Number of bytes of host memory used
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host_seconds 0.22 # Real time elapsed on the host
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host_tick_rate 31189 # Simulator tick rate (ticks/s)
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host_inst_rate 47059 # Simulator instruction rate (inst/s)
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host_mem_usage 160380 # Number of bytes of host memory used
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host_seconds 0.12 # Real time elapsed on the host
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host_tick_rate 57322 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5623 # Number of instructions simulated
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sim_seconds 0.000000 # Number of seconds simulated
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sim_ticks 6870 # Number of ticks simulated
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sim_ticks 6868 # Number of ticks simulated
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system.cpu.commit.COM:branches 862 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 6116
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system.cpu.commit.COM:committed_per_cycle.samples 6115
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 3908 6389.80%
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1 1064 1739.70%
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2 389 636.04%
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3 210 343.36%
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4 153 250.16%
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5 93 152.06%
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6 76 124.26%
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7 149 243.62%
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8 74 120.99%
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0 3908 6390.84%
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1 1063 1738.35%
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2 389 636.14%
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3 210 343.42%
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4 152 248.57%
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5 94 153.72%
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6 76 124.28%
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7 149 243.66%
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8 74 121.01%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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@ -46,67 +46,67 @@ system.cpu.commit.COM:swp_count 0 # Nu
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system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
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system.cpu.commit.commitSquashedInsts 4342 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 5623 # Number of Instructions Simulated
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system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
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system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1539 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1414 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.081222 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.064977 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
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system.cpu.cpi 1.221412 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 1.221412 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1536 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3.038760 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.235294 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1407 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 392 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.083984 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 129 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 228 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.066406 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 102 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 2.564246 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
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system.cpu.dcache.WriteReq_miss_rate 0.220443 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 179 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.087438 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11.511236 # Average number of references to valid blocks.
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system.cpu.dcache.avg_refs 11.791908 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2360 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2049 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.131780 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.072458 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_accesses 2348 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 2.762987 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2040 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 851 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.131175 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 308 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 380 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.073680 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 2360 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
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system.cpu.dcache.overall_accesses 2348 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 2.762987 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 2049 # number of overall hits
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system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.131780 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 311 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.072458 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
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system.cpu.dcache.overall_hits 2040 # number of overall hits
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system.cpu.dcache.overall_miss_latency 851 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.131175 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 308 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 135 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 380 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.073680 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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@ -119,43 +119,43 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
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system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2049 # Total number of references to valid blocks.
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system.cpu.dcache.tagsinuse 114.960547 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2040 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
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system.cpu.decode.DECODE:IdleCycles 3541 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashCycles 753 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
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system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
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system.cpu.fetch.Branches 2254 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
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system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.Cycles 3904 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
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system.cpu.fetch.Insts 13699 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
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system.cpu.fetch.branchRate 0.328141 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
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system.cpu.fetch.rate 1.994322 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 6871
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system.cpu.fetch.rateDist.samples 6869
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system.cpu.fetch.rateDist.min_value 0
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0 4549 6620.58%
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1 174 253.24%
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2 186 270.70%
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3 157 228.50%
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4 211 307.09%
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5 153 222.68%
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6 171 248.87%
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7 105 152.82%
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8 1165 1695.53%
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0 4548 6621.05%
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1 174 253.31%
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2 186 270.78%
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3 157 228.56%
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4 211 307.18%
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5 153 222.74%
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6 171 248.94%
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7 105 152.86%
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8 1164 1694.57%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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@ -218,38 +218,38 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
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system.cpu.icache.tagsinuse 176.439074 # Cycle average of tags in use
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system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.iew.EXEC:branches 1206 # Number of branches executed
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system.cpu.iew.EXEC:nop 37 # number of nop insts executed
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system.cpu.iew.EXEC:rate 1.157910 # Inst execution rate
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system.cpu.iew.EXEC:refs 2596 # number of memory reference insts executed
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system.cpu.iew.EXEC:rate 1.157374 # Inst execution rate
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system.cpu.iew.EXEC:refs 2595 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 985 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 5411 # num instructions consuming a value
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system.cpu.iew.WB:count 7675 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.744225 # average fanout of values written-back
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system.cpu.iew.WB:consumers 5409 # num instructions consuming a value
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system.cpu.iew.WB:count 7670 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.744130 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 4027 # num instructions producing a value
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system.cpu.iew.WB:rate 1.117014 # insts written-back per cycle
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system.cpu.iew.WB:sent 7748 # cumulative count of insts sent to commit
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system.cpu.iew.WB:producers 4025 # num instructions producing a value
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system.cpu.iew.WB:rate 1.116611 # insts written-back per cycle
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system.cpu.iew.WB:sent 7743 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
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system.cpu.iew.iewDispLoadInsts 2049 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
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system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute
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system.cpu.iew.iewExecutedInsts 7956 # Number of executed instructions
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system.cpu.iew.iewDispatchedInsts 9982 # Number of instructions dispatched to IQ
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system.cpu.iew.iewExecLoadInsts 1610 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 7950 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewSquashCycles 753 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
|
||||
|
|
@ -259,17 +259,17 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu
|
|||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 41 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1070 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 8363 # Type of FU issued
|
||||
system.cpu.ipc 0.818725 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.818725 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 8359 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
(null) 2 0.02% # Type of FU issued
|
||||
IntAlu 5577 66.69% # Type of FU issued
|
||||
IntAlu 5573 66.67% # Type of FU issued
|
||||
IntMult 1 0.01% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2 0.02% # Type of FU issued
|
||||
|
|
@ -278,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 1757 21.01% # Type of FU issued
|
||||
MemWrite 1024 12.24% # Type of FU issued
|
||||
MemRead 1757 21.02% # Type of FU issued
|
||||
MemWrite 1024 12.25% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.013751 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.013758 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
(null) 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1 0.87% # attempts to use FU when none available
|
||||
|
|
@ -302,72 +302,74 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 6869
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 3761 5473.73%
|
||||
1 893 1299.67%
|
||||
2 720 1047.88%
|
||||
3 615 895.07%
|
||||
4 447 650.56%
|
||||
5 278 404.60%
|
||||
6 104 151.36%
|
||||
7 41 59.67%
|
||||
8 12 17.46%
|
||||
0 3761 5475.32%
|
||||
1 891 1297.13%
|
||||
2 720 1048.19%
|
||||
3 617 898.24%
|
||||
4 445 647.84%
|
||||
5 278 404.72%
|
||||
6 104 151.40%
|
||||
7 41 59.69%
|
||||
8 12 17.47%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.217145 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8363 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 1.216917 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 9924 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 8359 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 3993 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsExamined 3985 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2571 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2568 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadReq_accesses 494 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2.071138 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1019 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.995951 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 492 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.008130 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
|
||||
system.cpu.l2cache.demand_accesses 496 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.991935 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.991935 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
|
||||
system.cpu.l2cache.overall_accesses 496 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 497 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.991935 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 492 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.991935 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -380,22 +382,22 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 6871 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 6869 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:IdleCycles 3757 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:SquashCycles 753 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 7 2006 11:12:49
|
||||
M5 started Sat Oct 7 11:12:59 2006
|
||||
M5 compiled Oct 7 2006 12:38:12
|
||||
M5 started Sat Oct 7 12:38:34 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Exiting @ tick 6870 because target called exit()
|
||||
Exiting @ tick 6868 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,67 +1,67 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 305072 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159668 # Number of bytes of host memory used
|
||||
host_inst_rate 286207 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159648 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 439277 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 413300 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5642 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 8312 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 981 # number of ReadReq accesses(hits+misses)
|
||||
sim_ticks 8316 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 891 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 270 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.091743 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 180 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.091743 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2.737500 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 276 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 184 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 741 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 219 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.097442 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 80 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 146 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.088916 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 9.600000 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1802 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 2.876471 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1632 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 489 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.094340 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 170 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 495 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.090455 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 330 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 1802 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 2.876471 # average overall miss latency
|
||||
system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1632 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 489 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.094340 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 170 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 1626 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 495 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 165 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.090455 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 163 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 330 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 112.055094 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1632 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 107.125526 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -138,55 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 133.267292 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 133.213539 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5366 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 1.968610 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 442 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 878 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997763 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 446 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 439 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.982103 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 439 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 882 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997738 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.002242 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.006803 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 1.968610 # average overall miss latency
|
||||
system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 878 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.993243 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 439 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.982103 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.993243 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency
|
||||
system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 446 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.993243 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 441 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 439 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.982103 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.993243 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -199,10 +201,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 446 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 245.259112 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 7 2006 11:12:49
|
||||
M5 started Sat Oct 7 11:13:04 2006
|
||||
M5 compiled Oct 7 2006 12:38:12
|
||||
M5 started Sat Oct 7 12:38:38 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
|
||||
Exiting @ tick 8312 because target called exit()
|
||||
Exiting @ tick 8316 because target called exit()
|
||||
|
|
|
|||
|
|
@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu
|
|||
global.BPredUnit.condPredicted 441 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 888 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 47938 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159916 # Number of bytes of host memory used
|
||||
host_inst_rate 45832 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159900 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 57613 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 55090 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit.
|
||||
|
|
@ -51,16 +51,16 @@ system.cpu.committedInsts 2387 # Nu
|
|||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 535 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses 534 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.121495 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.121723 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.114019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.114232 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency
|
||||
|
|
@ -75,37 +75,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # m
|
|||
system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 8.305882 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 8.294118 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 829 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses 828 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 706 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits 705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.148372 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.148551 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.102533 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.102657 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 829 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 828 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 706 # number of overall hits
|
||||
system.cpu.dcache.overall_hits 705 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.148372 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.148551 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 123 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.102533 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.102657 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -122,7 +122,7 @@ system.cpu.dcache.replacements 0 # nu
|
|||
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 706 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 705 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked
|
||||
|
|
@ -333,8 +333,8 @@ system.cpu.l2cache.ReadReq_misses 274 # nu
|
|||
system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 7 2006 11:12:49
|
||||
M5 started Sat Oct 7 11:13:07 2006
|
||||
M5 compiled Oct 7 2006 12:38:12
|
||||
M5 started Sat Oct 7 12:38:40 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
|
||||
Exiting @ tick 2886 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,22 +1,22 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 250729 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159188 # Number of bytes of host memory used
|
||||
host_inst_rate 196989 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159172 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 352925 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 279840 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2578 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 3777 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 165 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
|
||||
|
|
@ -30,37 +30,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # m
|
|||
system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 246 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 628 # number of overall hits
|
||||
system.cpu.dcache.overall_hits 627 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 246 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 82 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -77,7 +77,7 @@ system.cpu.dcache.replacements 0 # nu
|
|||
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 628 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 7 2006 11:12:49
|
||||
M5 started Sat Oct 7 11:13:10 2006
|
||||
M5 compiled Oct 7 2006 12:38:12
|
||||
M5 started Sat Oct 7 12:38:45 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
|
||||
Exiting @ tick 3777 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,67 +1,67 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 129834 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 158964 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 194881 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 273933 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159012 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 403699 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5657 # Number of instructions simulated
|
||||
sim_seconds 0.000000 # Number of seconds simulated
|
||||
sim_ticks 8573 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses)
|
||||
sim_ticks 8579 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 237 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.069850 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 79 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 158 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.069850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 79 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 933 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 2.586207 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 246 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 164 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 875 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 150 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.062165 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.053591 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 14.065693 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 2.824818 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1927 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 387 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.066376 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 137 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 396 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 258 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.062500 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 129 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 264 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 2.824818 # average overall miss latency
|
||||
system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1927 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 387 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.066376 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 137 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 1922 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 396 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 132 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 258 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.062500 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 129 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 264 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 137 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 91.822487 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1927 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 86.924009 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -138,55 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 138.188010 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 138.192774 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 440 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 1.963470 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 860 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.995455 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 438 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 430 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977273 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 866 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 433 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReq_accesses 1 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReq_hits 1 # number of WriteReq hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.004566 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.006928 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 440 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 1.963470 # average overall miss latency
|
||||
system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 860 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995455 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 438 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 866 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.993119 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 430 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.977273 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 430 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 433 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.993119 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 440 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 1.963470 # average overall miss latency
|
||||
system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 860 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995455 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 438 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 866 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.993119 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 433 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 430 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.977273 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 430 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 433 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.993119 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -199,10 +201,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 438 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 231.300093 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 226.406294 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
|
|
|
|||
|
|
@ -6,8 +6,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Sep 5 2006 15:37:09
|
||||
M5 started Tue Sep 5 15:46:32 2006
|
||||
M5 compiled Oct 7 2006 12:52:26
|
||||
M5 started Sat Oct 7 12:52:42 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
|
||||
Exiting @ tick 8573 because target called exit()
|
||||
Exiting @ tick 8579 because target called exit()
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -7,8 +7,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 7 2006 11:12:49
|
||||
M5 started Sat Oct 7 11:13:13 2006
|
||||
M5 compiled Oct 7 2006 12:38:12
|
||||
M5 started Sat Oct 7 12:38:47 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Exiting @ tick 8429 because target called exit()
|
||||
Exiting @ tick 8441 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,67 +1,67 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 309857 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159252 # Number of bytes of host memory used
|
||||
host_seconds 1.61 # Real time elapsed on the host
|
||||
host_tick_rate 422749 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 618043 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 159232 # Number of bytes of host memory used
|
||||
host_seconds 0.81 # Real time elapsed on the host
|
||||
host_tick_rate 843177 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 500000 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 682354 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 124564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 2.987952 # average ReadReq miss latency
|
||||
sim_ticks 682488 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 124315 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 744 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001999 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 249 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 496 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001991 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 248 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 56744 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 1.256024 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 945 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 630 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 56412 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 417 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005851 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 332 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002450 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 311.061962 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 181308 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 1.998279 # average overall miss latency
|
||||
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 180727 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1161 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003204 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 581 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1362 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 774 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002134 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 387 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 908 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 181308 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 1.998279 # average overall miss latency
|
||||
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 180727 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1161 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003204 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 581 # number of overall misses
|
||||
system.cpu.dcache.overall_hits 180321 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1362 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 454 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 774 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002134 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 387 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 908 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 581 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 347.118131 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180727 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 291.968600 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -138,54 +138,56 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 268.434590 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 268.423238 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 499597 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 984 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 1.605691 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1580 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1714 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 984 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 790 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.802846 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 790 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 857 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReq_accesses 165 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReq_hits 165 # number of WriteReq hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.192532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 984 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 1.605691 # average overall miss latency
|
||||
system.cpu.l2cache.demand_accesses 1022 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1580 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 984 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_hits 165 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1714 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.838552 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 790 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.802846 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 790 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 857 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.838552 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 984 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 1.605691 # average overall miss latency
|
||||
system.cpu.l2cache.overall_accesses 1022 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1580 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 984 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 165 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1714 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.838552 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 857 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 790 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.802846 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 790 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 857 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.838552 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -198,10 +200,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 984 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 615.553879 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 560.393094 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 165 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Oct 7 2006 11:12:49
|
||||
M5 started Sat Oct 7 11:13:19 2006
|
||||
M5 compiled Oct 7 2006 12:38:12
|
||||
M5 started Sat Oct 7 12:38:52 2006
|
||||
M5 executing on zizzer.eecs.umich.edu
|
||||
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
|
||||
Exiting @ tick 682354 because a thread reached the max instruction count
|
||||
Exiting @ tick 682488 because a thread reached the max instruction count
|
||||
|
|
|
|||
Loading…
Reference in a new issue