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update for small parameter and statistics name changes

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--HG--
extra : convert_revision : d538b79986c11a462ab285c167cef45dd793da32
This commit is contained in:
Nathan Binkert 2007-06-12 07:56:53 -07:00
parent 125237d357
commit 1a3e668446
62 changed files with 236 additions and 246 deletions
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8
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -99,7 +99,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -274,7 +274,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -312,7 +312,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -366,7 +366,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

6
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
View file

@ -275,7 +275,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -312,7 +312,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -349,7 +349,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

11
tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
View file

@ -8,10 +8,9 @@ global.BPredUnit.condIncorrect 422 # Nu
global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted
global.BPredUnit.lookups 1843 # Number of BP lookups
global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target.
host_inst_rate 54565 # Simulator instruction rate (inst/s)
host_mem_usage 154084 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 44392410 # Simulator tick rate (ticks/s)
host_inst_rate 7145 # Simulator instruction rate (inst/s)
host_seconds 0.79 # Real time elapsed on the host
host_tick_rate 5828052 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 127 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit.
@ -269,7 +268,7 @@ system.cpu.ipc 0.611395 # IP
system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 2 0.03% # Type of FU issued
No_OpClass 2 0.03% # Type of FU issued
IntAlu 5322 66.68% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
@ -287,7 +286,7 @@ system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 0 0.00% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available

8
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:39 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:32 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 4588000 because target called exit()

2
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
View file

@ -53,7 +53,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory

7
tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 576538 # Simulator instruction rate (inst/s)
host_mem_usage 148208 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 276546720 # Simulator tick rate (ticks/s)
host_inst_rate 93019 # Simulator instruction rate (inst/s)
host_seconds 0.06 # Real time elapsed on the host
host_tick_rate 46199079 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated

8
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:40 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:34 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2820500 because target called exit()

8
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -44,7 +44,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -82,7 +82,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -120,7 +120,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -174,7 +174,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

6
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out
View file

@ -94,7 +94,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -131,7 +131,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -168,7 +168,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

7
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 280990 # Simulator instruction rate (inst/s)
host_mem_usage 153668 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 642654954 # Simulator tick rate (ticks/s)
host_inst_rate 54390 # Simulator instruction rate (inst/s)
host_seconds 0.10 # Real time elapsed on the host
host_tick_rate 126525357 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000013 # Number of seconds simulated

8
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:40 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:35 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 13168000 because target called exit()

8
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
View file

@ -99,7 +99,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -274,7 +274,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -312,7 +312,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -366,7 +366,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

6
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
View file

@ -275,7 +275,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -312,7 +312,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -349,7 +349,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

11
tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
View file

@ -8,10 +8,9 @@ global.BPredUnit.condIncorrect 208 # Nu
global.BPredUnit.condPredicted 376 # Number of conditional branches predicted
global.BPredUnit.lookups 738 # Number of BP lookups
global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target.
host_inst_rate 54176 # Simulator instruction rate (inst/s)
host_mem_usage 153592 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
host_tick_rate 46286693 # Simulator tick rate (ticks/s)
host_inst_rate 8881 # Simulator instruction rate (inst/s)
host_seconds 0.27 # Real time elapsed on the host
host_tick_rate 7632084 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit.
@ -268,7 +267,7 @@ system.cpu.ipc 0.580920 # IP
system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
No_OpClass 0 0.00% # Type of FU issued
IntAlu 2178 70.83% # Type of FU issued
IntMult 1 0.03% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
@ -286,7 +285,7 @@ system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 2 5.71% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available

8
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:41 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:36 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 2053000 because target called exit()

2
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -53,7 +53,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory

7
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 484860 # Simulator instruction rate (inst/s)
host_mem_usage 147796 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 225459318 # Simulator tick rate (ticks/s)
host_inst_rate 111994 # Simulator instruction rate (inst/s)
host_seconds 0.02 # Real time elapsed on the host
host_tick_rate 55017079 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated

8
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:42 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:37 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 1288500 because target called exit()

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
View file

@ -44,7 +44,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -82,7 +82,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -120,7 +120,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -174,7 +174,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

6
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
View file

@ -94,7 +94,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -131,7 +131,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -168,7 +168,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

7
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 228404 # Simulator instruction rate (inst/s)
host_mem_usage 153176 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
host_tick_rate 552831639 # Simulator tick rate (ticks/s)
host_inst_rate 51133 # Simulator instruction rate (inst/s)
host_seconds 0.05 # Real time elapsed on the host
host_tick_rate 127514531 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000006 # Number of seconds simulated

8
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
View file

@ -6,9 +6,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:42 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:37 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 6472000 because target called exit()

8
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
View file

@ -99,7 +99,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -274,7 +274,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -312,7 +312,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -382,7 +382,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

6
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out
View file

@ -291,7 +291,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -328,7 +328,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -365,7 +365,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

15
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
View file

@ -8,10 +8,9 @@ global.BPredUnit.condIncorrect 1115 # Nu
global.BPredUnit.condPredicted 2318 # Number of conditional branches predicted
global.BPredUnit.lookups 3964 # Number of BP lookups
global.BPredUnit.usedRAS 532 # Number of times the RAS was used to get a target.
host_inst_rate 56668 # Simulator instruction rate (inst/s)
host_mem_usage 154692 # Number of bytes of host memory used
host_seconds 0.20 # Real time elapsed on the host
host_tick_rate 27618195 # Simulator tick rate (ticks/s)
host_inst_rate 8215 # Simulator instruction rate (inst/s)
host_seconds 1.37 # Real time elapsed on the host
host_tick_rate 4009351 # Simulator tick rate (ticks/s)
memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads.
memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads.
memdepunit.memDep.conflictingStores 54 # Number of conflicting stores.
@ -465,7 +464,7 @@ system.cpu.ipc_1 0.512251 # IP
system.cpu.ipc_total 1.024410 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0 8232 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 2 0.02% # Type of FU issued
No_OpClass 2 0.02% # Type of FU issued
IntAlu 5551 67.43% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
@ -482,7 +481,7 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
system.cpu.iq.ISSUE:FU_type_0.end_dist
system.cpu.iq.ISSUE:FU_type_1 8180 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1.start_dist
(null) 2 0.02% # Type of FU issued
No_OpClass 2 0.02% # Type of FU issued
IntAlu 5536 67.68% # Type of FU issued
IntMult 1 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
@ -499,7 +498,7 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist
system.cpu.iq.ISSUE:FU_type_1.end_dist
system.cpu.iq.ISSUE:FU_type 16412 # Type of FU issued
system.cpu.iq.ISSUE:FU_type.start_dist
(null) 4 0.02% # Type of FU issued
No_OpClass 4 0.02% # Type of FU issued
IntAlu 11087 67.55% # Type of FU issued
IntMult 2 0.01% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
@ -521,7 +520,7 @@ system.cpu.iq.ISSUE:fu_busy_rate 0.010968 # FU
system.cpu.iq.ISSUE:fu_busy_rate_0 0.005606 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_busy_rate_1 0.005362 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
No_OpClass 0 0.00% # attempts to use FU when none available
IntAlu 16 8.89% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available

8
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:42 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:38 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 5490000 because target called exit()

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
View file

@ -76,7 +76,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -124,7 +124,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -198,7 +198,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -246,7 +246,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -345,7 +345,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -376,7 +376,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
[system.membus.responder]
type=IsaFake

10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out
View file

@ -86,7 +86,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -207,7 +207,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -249,7 +249,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -322,7 +322,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -364,7 +364,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

7
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 607412 # Simulator instruction rate (inst/s)
host_mem_usage 245896 # Number of bytes of host memory used
host_seconds 103.93 # Real time elapsed on the host
host_tick_rate 17996726251 # Simulator tick rate (ticks/s)
host_inst_rate 110028 # Simulator instruction rate (inst/s)
host_seconds 573.73 # Real time elapsed on the host
host_tick_rate 3259967057 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63125943 # Number of instructions simulated
sim_seconds 1.870335 # Number of seconds simulated

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
View file

@ -1,5 +1,5 @@
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
0: system.remote_gdb.listener: listening for remote gdb on port 7002
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: 97861500: Trying to launch CPU number 1!

9
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
View file

@ -5,9 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 19:06:05
M5 started Tue May 15 19:06:07 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 01:04:58 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 1870335097000 because m5_exit instruction encountered

8
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
View file

@ -76,7 +76,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -124,7 +124,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -223,7 +223,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -254,7 +254,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
[system.membus.responder]
type=IsaFake

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out
View file

@ -86,7 +86,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -722,7 +722,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -764,7 +764,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

7
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 577751 # Simulator instruction rate (inst/s)
host_mem_usage 244724 # Number of bytes of host memory used
host_seconds 103.86 # Real time elapsed on the host
host_tick_rate 17603359253 # Simulator tick rate (ticks/s)
host_inst_rate 109117 # Simulator instruction rate (inst/s)
host_seconds 549.94 # Real time elapsed on the host
host_tick_rate 3324672454 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60007317 # Number of instructions simulated
sim_seconds 1.828355 # Number of seconds simulated

2
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
View file

@ -1,3 +1,3 @@
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb on port 7000
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: Entering event queue @ 0. Starting simulation...

9
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
View file

@ -5,9 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 19:06:05
M5 started Tue May 15 19:06:07 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 00:55:45 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 1828355481500 because m5_exit instruction encountered

12
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
View file

@ -74,7 +74,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -122,7 +122,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -194,7 +194,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -242,7 +242,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -341,7 +341,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -372,7 +372,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
[system.membus.responder]
type=IsaFake

10
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out
View file

@ -86,7 +86,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -207,7 +207,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -249,7 +249,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -322,7 +322,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -364,7 +364,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

7
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 213082 # Simulator instruction rate (inst/s)
host_mem_usage 203724 # Number of bytes of host memory used
host_seconds 296.83 # Real time elapsed on the host
host_tick_rate 6573231278 # Simulator tick rate (ticks/s)
host_inst_rate 62524 # Simulator instruction rate (inst/s)
host_seconds 1011.60 # Real time elapsed on the host
host_tick_rate 1928760125 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63248814 # Number of instructions simulated
sim_seconds 1.951129 # Number of seconds simulated

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
View file

@ -1,5 +1,5 @@
Listening for system connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb on port 7001
0: system.remote_gdb.listener: listening for remote gdb on port 7002
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: 423901000: Trying to launch CPU number 1!

9
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
View file

@ -5,9 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 19:06:05
M5 started Tue May 15 19:07:53 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 01:30:38 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 1951129131000 because m5_exit instruction encountered

8
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
View file

@ -74,7 +74,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -122,7 +122,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -221,7 +221,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -252,7 +252,7 @@ clock=1000
responder_set=false
width=64
default=system.membus.responder.pio
port=system.bridge.side_b system.physmem.port system.l2c.mem_side
port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
[system.membus.responder]
type=IsaFake

6
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out
View file

@ -86,7 +86,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -722,7 +722,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -764,7 +764,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

7
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 212380 # Simulator instruction rate (inst/s)
host_mem_usage 201984 # Number of bytes of host memory used
host_seconds 282.69 # Real time elapsed on the host
host_tick_rate 6746442466 # Simulator tick rate (ticks/s)
host_inst_rate 62427 # Simulator instruction rate (inst/s)
host_seconds 961.73 # Real time elapsed on the host
host_tick_rate 1983042717 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60037406 # Number of instructions simulated
sim_seconds 1.907146 # Number of seconds simulated

2
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
View file

@ -1,3 +1,3 @@
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb on port 7000
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: Entering event queue @ 0. Starting simulation...

9
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
View file

@ -5,9 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 19:06:05
M5 started Tue May 15 19:07:53 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 01:14:34 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 1907146437000 because m5_exit instruction encountered

2
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
View file

@ -44,7 +44,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory

7
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 819297 # Simulator instruction rate (inst/s)
host_mem_usage 147636 # Number of bytes of host memory used
host_seconds 0.61 # Real time elapsed on the host
host_tick_rate 409362131 # Simulator tick rate (ticks/s)
host_inst_rate 188118 # Simulator instruction rate (inst/s)
host_seconds 2.66 # Real time elapsed on the host
host_tick_rate 94046824 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated

8
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:43 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:41 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 249999500 because a thread reached the max instruction count

8
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
View file

@ -44,7 +44,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -82,7 +82,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -120,7 +120,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -165,7 +165,7 @@ bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side
port=system.physmem.port[0] system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory

6
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
View file

@ -85,7 +85,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -122,7 +122,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -159,7 +159,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

7
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
View file

@ -1,9 +1,8 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 392036 # Simulator instruction rate (inst/s)
host_mem_usage 153128 # Number of bytes of host memory used
host_seconds 1.28 # Real time elapsed on the host
host_tick_rate 542334315 # Simulator tick rate (ticks/s)
host_inst_rate 83773 # Simulator instruction rate (inst/s)
host_seconds 5.97 # Real time elapsed on the host
host_tick_rate 115920990 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000692 # Number of seconds simulated

8
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
View file

@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 14 2007 16:35:50
M5 started Tue May 15 12:18:44 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:44 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 691915000 because a thread reached the max instruction count

18
tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
View file

@ -42,7 +42,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -102,7 +102,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -162,7 +162,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -222,7 +222,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -282,7 +282,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -342,7 +342,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -402,7 +402,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -462,7 +462,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=10000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none
@ -513,7 +513,7 @@ prefetch_access=false
prefetch_cache_check_push=true
prefetch_data_accesses_only=false
prefetch_degree=1
prefetch_latency=10
prefetch_latency=100000
prefetch_miss=false
prefetch_past_page=false
prefetch_policy=none

18
tests/quick/50.memtest/ref/alpha/linux/memtest/config.out
View file

@ -52,7 +52,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=100000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -107,7 +107,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -162,7 +162,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -217,7 +217,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -272,7 +272,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -327,7 +327,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -382,7 +382,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -437,7 +437,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true
@ -499,7 +499,7 @@ prefetch_access=false
prefetcher_size=100
prefetch_past_page=false
prefetch_serial_squash=false
prefetch_latency=10
prefetch_latency=10000
prefetch_degree=1
prefetch_policy=none
prefetch_cache_check_push=true

5
tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
View file

@ -1,8 +1,7 @@
---------- Begin Simulation Statistics ----------
host_mem_usage 1265676 # Number of bytes of host memory used
host_seconds 390.60 # Real time elapsed on the host
host_tick_rate 215953 # Simulator tick rate (ticks/s)
host_seconds 37943.64 # Real time elapsed on the host
host_tick_rate 2223 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_seconds 0.000084 # Number of seconds simulated
sim_ticks 84350509 # Number of ticks simulated

8
tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
View file

@ -5,9 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 18 2007 23:44:20
M5 started Fri May 18 23:46:19 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
M5 compiled Jun 10 2007 14:06:20
M5 started Sun Jun 10 14:22:51 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 84350509 because Maximum number of loads reached!

8
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
View file

@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=drivesys.physmem
readfile=/tmp/newmem/configs/boot/netperf-server.rcS
readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
@ -128,7 +128,7 @@ clock=1000
responder_set=false
width=64
default=drivesys.membus.responder.pio
port=drivesys.bridge.side_b drivesys.physmem.port drivesys.cpu.icache_port drivesys.cpu.dcache_port
port=drivesys.bridge.side_b drivesys.physmem.port[0] drivesys.cpu.icache_port drivesys.cpu.dcache_port
[drivesys.membus.responder]
type=IsaFake
@ -704,7 +704,7 @@ kernel=/dist/m5/system/binaries/vmlinux
mem_mode=atomic
pal=/dist/m5/system/binaries/ts_osfpal
physmem=testsys.physmem
readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS
readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
@ -818,7 +818,7 @@ clock=1000
responder_set=false
width=64
default=testsys.membus.responder.pio
port=testsys.bridge.side_b testsys.physmem.port testsys.cpu.icache_port testsys.cpu.dcache_port
port=testsys.bridge.side_b testsys.physmem.port[0] testsys.cpu.icache_port testsys.cpu.dcache_port
[testsys.membus.responder]
type=IsaFake

4
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out
View file

@ -18,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux
console=/dist/m5/system/binaries/console
pal=/dist/m5/system/binaries/ts_osfpal
boot_osflags=root=/dev/hda1 console=ttyS0
readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS
readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-stream-client.rcS
symbolfile=
init_param=0
system_type=34
@ -643,7 +643,7 @@ kernel=/dist/m5/system/binaries/vmlinux
console=/dist/m5/system/binaries/console
pal=/dist/m5/system/binaries/ts_osfpal
boot_osflags=root=/dev/hda1 console=ttyS0
readfile=/tmp/newmem/configs/boot/netperf-server.rcS
readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-server.rcS
symbolfile=
init_param=0
system_type=34

12
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
View file

@ -139,10 +139,9 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa
drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted
drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
host_inst_rate 36401739 # Simulator instruction rate (inst/s)
host_mem_usage 388436 # Number of bytes of host memory used
host_seconds 7.51 # Real time elapsed on the host
host_tick_rate 26633033203 # Simulator tick rate (ticks/s)
host_inst_rate 6618724 # Simulator instruction rate (inst/s)
host_seconds 41.30 # Real time elapsed on the host
host_tick_rate 4842704130 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273348482 # Number of instructions simulated
sim_seconds 0.200001 # Number of seconds simulated
@ -381,10 +380,9 @@ drivesys.tsunami.ethernet.totalSwi 0 # to
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
host_inst_rate 79025291125 # Simulator instruction rate (inst/s)
host_mem_usage 388436 # Number of bytes of host memory used
host_inst_rate 65191624612 # Simulator instruction rate (inst/s)
host_seconds 0.00 # Real time elapsed on the host
host_tick_rate 211511841 # Simulator tick rate (ticks/s)
host_tick_rate 183725573 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 273348482 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated

6
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
View file

@ -1,6 +1,6 @@
Listening for testsys connection on port 3456
Listening for drivesys connection on port 3458
0: testsys.remote_gdb.listener: listening for remote gdb on port 7000
0: drivesys.remote_gdb.listener: listening for remote gdb on port 7003
Listening for drivesys connection on port 3457
0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001
warn: Entering event queue @ 0. Starting simulation...
warn: Obsolete M5 instruction ivlb encountered.

10
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
View file

@ -5,9 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
M5 compiled May 15 2007 19:06:05
M5 started Tue May 15 19:12:37 2007
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
M5 compiled Jun 10 2007 14:10:03
M5 started Mon Jun 11 01:47:32 2007
M5 executing on iceaxe
command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
Exiting @ tick 4300235844056 because checkpoint