sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

stats: update stats for thermals, indirect BP

Browse source
This commit is contained in:
Curtis Dunham 2016-04-08 11:01:45 -05:00
parent af27586fbc
commit 1d61224a8b
144 changed files with 6746 additions and 6172 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
View file

@ -34,6 +34,8 @@ readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -108,7 +110,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -150,7 +151,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -242,7 +242,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -284,7 +283,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -418,7 +416,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -455,7 +452,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -490,6 +486,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -559,6 +556,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1

2
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
View file

@ -11,4 +11,4 @@ info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
Exiting @ tick 1869358498000 because m5_exit instruction encountered
Exiting @ tick 1869357988000 because m5_exit instruction encountered

8
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
View file

@ -34,6 +34,8 @@ readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -108,7 +110,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -150,7 +151,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -201,7 +201,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -236,6 +235,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -344,7 +344,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -379,6 +378,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

2
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
View file

@ -10,4 +10,4 @@ Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1829332273500 because m5_exit instruction encountered
Exiting @ tick 1829331993500 because m5_exit instruction encountered

2
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
View file

@ -34,6 +34,8 @@ readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

8
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
View file

@ -34,6 +34,8 @@ readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -104,7 +106,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -146,7 +147,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -197,7 +197,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -232,6 +231,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -340,7 +340,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -375,6 +374,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

22
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini
View file

@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -146,7 +148,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -224,7 +225,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -337,7 +337,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -372,6 +371,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -434,7 +434,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -469,6 +468,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -637,6 +637,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@ -1024,8 +1025,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@ -1071,6 +1073,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0

41
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json
View file

@ -64,7 +64,9 @@
"symbolfile": "",
"readfile": "/z/atgutier/gem5/gem5-commit/tests/halt.sh",
"have_large_asid_64": false,
"thermal_model": null,
"phys_addr_range_64": 40,
"work_begin_exit_count": 0,
"have_lpae": false,
"cxx_class": "LinuxArmSystem",
"load_offset": 2147483648,
@ -523,10 +525,6 @@
"freq": 20000,
"type": "RealViewOsc"
},
"type": "SubSystem",
"eventq_index": 0,
"cxx_class": "SubSystem",
"path": "system.realview.mcc",
"osc_clcd": {
"position": 0,
"name": "osc_clcd",
@ -541,6 +539,24 @@
"freq": 42105,
"type": "RealViewOsc"
},
"thermal_domain": null,
"eventq_index": 0,
"cxx_class": "SubSystem",
"path": "system.realview.mcc",
"temp_crtl": {
"system": "system",
"position": 0,
"name": "temp_crtl",
"parent": "system.realview.realview_io",
"dcc": 0,
"site": 0,
"eventq_index": 0,
"cxx_class": "RealViewTemperatureSensor",
"device": 0,
"path": "system.realview.mcc.temp_crtl",
"type": "RealViewTemperatureSensor"
},
"type": "SubSystem",
"osc_system_bus": {
"position": 0,
"name": "osc_system_bus",
@ -572,6 +588,7 @@
"freq": 25000,
"type": "RealViewOsc"
},
"thermal_domain": null,
"osc_sys": {
"position": 0,
"name": "osc_sys",
@ -1139,6 +1156,7 @@
"type": "IsaFake",
"ret_data16": 65535
},
"point_of_coherency": true,
"snoop_filter": null,
"forward_latency": 4,
"clk_domain": "system.clk_domain",
@ -1200,11 +1218,10 @@
"role": "MASTER"
},
"type": "Cache",
"forward_snoops": false,
"writeback_clean": false,
"hit_latency": 50,
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"2147483648:2415919103"
],
@ -1381,6 +1398,7 @@
"role": "SLAVE"
},
"name": "toL2Bus",
"point_of_coherency": false,
"snoop_filter": {
"name": "snoop_filter",
"system": "system",
@ -1451,11 +1469,10 @@
"role": "MASTER"
},
"type": "Cache",
"forward_snoops": true,
"writeback_clean": true,
"hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
],
@ -1544,11 +1561,10 @@
"role": "MASTER"
},
"type": "Cache",
"forward_snoops": true,
"writeback_clean": false,
"hit_latency": 20,
"tgts_per_mshr": 12,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 12,
"addr_ranges": [
"0:18446744073709551615"
],
@ -1627,11 +1643,10 @@
"role": "MASTER"
},
"type": "Cache",
"forward_snoops": true,
"writeback_clean": false,
"hit_latency": 2,
"tgts_per_mshr": 20,
"demand_mshr_reserve": 1,
"tgts_per_mshr": 20,
"addr_ranges": [
"0:18446744073709551615"
],
@ -1690,7 +1705,7 @@
],
"gic_cpu_addr": 738205696,
"work_cpus_ckpt_count": 0,
"work_begin_exit_count": 0,
"thermal_components": [],
"machine_type": "VExpress_EMM",
"flags_addr": 469827632,
"path": "system",

28
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
View file

@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -146,7 +148,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -224,7 +225,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
@ -337,7 +337,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
@ -397,6 +396,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
@ -465,7 +465,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -543,7 +542,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
@ -656,7 +654,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
@ -716,6 +713,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
@ -778,7 +776,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -815,7 +812,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -850,6 +846,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -1018,6 +1015,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@ -1405,8 +1403,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@ -1452,6 +1451,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@ -1675,6 +1684,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1

22
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
View file

@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -146,7 +148,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -224,7 +225,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -337,7 +337,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -372,6 +371,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -434,7 +434,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -469,6 +468,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -637,6 +637,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@ -1024,8 +1025,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@ -1071,6 +1073,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0

28
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
View file

@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -142,7 +144,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -220,7 +221,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
@ -333,7 +333,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
@ -393,6 +392,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
@ -457,7 +457,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -535,7 +534,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=1
is_read_only=true
max_miss_count=0
@ -648,7 +646,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
is_read_only=false
max_miss_count=0
@ -708,6 +705,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
@ -770,7 +768,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -807,7 +804,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -842,6 +838,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -1074,6 +1071,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@ -1461,8 +1459,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@ -1508,6 +1507,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@ -1731,6 +1740,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1

2
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
View file

@ -1082,6 +1082,7 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks
system.cpu0.l2cache.writebacks::total 231848 # number of writebacks
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1793 # number of ReadExReq MSHR hits
@ -2016,6 +2017,7 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks
system.cpu1.l2cache.writebacks::total 26072 # number of writebacks
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 73 # number of ReadExReq MSHR hits

22
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
View file

@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -142,7 +144,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -220,7 +221,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -333,7 +333,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -368,6 +367,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -430,7 +430,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -465,6 +464,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -697,6 +697,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@ -1084,8 +1085,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@ -1131,6 +1133,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0

22
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
View file

@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -146,7 +148,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -224,7 +225,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -526,7 +526,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -563,7 +562,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -598,6 +596,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -766,6 +765,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@ -1153,8 +1153,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@ -1200,6 +1201,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@ -1423,6 +1434,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1

8
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
View file

@ -38,3 +38,11 @@ warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR

22
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
View file

@ -47,6 +47,8 @@ phys_addr_range_64=40
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
reset_addr_64=0
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -142,7 +144,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -220,7 +221,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -518,7 +518,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -555,7 +554,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -590,6 +588,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -822,6 +821,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@ -1209,8 +1209,9 @@ pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
children=osc_clcd osc_mcc osc_peripheral osc_system_bus
children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@ -1256,6 +1257,16 @@ position=0
site=0
voltage_domain=system.voltage_domain
[system.realview.mcc.temp_crtl]
type=RealViewTemperatureSensor
dcc=0
device=0
eventq_index=0
parent=system.realview.realview_io
position=0
site=0
system=system
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
@ -1479,6 +1490,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1

4
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
View file

@ -75,7 +75,3 @@ warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR

10
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
View file

@ -34,6 +34,8 @@ num_work_ids=16
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -144,7 +146,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -196,7 +197,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=2
is_read_only=false
max_miss_count=0
@ -233,7 +233,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -301,7 +300,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=2
is_read_only=false
max_miss_count=0
@ -338,7 +336,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -373,6 +370,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -855,7 +853,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -890,6 +887,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

10
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
View file

@ -34,6 +34,8 @@ num_work_ids=16
readfile=/z/atgutier/gem5/gem5-commit/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -140,7 +142,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -192,7 +193,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=2
is_read_only=false
max_miss_count=0
@ -229,7 +229,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -297,7 +296,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=2
is_read_only=false
max_miss_count=0
@ -334,7 +332,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -369,6 +366,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -851,7 +849,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
@ -886,6 +883,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

6
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
View file

@ -24,6 +24,8 @@ readfile=/z/atgutier/gem5/gem5-commit/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -209,6 +211,7 @@ clk_domain=drivesys.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@ -953,6 +956,8 @@ readfile=/z/atgutier/gem5/gem5-commit/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -1138,6 +1143,7 @@ clk_domain=testsys.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

9
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -120,11 +122,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache

695
tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
View file

@ -13,30 +13,30 @@ sim_insts 6413 # Nu
sim_ops 6413 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 23296 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
system.physmem.bytes_read::total 34112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
system.physmem.bytes_read::total 34048 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 619096973 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 287437880 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 906534853 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 619096973 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 619096973 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 619096973 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 287437880 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 906534853 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 533 # Number of read requests accepted
system.physmem.num_reads::total 532 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 619619139 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 288472822 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 908091961 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 619619139 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 619619139 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 619619139 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 288472822 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 908091961 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 532 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM
system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side
system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::6 1 # Pe
system.physmem.perBankRdBursts::7 5 # Per bank write bursts
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdBursts::9 1 # Per bank write bursts
system.physmem.perBankRdBursts::10 22 # Per bank write bursts
system.physmem.perBankRdBursts::10 21 # Per bank write bursts
system.physmem.perBankRdBursts::11 29 # Per bank write bursts
system.physmem.perBankRdBursts::12 19 # Per bank write bursts
system.physmem.perBankRdBursts::13 127 # Per bank write bursts
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 37524500 # Total gap between requests
system.physmem.totGap 37389500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 533 # Read request sizes (log2)
system.physmem.readPktSize::6 532 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 444 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -186,42 +186,42 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 388.626506 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 254.752349 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 332.370925 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 19 22.89% 44.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11 13.25% 57.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 11 13.25% 71.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2 2.41% 73.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5 6.02% 79.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 2 2.41% 81.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 7 8.43% 90.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8 9.64% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation
system.physmem.totQLat 3516000 # Total ticks spent queuing
system.physmem.totMemAccLat 13509750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6596.62 # Average queueing delay per DRAM burst
system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 387.902439 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 251.688412 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 333.441746 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 19 23.17% 23.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18 21.95% 45.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11 13.41% 58.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 10 12.20% 70.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1 1.22% 71.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 6 7.32% 79.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4 4.88% 84.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5 6.10% 90.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8 9.76% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation
system.physmem.totQLat 3129000 # Total ticks spent queuing
system.physmem.totMemAccLat 13104000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5881.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25346.62 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 906.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 24631.58 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 908.09 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 906.53 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 908.09 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.08 # Data bus utilization in percentage
system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads
system.physmem.busUtil 7.09 # Data bus utilization in percentage
system.physmem.busUtilRead 7.09 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 438 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads
system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 70402.44 # Average gap between requests
system.physmem.pageHitRate 82.18 # Row buffer hit rate, read and write combined
system.physmem.avgGap 70281.02 # Average gap between requests
system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
@ -231,55 +231,59 @@ system.physmem_0.actBackEnergy 21404070 # En
system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 105750 # Time in different power states
system.physmem_0.memoryStateTime::IDLE 16000 # Time in different power states
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ)
system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 20470410 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 886500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 25449690 # Total energy per rank (pJ)
system.physmem_1.averagePower 810.370642 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1337750 # Time in different power states
system.physmem_1.actBackEnergy 20432790 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 920250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 25465305 # Total energy per rank (pJ)
system.physmem_1.averagePower 810.835582 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1481500 # Time in different power states
system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 29041000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 1942 # Number of BP lookups
system.cpu.branchPred.condPredicted 1197 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 362 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1557 # Number of BTB lookups
system.cpu.branchPred.BTBHits 406 # Number of BTB hits
system.cpu.branchPred.lookups 2009 # Number of BP lookups
system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1611 # Number of BTB lookups
system.cpu.branchPred.BTBHits 378 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 26.075787 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 225 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 23.463687 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 338 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 325 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1372 # DTB read hits
system.cpu.dtb.read_hits 1378 # DTB read hits
system.cpu.dtb.read_misses 11 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1383 # DTB read accesses
system.cpu.dtb.write_hits 884 # DTB write hits
system.cpu.dtb.read_accesses 1389 # DTB read accesses
system.cpu.dtb.write_hits 885 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 887 # DTB write accesses
system.cpu.dtb.data_hits 2256 # DTB hits
system.cpu.dtb.write_accesses 888 # DTB write accesses
system.cpu.dtb.data_hits 2263 # DTB hits
system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2270 # DTB accesses
system.cpu.itb.fetch_hits 2673 # ITB hits
system.cpu.dtb.data_accesses 2277 # DTB accesses
system.cpu.itb.fetch_hits 2687 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 2690 # ITB accesses
system.cpu.itb.fetch_accesses 2704 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -293,80 +297,115 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 75258 # number of cpu cycles simulated
system.cpu.numCycles 74988 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6413 # Number of instructions committed
system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1090 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 1148 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 11.735225 # CPI: cycles per instruction
system.cpu.ipc 0.085214 # IPC: instructions per cycle
system.cpu.tickCycles 12565 # Number of cycles that the object actually ticked
system.cpu.idleCycles 62693 # Total number of cycles that the object has spent stopped
system.cpu.cpi 11.693123 # CPI: cycles per instruction
system.cpu.ipc 0.085520 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction
system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction
system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction
system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 6413 # Class of committed instruction
system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked
system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 104.289845 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1974 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.680473 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.715976 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 104.289845 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025461 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025461 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 104.135823 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025424 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025424 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1974 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1974 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1974 # number of overall hits
system.cpu.dcache.overall_hits::total 1974 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 1980 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1980 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1980 # number of overall hits
system.cpu.dcache.overall_hits::total 1980 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 228 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 228 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 228 # number of overall misses
system.cpu.dcache.overall_misses::total 228 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8381500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8381500 # number of ReadReq miss cycles
system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses
system.cpu.dcache.overall_misses::total 227 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 8280500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 8280500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9164500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9164500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 17546000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17546000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17546000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17546000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency::cpu.data 17445000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 17445000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 17445000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 17445000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1342 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077038 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.077038 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2207 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2207 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2207 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2207 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076006 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076006 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.103542 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.103542 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.103542 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.103542 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81373.786408 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 81373.786408 # average ReadReq miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.102855 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.102855 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102855 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102855 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81181.372549 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 81181.372549 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73316 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73316 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76956.140351 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76956.140351 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76956.140351 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76956.140351 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76850.220264 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76850.220264 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76850.220264 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76850.220264 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -375,14 +414,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 59 # number of overall MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
@ -391,82 +430,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7819000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7819000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7723000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7723000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5385500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5385500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13204500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13204500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13204500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13204500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13108500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 13108500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13108500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13108500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071535 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071535 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81447.916667 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81447.916667 # average ReadReq mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076575 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.076575 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076575 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076575 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80447.916667 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80447.916667 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78133.136095 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78133.136095 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78133.136095 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78133.136095 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 175.465909 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2308 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.323288 # Average number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.381868 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 175.465909 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.085677 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.085677 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
system.cpu.icache.tags.occ_blocks::cpu.inst 175.312988 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.085602 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.085602 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 5711 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5711 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2308 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2308 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2308 # number of overall hits
system.cpu.icache.overall_hits::total 2308 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
system.cpu.icache.overall_misses::total 365 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28127000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28127000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28127000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28127000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28127000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28127000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2673 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2673 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2673 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2673 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2673 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2673 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.136551 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.136551 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.136551 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.136551 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.136551 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.136551 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77060.273973 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77060.273973 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77060.273973 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77060.273973 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77060.273973 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77060.273973 # average overall miss latency
system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 5738 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5738 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 2323 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2323 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2323 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 2323 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 2323 # number of overall hits
system.cpu.icache.overall_hits::total 2323 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
system.cpu.icache.overall_misses::total 364 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 27766000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 27766000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 27766000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 27766000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 27766000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 27766000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2687 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2687 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2687 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2687 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2687 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2687 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135467 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.135467 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.135467 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.135467 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.135467 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.135467 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76280.219780 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76280.219780 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76280.219780 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76280.219780 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76280.219780 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76280.219780 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -475,48 +514,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27762000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27762000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27762000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27762000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27762000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27762000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136551 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.136551 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.136551 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76060.273973 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76060.273973 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76060.273973 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76060.273973 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76060.273973 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76060.273973 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27402000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27402000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27402000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27402000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27402000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27402000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135467 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.135467 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.135467 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75280.219780 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75280.219780 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 233.562418 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.479316 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 58.083102 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005355 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.007128 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.327844 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 58.009069 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005351 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001770 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.007121 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@ -525,64 +564,64 @@ system.cpu.l2cache.overall_hits::cpu.inst 1 # n
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 364 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 364 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses
system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
system.cpu.l2cache.overall_misses::total 533 # number of overall misses
system.cpu.l2cache.overall_misses::total 532 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5275000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5275000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27202500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27202500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27202500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12948500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 40151000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27202500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12948500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 40151000 # number of overall miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26844000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 26844000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7577500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7577500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 26844000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12852500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 39696500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 26844000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12852500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 39696500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 533 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 364 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 533 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997260 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997260 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997253 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997253 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997260 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses
system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72260.273973 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72260.273973 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74732.142857 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74732.142857 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79932.291667 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79932.291667 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74732.142857 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76618.343195 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75330.206379 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74732.142857 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76618.343195 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75330.206379 # average overall miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73950.413223 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73950.413223 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78932.291667 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78932.291667 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73950.413223 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76050.295858 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74617.481203 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73950.413223 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76050.295858 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74617.481203 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -593,110 +632,110 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 364 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 364 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4545000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4545000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23562500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23562500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23562500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11258500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 34821000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23562500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11258500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 34821000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23214000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23214000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6617500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6617500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11162500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 34376500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11162500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 34376500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997260 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62260.273973 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62260.273973 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64732.142857 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64732.142857 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69932.291667 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69932.291667 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64732.142857 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66618.343195 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65330.206379 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64732.142857 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66618.343195 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65330.206379 # average overall mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63950.413223 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63950.413223 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68932.291667 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68932.291667 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001873 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.043274 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 533 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001876 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.043315 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 533 99.81% 99.81% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 532 99.81% 99.81% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
system.membus.trans_dist::ReadResp 460 # Transaction distribution
system.membus.trans_dist::ReadResp 459 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 460 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 533 # Request fanout histogram
system.membus.snoop_fanout::samples 532 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 533 # Request fanout histogram
system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 532 # Request fanout histogram
system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 2833750 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 2826750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

9
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache

1130
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

14
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -120,11 +122,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
@ -135,7 +144,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -560,7 +568,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -611,7 +618,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -646,6 +652,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -711,6 +718,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

621
tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
View file

@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000020 # Number of seconds simulated
sim_ticks 20075000 # Number of ticks simulated
final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 20320000 # Number of ticks simulated
final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 31344 # Simulator instruction rate (inst/s)
host_op_rate 31334 # Simulator op (including micro ops) rate (op/s)
@ -13,30 +13,30 @@ sim_insts 2585 # Nu
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 14272 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 19712 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 14272 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory
system.physmem.bytes_read::total 19840 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 710933998 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 270983811 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 981917808 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 710933998 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 710933998 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 710933998 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 270983811 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 981917808 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 308 # Number of read requests accepted
system.physmem.num_reads::total 310 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 708661417 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 267716535 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 976377953 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 708661417 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 708661417 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 708661417 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 267716535 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 976377953 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 310 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 19712 # Total number of bytes read from DRAM
system.physmem.bytesReadDRAM 19840 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 19712 # Total read bytes from the system interface side
system.physmem.bytesReadSys 19840 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@ -52,7 +52,7 @@ system.physmem.perBankRdBursts::7 47 # Pe
system.physmem.perBankRdBursts::8 68 # Per bank write bursts
system.physmem.perBankRdBursts::9 2 # Per bank write bursts
system.physmem.perBankRdBursts::10 15 # Per bank write bursts
system.physmem.perBankRdBursts::11 14 # Per bank write bursts
system.physmem.perBankRdBursts::11 16 # Per bank write bursts
system.physmem.perBankRdBursts::12 18 # Per bank write bursts
system.physmem.perBankRdBursts::13 52 # Per bank write bursts
system.physmem.perBankRdBursts::14 15 # Per bank write bursts
@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 19987000 # Total gap between requests
system.physmem.totGap 20232000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 308 # Read request sizes (log2)
system.physmem.readPktSize::6 310 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
@ -187,41 +187,41 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 430.829268 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 282.802413 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.088769 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 282.076610 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.225077 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 6 14.63% 68.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 4 9.76% 78.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 7.32% 78.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation
system.physmem.totQLat 1568250 # Total ticks spent queuing
system.physmem.totMemAccLat 7343250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5091.72 # Average queueing delay per DRAM burst
system.physmem.totQLat 1648500 # Total ticks spent queuing
system.physmem.totMemAccLat 7461000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5317.74 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23841.72 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 981.92 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 24067.74 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 976.38 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 981.92 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 976.38 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.67 # Data bus utilization in percentage
system.physmem.busUtilRead 7.67 # Data bus utilization in percentage for reads
system.physmem.busUtil 7.63 # Data bus utilization in percentage
system.physmem.busUtilRead 7.63 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 258 # Number of row buffer hits during reads
system.physmem.readRowHits 259 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads
system.physmem.readRowHitRate 83.55 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 64892.86 # Average gap between requests
system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined
system.physmem.avgGap 65264.52 # Average gap between requests
system.physmem.pageHitRate 83.55 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ)
@ -231,55 +231,59 @@ system.physmem_0.actBackEnergy 10605420 # En
system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ)
system.physmem_0.averagePower 803.889152 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 534250 # Time in different power states
system.physmem_0.memoryStateTime::IDLE 681250 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ)
system.physmem_1.readEnergy 1193400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10488285 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 13297980 # Total energy per rank (pJ)
system.physmem_1.averagePower 839.916627 # Core power per rank (mW)
system.physmem_1.totalEnergy 13290180 # Total energy per rank (pJ)
system.physmem_1.averagePower 839.423970 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 787 # Number of BP lookups
system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 164 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 560 # Number of BTB lookups
system.cpu.branchPred.BTBHits 60 # Number of BTB hits
system.cpu.branchPred.lookups 794 # Number of BP lookups
system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups
system.cpu.branchPred.BTBHits 54 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 10.714286 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 9.608541 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 144 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 83 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 0 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 83 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 32 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 506 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_hits 510 # DTB read hits
system.cpu.dtb.read_misses 8 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
system.cpu.dtb.read_accesses 513 # DTB read accesses
system.cpu.dtb.read_accesses 518 # DTB read accesses
system.cpu.dtb.write_hits 307 # DTB write hits
system.cpu.dtb.write_misses 6 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 313 # DTB write accesses
system.cpu.dtb.data_hits 813 # DTB hits
system.cpu.dtb.data_misses 13 # DTB misses
system.cpu.dtb.data_hits 817 # DTB hits
system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
system.cpu.dtb.data_accesses 826 # DTB accesses
system.cpu.itb.fetch_hits 965 # ITB hits
system.cpu.dtb.data_accesses 831 # DTB accesses
system.cpu.itb.fetch_hits 975 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 978 # ITB accesses
system.cpu.itb.fetch_accesses 988 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@ -293,40 +297,75 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
system.cpu.numCycles 40150 # number of cpu cycles simulated
system.cpu.numCycles 40640 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2585 # Number of instructions committed
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
system.cpu.discardedOps 581 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 603 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 15.531915 # CPI: cycles per instruction
system.cpu.ipc 0.064384 # IPC: instructions per cycle
system.cpu.tickCycles 5369 # Number of cycles that the object actually ticked
system.cpu.idleCycles 34781 # Total number of cycles that the object has spent stopped
system.cpu.cpi 15.721470 # CPI: cycles per instruction
system.cpu.ipc 0.063607 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction
system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 72.26% # Class of committed instruction
system.cpu.op_class_0::MemRead 419 16.21% 88.47% # Class of committed instruction
system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 2585 # Class of committed instruction
system.cpu.tickCycles 5416 # Number of cycles that the object actually ticked
system.cpu.idleCycles 35224 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 48.313800 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 689 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 48.513757 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 693 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 8.105882 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 8.152941 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 48.313800 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.011795 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.011795 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 48.513757 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.011844 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.011844 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1671 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1671 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 438 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 438 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 1679 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1679 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 442 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 442 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 689 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 689 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 689 # number of overall hits
system.cpu.dcache.overall_hits::total 689 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 693 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 693 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 693 # number of overall hits
system.cpu.dcache.overall_hits::total 693 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
@ -335,38 +374,38 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n
system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses
system.cpu.dcache.overall_misses::total 104 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4723000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4723500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3258500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7981500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 499 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 499 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency::cpu.data 7982000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7982000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7982000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7982000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 503 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 503 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 793 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 793 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 793 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 793 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.122244 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.122244 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 797 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 797 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 797 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 797 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.121272 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.121272 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.131148 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.131148 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.131148 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.131148 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508 # average ReadReq miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.130489 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.130489 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.130489 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.130489 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77434.426230 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 77434.426230 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 75779.069767 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76745.192308 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76745.192308 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 76750 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 76750 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 76750 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 76750 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -391,82 +430,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4442000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4442000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4442500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4442500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6459500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6459500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6459500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6459500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116232 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116232 # mshr miss rate for ReadReq accesses
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6460000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 6460000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6460000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 6460000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.107188 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.107188 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897 # average ReadReq mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106650 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.106650 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106650 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.106650 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76594.827586 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76594.827586 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 76000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 117.873256 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 742 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3.327354 # Average number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 119.123012 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 750 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3.333333 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 117.873256 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.057555 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.057555 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2153 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2153 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 742 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 742 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 742 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 742 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 742 # number of overall hits
system.cpu.icache.overall_hits::total 742 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses
system.cpu.icache.overall_misses::total 223 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16979500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16979500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16979500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16979500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16979500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16979500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 965 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 965 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 965 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231088 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.231088 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.231088 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.231088 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.231088 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.231088 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76141.255605 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76141.255605 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76141.255605 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76141.255605 # average overall miss latency
system.cpu.icache.tags.occ_blocks::cpu.inst 119.123012 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.058166 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.058166 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2175 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2175 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 750 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 750 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 750 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 750 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 750 # number of overall hits
system.cpu.icache.overall_hits::total 750 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 225 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses
system.cpu.icache.overall_misses::total 225 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17203000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 17203000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 17203000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 17203000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17203000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17203000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 975 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 975 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 975 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 975 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 975 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 975 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230769 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.230769 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.230769 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.230769 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.230769 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.230769 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76457.777778 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76457.777778 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76457.777778 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76457.777778 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76457.777778 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76457.777778 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -475,84 +514,84 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16756500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16756500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16756500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16756500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16756500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16756500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231088 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.231088 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.231088 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75141.255605 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75141.255605 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 225 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16978000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 16978000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16978000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 16978000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16978000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16978000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230769 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230769 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230769 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.230769 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230769 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.230769 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75457.777778 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75457.777778 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75457.777778 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75457.777778 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75457.777778 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 145.780629 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 147.162900 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 283 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 117.989893 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 27.790736 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003601 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.004449 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses
system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.239277 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 27.923624 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003639 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.004491 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 283 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008636 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 223 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 223 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 58 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 58 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses
system.cpu.l2cache.demand_misses::total 310 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
system.cpu.l2cache.overall_misses::total 308 # number of overall misses
system.cpu.l2cache.overall_misses::total 310 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16422000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16422000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16422000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6331000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16422000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6331000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16640500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16640500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 16640500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 6331500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22972000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 16640500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 6331500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22972000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 223 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 223 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 225 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 223 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 225 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 223 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 310 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 225 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 310 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
@ -567,16 +606,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73641.255605 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73641.255605 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73873.376623 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73873.376623 # average overall miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73957.777778 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73957.777778 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75077.586207 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75077.586207 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73957.777778 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74488.235294 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74103.225806 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73957.777778 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74488.235294 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74103.225806 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -587,28 +626,28 @@ system.cpu.l2cache.fast_writes 0 # nu
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 223 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 223 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 58 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 58 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 310 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14192000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14192000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14192000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19673000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14192000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19673000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14390500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14390500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14390500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19872000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14390500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19872000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
@ -623,74 +662,74 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63641.255605 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63641.255605 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63957.777778 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63957.777778 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65077.586207 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65077.586207 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63957.777778 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64488.235294 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64103.225806 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63957.777778 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64488.235294 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64103.225806 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 308 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 223 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 225 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 450 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 620 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14400 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 19840 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 310 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 310 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 310 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 334500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
system.membus.trans_dist::ReadResp 281 # Transaction distribution
system.membus.trans_dist::ReadResp 283 # Transaction distribution
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 281 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadSharedReq 283 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 620 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 620 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19840 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 19840 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 308 # Request fanout histogram
system.membus.snoop_fanout::samples 310 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::0 310 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 308 # Request fanout histogram
system.membus.reqLayer0.occupancy 359500 # Layer occupancy (ticks)
system.membus.snoop_fanout::total 310 # Request fanout histogram
system.membus.reqLayer0.occupancy 363500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 1638750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 8.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 1649000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 8.1 # Layer utilization (%)
---------- End Simulation Statistics ----------

14
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
@ -160,7 +169,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -509,7 +517,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -560,7 +567,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -595,6 +601,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -660,6 +667,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

845
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -151,6 +153,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

7
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -181,7 +181,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -216,6 +215,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -281,6 +281,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

14
tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -122,11 +124,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache
@ -137,7 +146,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -598,7 +606,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -711,7 +718,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -746,6 +752,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -811,6 +818,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

623
tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
View file

@ -1,8 +1,8 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000030 # Number of seconds simulated
sim_ticks 29949500 # Number of ticks simulated
final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_ticks 29977500 # Number of ticks simulated
final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 167534 # Simulator instruction rate (inst/s)
host_op_rate 196036 # Simulator op (including micro ops) rate (op/s)
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu
system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 651155033 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 247652406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 898807439 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 651155033 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 651155033 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 651155033 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 247652406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 898807439 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 421 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 29858000 # Total gap between requests
system.physmem.totGap 29886000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@ -188,31 +188,31 @@ system.physmem.wrQLenPdf::62 0 # Wh
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 287.393665 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 328.869570 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 5 8.06% 67.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4 6.45% 74.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation
system.physmem.totQLat 2201000 # Total ticks spent queuing
system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 2113500 # Total ticks spent queuing
system.physmem.totMemAccLat 10007250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst
system.physmem.avgQLat 5020.19 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgMemAccLat 23770.19 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 898.81 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s
system.physmem.avgRdBWSys 898.81 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.03 # Data bus utilization in percentage
system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads
system.physmem.busUtil 7.02 # Data bus utilization in percentage
system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 70921.62 # Average gap between requests
system.physmem.avgGap 70988.12 # Average gap between requests
system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ)
@ -241,24 +241,28 @@ system.physmem_1.preEnergy 70125 # En
system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ)
system.physmem_1.averagePower 784.282403 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states
system.physmem_1.actBackEnergy 15745680 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 359250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 18523455 # Total energy per rank (pJ)
system.physmem_1.averagePower 784.269066 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1654750 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states
system.physmem_1.memoryStateTime::ACT 22324250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 1912 # Number of BP lookups
system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups
system.cpu.branchPred.BTBHits 347 # Number of BTB hits
system.cpu.branchPred.lookups 1949 # Number of BP lookups
system.cpu.branchPred.condPredicted 1165 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
system.cpu.branchPred.BTBHits 316 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 19.256551 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 133 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 8 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 125 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@ -377,44 +381,79 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
system.cpu.numCycles 59899 # number of cpu cycles simulated
system.cpu.numCycles 59955 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 4605 # Number of instructions committed
system.cpu.committedOps 5391 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 1202 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 13.007383 # CPI: cycles per instruction
system.cpu.ipc 0.076879 # IPC: instructions per cycle
system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked
system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped
system.cpu.cpi 13.019544 # CPI: cycles per instruction
system.cpu.ipc 0.076808 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction
system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction
system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction
system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 5391 # Class of committed instruction
system.cpu.tickCycles 10654 # Number of cycles that the object actually ticked
system.cpu.idleCycles 49301 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 86.495507 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1916 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.123288 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 86.495507 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 4342 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4342 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits
system.cpu.dcache.overall_hits::total 1893 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 1894 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1894 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1894 # number of overall hits
system.cpu.dcache.overall_hits::total 1894 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses
@ -423,42 +462,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
system.cpu.dcache.overall_misses::total 182 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6977500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 6977500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5011500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 5011500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 11989000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 11989000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 11989000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 11989000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses
system.cpu.dcache.demand_accesses::cpu.data 2076 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2076 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2076 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2076 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098882 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098882 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency
system.cpu.dcache.demand_miss_rate::cpu.data 0.087669 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.087669 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.087669 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.087669 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60673.913043 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60673.913043 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74798.507463 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74798.507463 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 65873.626374 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65873.626374 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 65873.626374 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -483,82 +522,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146
system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6370500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6370500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3194000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3194000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9564500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 9564500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9564500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 9564500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088564 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088564 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.070328 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070328 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.070328 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61849.514563 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61849.514563 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74279.069767 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74279.069767 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65510.273973 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65510.273973 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 3 # number of replacements
system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks.
system.cpu.icache.tags.replacements 4 # number of replacements
system.cpu.icache.tags.tagsinuse 162.122030 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 1926 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 323 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 5.962848 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 162.122030 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.079161 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.079161 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4806 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits
system.cpu.icache.overall_hits::total 1920 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses
system.cpu.icache.overall_misses::total 322 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency
system.cpu.icache.tags.tag_accesses 4821 # Number of tag accesses
system.cpu.icache.tags.data_accesses 4821 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 1926 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1926 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1926 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 1926 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 1926 # number of overall hits
system.cpu.icache.overall_hits::total 1926 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 323 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 323 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 323 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 323 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 323 # number of overall misses
system.cpu.icache.overall_misses::total 323 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23530000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 23530000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 23530000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 23530000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 23530000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 23530000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2249 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2249 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2249 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 2249 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 2249 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 2249 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143619 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.143619 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.143619 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.143619 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.143619 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.143619 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72848.297214 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 72848.297214 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 72848.297214 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72848.297214 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 72848.297214 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -567,62 +606,62 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 3 # number of writebacks
system.cpu.icache.writebacks::total 3 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency
system.cpu.icache.writebacks::writebacks 4 # number of writebacks
system.cpu.icache.writebacks::total 4 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 323 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 323 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 323 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 323 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 323 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23207000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 23207000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23207000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 23207000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23207000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 23207000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143619 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.143619 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143619 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.143619 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71848.297214 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71848.297214 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71848.297214 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71848.297214 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks.
system.cpu.l2cache.tags.tagsinuse 195.781809 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.113757 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.633330 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 41.148479 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004719 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001256 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005975 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses
system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits
system.cpu.l2cache.tags.tag_accesses 4197 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4197 # Number of data accesses
system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits
system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits
system.cpu.l2cache.overall_hits::total 39 # number of overall hits
system.cpu.l2cache.overall_hits::total 40 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses
@ -635,56 +674,56 @@ system.cpu.l2cache.demand_misses::total 429 # nu
system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses
system.cpu.l2cache.overall_misses::total 429 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3129500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3129500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22515500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 22515500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5956000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5956000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 22515500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9085500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 31601000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 22515500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9085500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 31601000 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 323 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 323 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses
system.cpu.l2cache.demand_accesses::total 469 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 323 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 469 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.944272 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.944272 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.944272 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses
system.cpu.l2cache.demand_miss_rate::total 0.914712 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.944272 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency
system.cpu.l2cache.overall_miss_rate::total 0.914712 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72779.069767 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72779.069767 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73821.311475 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73821.311475 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73530.864198 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73530.864198 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73662.004662 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73821.311475 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73270.161290 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73662.004662 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -711,76 +750,76 @@ system.cpu.l2cache.demand_mshr_misses::total 421
system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19465500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19465500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4696000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4696000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19465500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 26861000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19465500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 26861000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.944272 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.897655 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.944272 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_miss_rate::total 0.897655 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62779.069767 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62779.069767 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63821.311475 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63821.311475 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64328.767123 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64328.767123 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63821.311475 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63754.310345 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63802.850356 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_requests 473 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 51 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 426 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 323 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 650 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 942 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20928 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 30272 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 469 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.102345 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.303426 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 421 89.77% 89.77% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 48 10.23% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 469 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 484500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
@ -803,9 +842,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 421 # Request fanout histogram
system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 2236750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---------- End Simulation Statistics ----------

9
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -147,11 +149,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.checker]
type=O3Checker

1151
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
View file

File diff suppressed because it is too large Load diff

9
tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -147,8 +149,15 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache

1091
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -401,6 +403,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

3
tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -251,6 +253,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

7
tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -90,7 +92,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -168,7 +169,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -281,7 +281,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -316,6 +315,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -381,6 +381,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

9
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache

1093
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

2
tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

9
tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -146,11 +148,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache

1056
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -151,6 +153,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

3
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -150,6 +152,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

2
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

7
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -180,7 +180,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -215,6 +214,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -280,6 +280,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

9
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -151,11 +153,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache

1199
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -184,6 +186,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

2
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
View file

@ -4,6 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!

7
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -94,7 +96,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -146,7 +147,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -214,7 +214,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -249,6 +248,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -314,6 +314,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

9
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=true
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=2
useIndirect=true
[system.cpu.dcache]
type=Cache

1464
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
View file

File diff suppressed because it is too large Load diff

9
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -145,11 +147,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
indirectHashGHR=true
indirectHashTargets=true
indirectPathLength=3
indirectSets=256
indirectTagSize=16
indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
useIndirect=true
[system.cpu.dcache]
type=Cache

1186
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

3
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -150,6 +152,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

7
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -88,7 +90,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -130,7 +131,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -180,7 +180,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -215,6 +214,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -280,6 +280,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

2
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

3
tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -320,6 +322,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

7
tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -96,7 +98,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -173,7 +174,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -318,6 +318,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@ -343,7 +344,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -454,6 +454,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

2
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

2
tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0

3
tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -221,6 +223,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

7
tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -94,7 +96,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -136,7 +137,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -219,6 +219,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@ -244,7 +245,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -355,6 +355,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

3
tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -253,6 +255,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

7
tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -100,7 +102,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -151,7 +152,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -251,6 +251,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
@ -276,7 +277,6 @@ clk_domain=system.clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -387,6 +387,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

3
tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -251,6 +253,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

7
tests/quick/se/10.mcf/ref/arm/linux/simple-timing/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -90,7 +92,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
@ -168,7 +169,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
@ -281,7 +281,6 @@ clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
@ -316,6 +315,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@ -381,6 +381,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

3
tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -150,6 +152,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

3
tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
View file

@ -29,6 +29,8 @@ multi_thread=false
num_work_ids=16
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@ -184,6 +186,7 @@ clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4

Some files were not shown because too many files have changed in this diff Show more